gem5  v21.1.0.2
mmu.hh
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37 
38 #ifndef __ARCH_ARM_MMU_HH__
39 #define __ARCH_ARM_MMU_HH__
40 
41 #include "arch/arm/table_walker.hh"
42 #include "arch/arm/tlb.hh"
43 #include "arch/generic/mmu.hh"
44 
45 #include "params/ArmMMU.hh"
46 
47 namespace gem5
48 {
49 
50 namespace ArmISA {
51 
52 class MMU : public BaseMMU
53 {
54  protected:
55  ArmISA::TLB *
56  getDTBPtr() const
57  {
58  return static_cast<ArmISA::TLB *>(dtb);
59  }
60 
61  ArmISA::TLB *
62  getITBPtr() const
63  {
64  return static_cast<ArmISA::TLB *>(itb);
65  }
66 
67  TLB * getTlb(BaseMMU::Mode mode, bool stage2) const;
68 
69  protected:
72 
75 
80 
81  public:
82  enum TLBType
83  {
84  I_TLBS = 0x01,
85  D_TLBS = 0x10,
86  ALL_TLBS = 0x11
87  };
88 
89  MMU(const ArmMMUParams &p);
90 
91  void init() override;
92 
93  bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
94 
97 
100  bool stage2);
101 
104  BaseMMU::Mode mode, bool stage2);
105 
106  void translateTiming(const RequestPtr &req, ThreadContext *tc,
107  BaseMMU::Translation *translation, BaseMMU::Mode mode, bool stage2);
108 
110 
111  template <typename OP>
112  void
113  flush(const OP &tlbi_op)
114  {
115  if (tlbi_op.stage1Flush()) {
116  flushStage1(tlbi_op);
117  }
118 
119  if (tlbi_op.stage2Flush()) {
120  flushStage2(tlbi_op.makeStage2());
121  }
122  }
123 
124  template <typename OP>
125  void
126  flushStage1(const OP &tlbi_op)
127  {
128  iflush(tlbi_op);
129  dflush(tlbi_op);
130  }
131 
132  template <typename OP>
133  void
134  flushStage2(const OP &tlbi_op)
135  {
136  itbStage2->flush(tlbi_op);
137  dtbStage2->flush(tlbi_op);
138  }
139 
140  template <typename OP>
141  void
142  iflush(const OP &tlbi_op)
143  {
144  getITBPtr()->flush(tlbi_op);
145  }
146 
147  template <typename OP>
148  void
149  dflush(const OP &tlbi_op)
150  {
151  getDTBPtr()->flush(tlbi_op);
152  }
153 
154  void
155  flushAll() override
156  {
158  itbStage2->flushAll();
159  dtbStage2->flushAll();
160  }
161 
162  uint64_t
163  getAttr() const
164  {
165  return getDTBPtr()->getAttr();
166  }
167 };
168 
169 template<typename T>
170 MMU *
171 getMMUPtr(T *tc)
172 {
173  auto mmu = static_cast<MMU *>(tc->getMMUPtr());
174  assert(mmu);
175  return mmu;
176 }
177 
178 } // namespace ArmISA
179 } // namespace gem5
180 
181 #endif // __ARCH_ARM_MMU_HH__
gem5::ArmISA::MMU::itbWalker
TableWalker * itbWalker
Definition: mmu.hh:76
gem5::ArmISA::MMU::flush
void flush(const OP &tlbi_op)
Definition: mmu.hh:113
gem5::ArmISA::TableWalker::Port
Definition: table_walker.hh:869
gem5::ArmISA::MMU::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, bool stage2)
Definition: mmu.cc:118
gem5::ArmISA::MMU::getAttr
uint64_t getAttr() const
Definition: mmu.hh:163
gem5::BaseMMU::dtb
BaseTLB * dtb
Definition: mmu.hh:120
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::ArmISA::MMU::dtbStage2Walker
TableWalker * dtbStage2Walker
Definition: mmu.hh:79
gem5::ArmISA::MMU::iport
TableWalker::Port iport
Definition: mmu.hh:73
gem5::ArmISA::MMU::D_TLBS
@ D_TLBS
Definition: mmu.hh:85
gem5::ArmISA::TLB
Definition: tlb.hh:109
tlb.hh
gem5::ArmISA::MMU::getDTBPtr
ArmISA::TLB * getDTBPtr() const
Definition: mmu.hh:56
table_walker.hh
gem5::ArmISA::MMU::dtbWalker
TableWalker * dtbWalker
Definition: mmu.hh:77
gem5::ArmISA::MMU::TLBType
TLBType
Definition: mmu.hh:82
gem5::ArmISA::MMU::MMU
MMU(const ArmMMUParams &p)
Definition: mmu.cc:47
gem5::ArmISA::MMU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: mmu.cc:63
gem5::ArmISA::getMMUPtr
MMU * getMMUPtr(T *tc)
Definition: mmu.hh:171
gem5::ArmISA::MMU::flushAll
void flushAll() override
Definition: mmu.hh:155
gem5::BaseMMU
Definition: mmu.hh:50
gem5::ArmISA::MMU::ALL_TLBS
@ ALL_TLBS
Definition: mmu.hh:86
gem5::ArmISA::MMU::itbStage2Walker
TableWalker * itbStage2Walker
Definition: mmu.hh:78
gem5::ArmISA::MMU::dport
TableWalker::Port dport
Definition: mmu.hh:74
gem5::ArmISA::MMU::itbStage2
TLB * itbStage2
Definition: mmu.hh:70
gem5::ArmISA::MMU::iflush
void iflush(const OP &tlbi_op)
Definition: mmu.hh:142
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::MMU::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, bool stage2)
Definition: mmu.cc:125
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ArmISA::TLB::flush
void flush(const TLBIALL &tlbi_op)
Reset the entire TLB.
Definition: tlb.cc:292
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::MMU::flushStage2
void flushStage2(const OP &tlbi_op)
Definition: mmu.hh:134
mmu.hh
gem5::ArmISA::MMU::dflush
void dflush(const OP &tlbi_op)
Definition: mmu.hh:149
gem5::ArmISA::MMU::translateFunctional
bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr)
Definition: mmu.cc:96
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::TLB::flushAll
void flushAll() override
Reset the entire TLB.
Definition: tlb.cc:274
gem5::ArmISA::MMU::getITBPtr
ArmISA::TLB * getITBPtr() const
Definition: mmu.hh:62
gem5::BaseMMU::Translation
Definition: mmu.hh:55
gem5::ArmISA::MMU::getTlb
TLB * getTlb(BaseMMU::Mode mode, bool stage2) const
Definition: mmu.cc:80
gem5::ArmISA::TableWalker
Definition: table_walker.hh:66
gem5::ArmISA::TLB::getAttr
uint64_t getAttr() const
Definition: tlb.hh:349
gem5::ArmISA::MMU::flushStage1
void flushStage1(const OP &tlbi_op)
Definition: mmu.hh:126
gem5::BaseMMU::flushAll
virtual void flushAll()
Definition: mmu.cc:51
gem5::ArmISA::TLB::ArmTranslationType
ArmTranslationType
Definition: tlb.hh:128
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::ArmISA::MMU::dtbStage2
TLB * dtbStage2
Definition: mmu.hh:71
gem5::BaseMMU::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
Definition: mmu.cc:65
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::MMU
Definition: mmu.hh:52
gem5::ArmISA::MMU::I_TLBS
@ I_TLBS
Definition: mmu.hh:84
gem5::ArmISA::MMU::invalidateMiscReg
void invalidateMiscReg(TLBType type=ALL_TLBS)
Definition: mmu.cc:132
gem5::BaseMMU::itb
BaseTLB * itb
Definition: mmu.hh:121
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73

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