gem5  v21.2.1.1
mmu.hh
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40 
41 #ifndef __ARCH_ARM_MMU_HH__
42 #define __ARCH_ARM_MMU_HH__
43 
44 #include "arch/arm/page_size.hh"
45 #include "arch/arm/tlb.hh"
46 #include "arch/generic/mmu.hh"
47 
48 #include "enums/ArmLookupLevel.hh"
49 
50 #include "params/ArmMMU.hh"
51 
52 namespace gem5
53 {
54 
55 namespace ArmISA {
56 
57 class TableWalker;
58 
59 class MMU : public BaseMMU
60 {
61  protected:
62  using LookupLevel = enums::ArmLookupLevel;
63 
64  ArmISA::TLB *
65  getDTBPtr() const
66  {
67  return static_cast<ArmISA::TLB *>(dtb);
68  }
69 
70  ArmISA::TLB *
71  getITBPtr() const
72  {
73  return static_cast<ArmISA::TLB *>(itb);
74  }
75 
76  TLB * getTlb(BaseMMU::Mode mode, bool stage2) const;
77  TableWalker * getTableWalker(BaseMMU::Mode mode, bool stage2) const;
78 
79  protected:
82 
87 
88  public:
91  Mode mode, Request::Flags flags) override
92  {
94  PageBytes, start, size, tc, this, mode, flags));
95  }
96 
97  enum ArmFlags
98  {
100 
101  AlignByte = 0x0,
103  AlignWord = 0x2,
107 
109  // Priv code operating as if it wasn't
110  UserMode = 0x10
111  };
112 
114  {
116  S1CTran = 0x1,
117  HypMode = 0x2,
118  // Secure code operating as if it wasn't (required by some Address
119  // Translate operations)
120  S1S2NsTran = 0x4,
121  // Address translation instructions (eg AT S1E0R_Xt) need to be handled
122  // in special ways during translation because they could need to act
123  // like a different EL than the current EL. The following flags are
124  // for these instructions
125  S1E0Tran = 0x8,
126  S1E1Tran = 0x10,
127  S1E2Tran = 0x20,
128  S1E3Tran = 0x40,
129  S12E0Tran = 0x80,
130  S12E1Tran = 0x100
131  };
132 
133  struct CachedState {
134  explicit CachedState(MMU *_mmu, bool stage2)
135  : mmu(_mmu), isStage2(stage2)
136  {}
137 
138  void updateMiscReg(ThreadContext *tc, ArmTranslationType tran_type);
139 
142  vmid_t getVMID(ThreadContext *tc) const;
143 
145  bool isStage2 = false;
146  CPSR cpsr = 0;
147  bool aarch64 = false;
149  SCTLR sctlr = 0;
150  SCR scr = 0;
151  bool isPriv = false;
152  bool isSecure = false;
153  bool isHyp = false;
154  TTBCR ttbcr = 0;
155  uint16_t asid = 0;
157  PRRR prrr = 0;
158  NMRR nmrr = 0;
159  HCR hcr = 0;
160  uint32_t dacr = 0;
161  bool miscRegValid = false;
163 
164  // Indicates whether a stage 2 lookup is also required
165  bool stage2Req = false;
166 
167  // Indicates whether a stage 2 lookup of the table descriptors is
168  // required. Certain address translation instructions will
169  // intercept the IPA but the table descriptors still need to be
170  // translated by the stage2.
171  bool stage2DescReq = false;
172 
173  // Indicates whether all translation requests should
174  // be routed directly to the stage 2 TLB
175  bool directToStage2 = false;
176  };
177 
178  MMU(const ArmMMUParams &p);
179 
180  void init() override;
181 
183 
192  bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
193 
195  BaseMMU::Mode mode) override;
196 
203 
205  BaseMMU::Mode mode, ArmTranslationType tran_type, bool stage2);
206 
207  Fault
209  ThreadContext *tc, Mode mode) override
210  {
211  return translateAtomic(req, tc, mode, NormalTran);
212  }
214  BaseMMU::Mode mode, ArmTranslationType tran_type, bool stage2);
216  ArmTranslationType tran_type);
217 
218  void
220  Translation *translation, Mode mode) override
221  {
222  translateTiming(req, tc, translation, mode, NormalTran, false);
223  }
224  void translateTiming(const RequestPtr &req, ThreadContext *tc,
225  BaseMMU::Translation *translation, BaseMMU::Mode mode, bool stage2);
226  void translateTiming(
227  const RequestPtr &req, ThreadContext *tc,
228  Translation *translation, Mode mode,
229  ArmTranslationType tran_type, bool stage2);
230 
232  ArmTranslationType tran_type, Addr vaddr, bool long_desc_format,
233  CachedState &state);
235  Translation *translation, bool &delay, bool timing, bool functional,
236  Addr vaddr, ArmFault::TranMethod tranMethod,
237  CachedState &state);
238 
240  Translation *translation, bool &delay,
241  bool timing, ArmTranslationType tran_type, bool functional,
242  CachedState &state);
244  Translation *translation, bool &delay, bool timing,
245  CachedState &state);
246 
248  Translation *translation, Mode mode, ArmTranslationType tran_type,
249  bool call_from_s2);
251  Translation *translation, Mode mode, ArmTranslationType tran_type,
252  bool call_from_s2, CachedState &state);
254  const RequestPtr &req,
255  ThreadContext *tc, Mode mode) const override;
256 
257  void drainResume() override;
258 
259  void takeOverFrom(BaseMMU *old_mmu) override;
260 
261  void invalidateMiscReg();
262 
263  template <typename OP>
264  void
265  flush(const OP &tlbi_op)
266  {
267  if (tlbi_op.stage1Flush()) {
268  flushStage1(tlbi_op);
269  }
270 
271  if (tlbi_op.stage2Flush()) {
272  flushStage2(tlbi_op.makeStage2());
273  }
274  }
275 
276  template <typename OP>
277  void
278  flushStage1(const OP &tlbi_op)
279  {
280  for (auto tlb : instruction) {
281  static_cast<TLB*>(tlb)->flush(tlbi_op);
282  }
283  for (auto tlb : data) {
284  static_cast<TLB*>(tlb)->flush(tlbi_op);
285  }
286  for (auto tlb : unified) {
287  static_cast<TLB*>(tlb)->flush(tlbi_op);
288  }
289  }
290 
291  template <typename OP>
292  void
293  flushStage2(const OP &tlbi_op)
294  {
295  itbStage2->flush(tlbi_op);
296  dtbStage2->flush(tlbi_op);
297  }
298 
299  template <typename OP>
300  void
301  iflush(const OP &tlbi_op)
302  {
303  for (auto tlb : instruction) {
304  static_cast<TLB*>(tlb)->flush(tlbi_op);
305  }
306  for (auto tlb : unified) {
307  static_cast<TLB*>(tlb)->flush(tlbi_op);
308  }
309  }
310 
311  template <typename OP>
312  void
313  dflush(const OP &tlbi_op)
314  {
315  for (auto tlb : data) {
316  static_cast<TLB*>(tlb)->flush(tlbi_op);
317  }
318  for (auto tlb : unified) {
319  static_cast<TLB*>(tlb)->flush(tlbi_op);
320  }
321  }
322 
323  void
324  flushAll() override
325  {
327  itbStage2->flushAll();
328  dtbStage2->flushAll();
329  }
330 
331  uint64_t
332  getAttr() const
333  {
334  return _attr;
335  }
336 
339  void
340  setAttr(uint64_t attr)
341  {
342  _attr = attr;
343  }
344 
345  const ArmRelease* release() const { return _release; }
346 
347  bool hasWalkCache() const { return _hasWalkCache; }
348 
355 
356  public:
370  TlbEntry *lookup(Addr vpn, uint16_t asn, vmid_t vmid, bool hyp,
371  bool secure, bool functional,
372  bool ignore_asn, ExceptionLevel target_el,
373  bool in_host, bool stage2, BaseMMU::Mode mode);
374 
375  Fault getTE(TlbEntry **te, const RequestPtr &req,
376  ThreadContext *tc, Mode mode,
377  Translation *translation, bool timing, bool functional,
378  bool is_secure, ArmTranslationType tran_type,
379  bool stage2);
380  Fault getTE(TlbEntry **te, const RequestPtr &req,
381  ThreadContext *tc, Mode mode,
382  Translation *translation, bool timing, bool functional,
383  bool is_secure, ArmTranslationType tran_type,
384  CachedState &state);
385 
386  Fault getResultTe(TlbEntry **te, const RequestPtr &req,
387  ThreadContext *tc, Mode mode,
388  Translation *translation, bool timing,
389  bool functional, TlbEntry *mergeTe,
390  CachedState &state);
391 
393  bool stage2);
395  CachedState &state);
397  ThreadContext *tc, bool stage2);
399  ThreadContext *tc, CachedState &state);
400  protected:
401  bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req,
402  Mode mode, const bool is_priv, CachedState &state);
403 
404  bool faultPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req,
405  Mode mode, const bool is_priv, CachedState &state);
406 
408  TlbEntry *te, const RequestPtr &req, Mode mode,
409  ThreadContext *tc, CachedState &state, bool r, bool w, bool x);
410 
412  TlbEntry *te, const RequestPtr &req, Mode mode,
413  ThreadContext *tc, CachedState &state, bool r, bool w, bool x);
414 
415  public: /* Testing */
417 
419 
422  Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode,
424  LookupLevel lookup_level, bool stage2);
425  Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode,
427  LookupLevel lookup_level, CachedState &state);
428 
429  protected:
430  bool checkWalkCache() const;
431 
432  bool isCompleteTranslation(TlbEntry *te) const;
433 
435  ThreadContext *tc, ArmTranslationType tran_type,
436  bool stage2);
437 
438  protected:
440 
441  public:
443 
444  protected:
445  uint64_t _attr; // Memory attributes for last accessed TLB entry
446 
447  // Cached copies of system-level properties
450  uint8_t physAddrRange;
451 
453 
455 
456  struct Stats : public statistics::Group
457  {
458  Stats(statistics::Group *parent);
459  // Access Stats
464  } stats;
465 
466 };
467 
468 template<typename T>
469 MMU *
470 getMMUPtr(T *tc)
471 {
472  auto mmu = static_cast<MMU *>(tc->getMMUPtr());
473  assert(mmu);
474  return mmu;
475 }
476 
477 } // namespace ArmISA
478 } // namespace gem5
479 
480 #endif // __ARCH_ARM_MMU_HH__
gem5::ArmISA::MMU::itbWalker
TableWalker * itbWalker
Definition: mmu.hh:83
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::ArmISA::MMU::S12E0Tran
@ S12E0Tran
Definition: mmu.hh:129
gem5::ArmISA::tlb
Bitfield< 59, 56 > tlb
Definition: misc_types.hh:92
gem5::ArmISA::MMU::finalizePhysical
Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, Mode mode) const override
Definition: mmu.cc:203
gem5::ArmISA::MMU::flush
void flush(const OP &tlbi_op)
Definition: mmu.hh:265
gem5::ArmISA::MMU::haveLargeAsid64
bool haveLargeAsid64
Definition: mmu.hh:449
gem5::ArmISA::MMU::S12E1Tran
@ S12E1Tran
Definition: mmu.hh:130
gem5::ArmISA::MMU::LookupLevel
enums::ArmLookupLevel LookupLevel
Definition: mmu.hh:62
gem5::MipsISA::w
Bitfield< 0 > w
Definition: pra_constants.hh:281
gem5::ArmISA::MMU::CachedState::nmrr
NMRR nmrr
Definition: mmu.hh:158
gem5::ArmISA::MMU::s2PermBits64
std::pair< bool, bool > s2PermBits64(TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, CachedState &state, bool r, bool w, bool x)
Definition: mmu.cc:576
gem5::ArmISA::MMU::Stats::domainFaults
statistics::Scalar domainFaults
Definition: mmu.hh:462
gem5::ArmISA::MMU::getTE
Fault getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, ArmTranslationType tran_type, bool stage2)
Definition: mmu.cc:1397
gem5::ArmISA::MMU::getAttr
uint64_t getAttr() const
Definition: mmu.hh:332
gem5::ArmISA::MMU::AlignDoubleWord
@ AlignDoubleWord
Definition: mmu.hh:104
gem5::BaseMMU::dtb
BaseTLB * dtb
Definition: mmu.hh:158
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::ArmISA::attr
attr
Definition: misc_types.hh:656
gem5::ArmISA::MMU::m5opRange
AddrRange m5opRange
Definition: mmu.hh:452
gem5::ArmISA::MMU::AlignByte
@ AlignByte
Definition: mmu.hh:101
gem5::ArmISA::domain
Bitfield< 7, 4 > domain
Definition: misc_types.hh:424
gem5::ArmISA::MMU::dtbStage2Walker
TableWalker * dtbStage2Walker
Definition: mmu.hh:86
gem5::ArmISA::vmid_t
uint16_t vmid_t
Definition: types.hh:57
gem5::ArmISA::MMU::CachedState::updateMiscReg
void updateMiscReg(ThreadContext *tc, ArmTranslationType tran_type)
Definition: mmu.cc:1201
gem5::ArmISA::MMU::S1E0Tran
@ S1E0Tran
Definition: mmu.hh:125
gem5::ArmISA::TLB
Definition: tlb.hh:115
gem5::ArmISA::MMU::S1CTran
@ S1CTran
Definition: mmu.hh:116
gem5::ArmISA::MMU::CachedState::vmid
vmid_t vmid
Definition: mmu.hh:156
gem5::ArmISA::MMU::getResultTe
Fault getResultTe(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, TlbEntry *mergeTe, CachedState &state)
Definition: mmu.cc:1489
tlb.hh
gem5::ArmISA::MMU::S1E3Tran
@ S1E3Tran
Definition: mmu.hh:128
gem5::ArmISA::MMU::AllowUnaligned
@ AllowUnaligned
Definition: mmu.hh:108
gem5::ArmISA::MMU::ArmFlags
ArmFlags
Definition: mmu.hh:97
gem5::ArmISA::MMU::_hasWalkCache
bool _hasWalkCache
Definition: mmu.hh:454
gem5::ArmISA::MMU::getDTBPtr
ArmISA::TLB * getDTBPtr() const
Definition: mmu.hh:65
gem5::ArmISA::MMU::dtbWalker
TableWalker * dtbWalker
Definition: mmu.hh:84
gem5::ArmISA::TlbTestInterface
Definition: tlb.hh:79
gem5::ArmISA::MMU::testWalk
Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, TlbEntry::DomainType domain, LookupLevel lookup_level, bool stage2)
Definition: mmu.cc:1607
gem5::ArmISA::MMU::MMU
MMU(const ArmMMUParams &p)
Definition: mmu.cc:59
gem5::ArmISA::MMU::CachedState::ttbcr
TTBCR ttbcr
Definition: mmu.hh:154
gem5::ArmISA::MMU::Stats
Definition: mmu.hh:456
gem5::ArmISA::TlbEntry
Definition: pagetable.hh:165
gem5::ArmISA::MMU::AlignOctWord
@ AlignOctWord
Definition: mmu.hh:106
gem5::ArmISA::MMU::S1E2Tran
@ S1E2Tran
Definition: mmu.hh:127
gem5::ArmISA::MMU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: mmu.cc:92
gem5::ArmISA::MMU::_attr
uint64_t _attr
Definition: mmu.hh:445
gem5::ArmISA::MMU::CachedState::CachedState
CachedState(MMU *_mmu, bool stage2)
Definition: mmu.hh:134
gem5::ArmISA::getMMUPtr
MMU * getMMUPtr(T *tc)
Definition: mmu.hh:470
gem5::ArmISA::TlbEntry::DomainType
DomainType
Definition: pagetable.hh:177
gem5::ArmISA::MMU::flushAll
void flushAll() override
Definition: mmu.hh:324
gem5::ArmISA::MMU::Stats::permsFaults
statistics::Scalar permsFaults
Definition: mmu.hh:463
gem5::ArmISA::MMU::CachedState::curTranType
ArmTranslationType curTranType
Definition: mmu.hh:162
gem5::BaseMMU
Definition: mmu.hh:53
gem5::ArmISA::MMU::itbStage2Walker
TableWalker * itbStage2Walker
Definition: mmu.hh:85
gem5::BaseMMU::translateFunctional
virtual Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
Definition: mmu.cc:118
gem5::ArmISA::MMU::translateFs
Fault translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, ArmTranslationType tran_type, bool functional, CachedState &state)
Definition: mmu.cc:940
gem5::ArmISA::MMU::CachedState::cpsr
CPSR cpsr
Definition: mmu.hh:146
gem5::ArmISA::MMU::UserMode
@ UserMode
Definition: mmu.hh:110
gem5::ArmISA::MMU::itbStage2
TLB * itbStage2
Definition: mmu.hh:80
gem5::ArmISA::MMU::CachedState::aarch64
bool aarch64
Definition: mmu.hh:147
gem5::ArmISA::MMU::translateComplete
Fault translateComplete(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tran_type, bool call_from_s2)
Definition: mmu.cc:1091
gem5::ArmISA::pa
Bitfield< 39, 12 > pa
Definition: misc_types.hh:657
gem5::ArmISA::MMU::CachedState::mmu
MMU * mmu
Definition: mmu.hh:144
gem5::Flags< FlagsType >
gem5::ArmISA::MMU::getTableWalker
TableWalker * getTableWalker(BaseMMU::Mode mode, bool stage2) const
Definition: mmu.cc:153
gem5::ArmISA::MMU::CachedState::isPriv
bool isPriv
Definition: mmu.hh:151
gem5::ArmISA::MMU::CachedState
Definition: mmu.hh:133
gem5::ArmISA::MMU::Stats::prefetchFaults
statistics::Scalar prefetchFaults
Definition: mmu.hh:461
gem5::ArmISA::MMU::iflush
void iflush(const OP &tlbi_op)
Definition: mmu.hh:301
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::MMU::setTestInterface
void setTestInterface(SimObject *ti)
Definition: mmu.cc:1583
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::MMU::AlignWord
@ AlignWord
Definition: mmu.hh:103
gem5::BaseMMU::unified
std::set< BaseTLB * > unified
Definition: mmu.hh:183
gem5::ArmISA::MMU::NormalTran
@ NormalTran
Definition: mmu.hh:115
gem5::ArmISA::MMU::CachedState::prrr
PRRR prrr
Definition: mmu.hh:157
gem5::ArmISA::MMU::AlignQuadWord
@ AlignQuadWord
Definition: mmu.hh:105
gem5::ArmISA::MMU::tranTypeEL
static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type)
Determine the EL to use for the purpose of a translation given a specific translation type.
Definition: mmu.cc:1368
gem5::ArmISA::MMU::translateSe
Fault translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, CachedState &state)
Definition: mmu.cc:233
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ArmISA::MMU::CachedState::dacr
uint32_t dacr
Definition: mmu.hh:160
gem5::ArmISA::TLB::flush
void flush(const TLBIALL &tlbi_op)
Reset the entire TLB.
Definition: tlb.cc:318
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::MMU::flushStage2
void flushStage2(const OP &tlbi_op)
Definition: mmu.hh:293
mmu.hh
gem5::ArmISA::MMU::CachedState::asid
uint16_t asid
Definition: mmu.hh:155
gem5::ArmISA::MMU::s1State
CachedState s1State
Definition: mmu.hh:442
gem5::ArmISA::MMU::AlignmentMask
@ AlignmentMask
Definition: mmu.hh:99
gem5::ArmISA::MMU::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) override
Definition: mmu.hh:208
gem5::ArmISA::MMU::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: mmu.cc:130
gem5::ArmISA::te
Bitfield< 30 > te
Definition: misc_types.hh:338
gem5::ArmISA::MMU::dflush
void dflush(const OP &tlbi_op)
Definition: mmu.hh:313
gem5::ArmISA::MMU::CachedState::isSecure
bool isSecure
Definition: mmu.hh:152
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
std::pair
STL pair class.
Definition: stl.hh:58
gem5::ArmISA::MMU::miscRegContext
ContextID miscRegContext
Definition: mmu.hh:439
gem5::ArmISA::MMU::translateMmuOff
Fault translateMmuOff(ThreadContext *tc, const RequestPtr &req, Mode mode, ArmTranslationType tran_type, Addr vaddr, bool long_desc_format, CachedState &state)
Definition: mmu.cc:793
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::TLB::flushAll
void flushAll() override
Reset the entire TLB.
Definition: tlb.cc:298
gem5::ArmISA::MMU::CachedState::aarch64EL
ExceptionLevel aarch64EL
Definition: mmu.hh:148
gem5::ArmISA::MMU::checkWalkCache
bool checkWalkCache() const
Definition: mmu.cc:111
gem5::ArmISA::MMU::HypMode
@ HypMode
Definition: mmu.hh:117
gem5::MipsISA::ti
Bitfield< 30 > ti
Definition: pra_constants.hh:179
gem5::BaseMMU::instruction
std::set< BaseTLB * > instruction
It is possible from the MMU to traverse the entire hierarchy of TLBs, starting from the DTB and ITB (...
Definition: mmu.hh:181
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:276
gem5::ArmISA::MMU::CachedState::hcr
HCR hcr
Definition: mmu.hh:159
gem5::ArmRelease
Definition: system.hh:68
gem5::ArmISA::MMU::faultPAN
bool faultPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode, const bool is_priv, CachedState &state)
Definition: mmu.cc:738
gem5::ArmISA::MMU::CachedState::miscRegValid
bool miscRegValid
Definition: mmu.hh:161
gem5::ArmISA::MMU::getITBPtr
ArmISA::TLB * getITBPtr() const
Definition: mmu.hh:71
gem5::BaseMMU::Translation
Definition: mmu.hh:58
gem5::ArmISA::MMU::getTlb
TLB * getTlb(BaseMMU::Mode mode, bool stage2) const
Definition: mmu.cc:137
gem5::ArmISA::MMU::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) override
Definition: mmu.hh:219
gem5::ArmISA::MMU::physAddrRange
uint8_t physAddrRange
Definition: mmu.hh:450
gem5::ArmISA::MMU::ArmTranslationType
ArmTranslationType
Definition: mmu.hh:113
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
gem5::ArmISA::MMU::S1S2NsTran
@ S1S2NsTran
Definition: mmu.hh:120
gem5::ArmISA::TableWalker
Definition: table_walker.hh:66
gem5::ArmISA::ArmFault::TranMethod
TranMethod
Definition: faults.hh:150
gem5::RiscvISA::x
Bitfield< 3 > x
Definition: pagetable.hh:73
gem5::ArmISA::MMU::AlignHalfWord
@ AlignHalfWord
Definition: mmu.hh:102
gem5::ArmISA::MMU::test
TlbTestInterface * test
Definition: mmu.hh:416
gem5::ArmISA::MMU::testTranslation
Fault testTranslation(const RequestPtr &req, Mode mode, TlbEntry::DomainType domain, CachedState &state)
Definition: mmu.cc:1595
gem5::ArmISA::MMU::translateFunctional
TranslationGenPtr translateFunctional(Addr start, Addr size, ThreadContext *tc, Mode mode, Request::Flags flags) override
Returns a translation generator for a region of virtual addresses, instead of directly translating a ...
Definition: mmu.hh:90
gem5::ArmISA::MMU::checkPAN
bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode, const bool is_priv, CachedState &state)
Definition: mmu.cc:763
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::ArmISA::MMU::CachedState::getVMID
vmid_t getVMID(ThreadContext *tc) const
Returns the current VMID (information stored in the VTTBR_EL2 register)
Definition: mmu.cc:1132
gem5::ArmISA::MMU::checkPermissions
Fault checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode, bool stage2)
Definition: mmu.cc:274
gem5::ArmISA::PageBytes
const Addr PageBytes
Definition: page_size.hh:53
gem5::ArmISA::MMU::flushStage1
void flushStage1(const OP &tlbi_op)
Definition: mmu.hh:278
gem5::BaseMMU::flushAll
virtual void flushAll()
Definition: mmu.cc:81
gem5::ArmISA::MMU::updateMiscReg
CachedState & updateMiscReg(ThreadContext *tc, ArmTranslationType tran_type, bool stage2)
Definition: mmu.cc:1161
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::ArmISA::MMU::CachedState::isHyp
bool isHyp
Definition: mmu.hh:153
gem5::ArmISA::MMU::invalidateMiscReg
void invalidateMiscReg()
Definition: mmu.cc:197
gem5::ArmISA::MMU::CachedState::sctlr
SCTLR sctlr
Definition: mmu.hh:149
gem5::ArmISA::MMU::setAttr
void setAttr(uint64_t attr)
Accessor functions for memory attributes for last accessed TLB entry.
Definition: mmu.hh:340
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::ArmISA::MMU::release
const ArmRelease * release() const
Definition: mmu.hh:345
gem5::ArmISA::MMU::S1E1Tran
@ S1E1Tran
Definition: mmu.hh:126
gem5::ArmISA::MMU::CachedState::stage2Req
bool stage2Req
Definition: mmu.hh:165
gem5::ArmISA::MMU::CachedState::isStage2
bool isStage2
Definition: mmu.hh:145
page_size.hh
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::ArmISA::MMU::takeOverFrom
void takeOverFrom(BaseMMU *old_mmu) override
Definition: mmu.cc:1569
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:81
gem5::ArmISA::MMU::dtbStage2
TLB * dtbStage2
Definition: mmu.hh:81
gem5::ArmISA::MMU::translateMmuOn
Fault translateMmuOn(ThreadContext *tc, const RequestPtr &req, Mode mode, Translation *translation, bool &delay, bool timing, bool functional, Addr vaddr, ArmFault::TranMethod tranMethod, CachedState &state)
Definition: mmu.cc:868
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::MMU::CachedState::scr
SCR scr
Definition: mmu.hh:150
gem5::ArmISA::MMU::_release
const ArmRelease * _release
Definition: mmu.hh:448
gem5::ArmISA::MMU::CachedState::stage2DescReq
bool stage2DescReq
Definition: mmu.hh:171
gem5::ArmISA::MMU::stats
gem5::ArmISA::MMU::Stats stats
gem5::ArmISA::MMU
Definition: mmu.hh:59
gem5::ArmISA::MMU::hasWalkCache
bool hasWalkCache() const
Definition: mmu.hh:347
gem5::ArmISA::MMU::isCompleteTranslation
bool isCompleteTranslation(TlbEntry *te) const
Definition: mmu.cc:1563
gem5::ArmISA::MMU::Stats::Stats
Stats(statistics::Group *parent)
Definition: mmu.cc:1628
gem5::ArmISA::MMU::Stats::alignFaults
statistics::Scalar alignFaults
Definition: mmu.hh:460
gem5::ArmISA::MMU::lookup
TlbEntry * lookup(Addr vpn, uint16_t asn, vmid_t vmid, bool hyp, bool secure, bool functional, bool ignore_asn, ExceptionLevel target_el, bool in_host, bool stage2, BaseMMU::Mode mode)
Lookup an entry in the TLB.
Definition: mmu.cc:1407
gem5::BaseMMU::data
std::set< BaseTLB * > data
Definition: mmu.hh:182
gem5::TranslationGenPtr
std::unique_ptr< TranslationGen > TranslationGenPtr
Definition: translation_gen.hh:128
gem5::ArmISA::MMU::s2State
CachedState s2State
Definition: mmu.hh:442
gem5::BaseMMU::itb
BaseTLB * itb
Definition: mmu.hh:159
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
gem5::BaseMMU::MMUTranslationGen
Definition: mmu.hh:126
gem5::ArmISA::MMU::checkPermissions64
Fault checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, bool stage2)
Definition: mmu.cc:460
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::ArmISA::MMU::CachedState::directToStage2
bool directToStage2
Definition: mmu.hh:175
gem5::ArmISA::MMU::s1PermBits64
std::pair< bool, bool > s1PermBits64(TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, CachedState &state, bool r, bool w, bool x)
Definition: mmu.cc:616

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