GPU TranslationState: this currently is a somewhat bastardization of the usage of SenderState, whereby the receiver of a packet is not usually supposed to need to look at the contents of the senderState, you're really only supposed to look at what you pushed on, pop it off, and send it back. More...
#include <gpu_translation_state.hh>
Public Member Functions | |
| GpuTranslationState (BaseMMU::Mode tlb_mode, ThreadContext *_tc, bool _prefetch=false, Packet::SenderState *_saved=nullptr) | |
| GpuTranslationState (BaseMMU::Mode tlb_mode, bool _prefetch=false, Packet::SenderState *_saved=nullptr) | |
 Public Member Functions inherited from gem5::Packet::SenderState | |
| SenderState () | |
| virtual | ~SenderState () |
Public Attributes | |
| BaseMMU::Mode | tlbMode |
| ThreadContext * | tc |
| int | deviceId |
| int | pasId |
| Serializable * | tlbEntry |
| bool | isPrefetch |
| uint64_t | issueTime |
| std::vector< ResponsePort * > | ports |
| std::vector< int > | reqCnt |
| int | hitLevel |
| Packet::SenderState * | saved |
| Public Attributes inherited from gem5::Packet::SenderState | |
| SenderState * | predecessor |
Detailed Description
GPU TranslationState: this currently is a somewhat bastardization of the usage of SenderState, whereby the receiver of a packet is not usually supposed to need to look at the contents of the senderState, you're really only supposed to look at what you pushed on, pop it off, and send it back.
However, since there is state that we want to pass to the TLBs using the send/recv Timing/Functional/etc. APIs, which don't allow for new arguments, we need a common TLB senderState to pass between TLBs, both "forwards" and "backwards."
So, basically, the rule is that any packet received by a TLB port (cpuside OR memside) must be safely castable to a GpuTranslationState.
Definition at line 58 of file gpu_translation_state.hh.
Constructor & Destructor Documentation
◆ GpuTranslationState() [1/2]
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inline |
Definition at line 88 of file gpu_translation_state.hh.
◆ GpuTranslationState() [2/2]
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inline |
Definition at line 95 of file gpu_translation_state.hh.
Member Data Documentation
◆ deviceId
| int gem5::GpuTranslationState::deviceId |
Definition at line 65 of file gpu_translation_state.hh.
Referenced by gem5::VegaISA::GpuTLB::translationReturn().
◆ hitLevel
| int gem5::GpuTranslationState::hitLevel |
Definition at line 85 of file gpu_translation_state.hh.
Referenced by gem5::X86ISA::GpuTLB::issueTLBLookup(), gem5::VegaISA::GpuTLB::issueTLBLookup(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::VegaISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::ComputeUnit::DTLBPort::recvTimingResp(), gem5::ComputeUnit::sendRequest(), gem5::TLBCoalescer::updatePhysAddresses(), and gem5::VegaTLBCoalescer::updatePhysAddresses().
◆ isPrefetch
| bool gem5::GpuTranslationState::isPrefetch |
Definition at line 75 of file gpu_translation_state.hh.
Referenced by gem5::TLBCoalescer::canCoalesce(), gem5::VegaTLBCoalescer::canCoalesce(), gem5::X86ISA::GpuTLB::handleFuncTranslationReturn(), gem5::VegaISA::GpuTLB::handleFuncTranslationReturn(), gem5::VegaISA::GpuTLB::handleTranslationReturn(), gem5::X86ISA::GpuTLB::issueTLBLookup(), gem5::VegaISA::GpuTLB::issueTLBLookup(), gem5::TLBCoalescer::processProbeTLBEvent(), gem5::VegaTLBCoalescer::processProbeTLBEvent(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::TLBCoalescer::CpuSidePort::recvFunctional(), gem5::VegaISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::VegaTLBCoalescer::CpuSidePort::recvFunctional(), gem5::TLBCoalescer::CpuSidePort::recvTimingReq(), gem5::VegaTLBCoalescer::CpuSidePort::recvTimingReq(), gem5::X86ISA::GpuTLB::translationReturn(), gem5::VegaISA::GpuTLB::translationReturn(), gem5::TLBCoalescer::updatePhysAddresses(), and gem5::VegaTLBCoalescer::updatePhysAddresses().
◆ issueTime
| uint64_t gem5::GpuTranslationState::issueTime |
Definition at line 77 of file gpu_translation_state.hh.
Referenced by gem5::TLBCoalescer::CpuSidePort::recvTimingReq(), and gem5::VegaTLBCoalescer::CpuSidePort::recvTimingReq().
◆ pasId
| int gem5::GpuTranslationState::pasId |
Definition at line 66 of file gpu_translation_state.hh.
Referenced by gem5::VegaISA::GpuTLB::translationReturn().
◆ ports
| std::vector<ResponsePort*> gem5::GpuTranslationState::ports |
Definition at line 79 of file gpu_translation_state.hh.
Referenced by gem5::TLBCoalescer::CpuSidePort::recvTimingReq(), gem5::VegaTLBCoalescer::CpuSidePort::recvTimingReq(), gem5::ComputeUnit::DTLBPort::recvTimingResp(), gem5::ComputeUnit::ITLBPort::recvTimingResp(), gem5::ComputeUnit::ScalarDTLBPort::recvTimingResp(), gem5::TLBCoalescer::updatePhysAddresses(), and gem5::VegaTLBCoalescer::updatePhysAddresses().
◆ reqCnt
| std::vector<int> gem5::GpuTranslationState::reqCnt |
Definition at line 83 of file gpu_translation_state.hh.
Referenced by gem5::TLBCoalescer::canCoalesce(), gem5::VegaTLBCoalescer::canCoalesce(), gem5::VegaISA::GpuTLB::handleTranslationReturn(), gem5::X86ISA::GpuTLB::issueTLBLookup(), gem5::VegaISA::GpuTLB::issueTLBLookup(), gem5::TLBCoalescer::processProbeTLBEvent(), gem5::VegaTLBCoalescer::processProbeTLBEvent(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::VegaISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::TLBCoalescer::CpuSidePort::recvTimingReq(), gem5::VegaTLBCoalescer::CpuSidePort::recvTimingReq(), gem5::X86ISA::GpuTLB::translationReturn(), gem5::VegaISA::GpuTLB::translationReturn(), gem5::TLBCoalescer::updatePhysAddresses(), and gem5::VegaTLBCoalescer::updatePhysAddresses().
◆ saved
| Packet::SenderState* gem5::GpuTranslationState::saved |
Definition at line 86 of file gpu_translation_state.hh.
Referenced by gem5::ComputeUnit::DTLBPort::recvTimingResp(), gem5::ComputeUnit::ITLBPort::recvTimingResp(), gem5::ComputeUnit::ScalarDTLBPort::recvTimingResp(), and gem5::ComputeUnit::sendRequest().
◆ tc
| ThreadContext* gem5::GpuTranslationState::tc |
Definition at line 63 of file gpu_translation_state.hh.
Referenced by gem5::X86ISA::GpuTLB::handleFuncTranslationReturn(), gem5::X86ISA::GpuTLB::handleTranslationReturn(), gem5::X86ISA::GpuTLB::issueTLBLookup(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::X86ISA::GpuTLB::translationReturn(), and gem5::TLBCoalescer::updatePhysAddresses().
◆ tlbEntry
| Serializable* gem5::GpuTranslationState::tlbEntry |
Definition at line 73 of file gpu_translation_state.hh.
Referenced by gem5::Shader::functionalTLBAccess(), gem5::X86ISA::GpuTLB::handleFuncTranslationReturn(), gem5::VegaISA::GpuTLB::handleFuncTranslationReturn(), gem5::X86ISA::GpuTLB::handleTranslationReturn(), gem5::VegaISA::GpuTLB::handleTranslationReturn(), gem5::FetchUnit::initiateFetch(), gem5::X86ISA::GpuTLB::issueTLBLookup(), gem5::VegaISA::GpuTLB::issueTLBLookup(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::VegaISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::ComputeUnit::DTLBPort::recvTimingResp(), gem5::ComputeUnit::ITLBPort::recvTimingResp(), gem5::ComputeUnit::ScalarDTLBPort::recvTimingResp(), gem5::ComputeUnit::sendRequest(), gem5::X86ISA::GpuTLB::translationReturn(), gem5::TLBCoalescer::updatePhysAddresses(), gem5::VegaTLBCoalescer::updatePhysAddresses(), and gem5::VegaISA::GpuTLB::walkerResponse().
◆ tlbMode
| BaseMMU::Mode gem5::GpuTranslationState::tlbMode |
Definition at line 61 of file gpu_translation_state.hh.
Referenced by gem5::TLBCoalescer::canCoalesce(), gem5::VegaTLBCoalescer::canCoalesce(), gem5::X86ISA::GpuTLB::handleFuncTranslationReturn(), gem5::VegaISA::GpuTLB::handleFuncTranslationReturn(), gem5::X86ISA::GpuTLB::handleTranslationReturn(), gem5::VegaISA::GpuTLB::handleTranslationReturn(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::ComputeUnit::DTLBPort::recvTimingResp(), and gem5::X86ISA::GpuTLB::translationReturn().
The documentation for this struct was generated from the following file:
- arch/amdgpu/common/gpu_translation_state.hh