gem5  v21.2.1.1
fetch_unit.cc
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31 
33 
35 #include "base/bitfield.hh"
36 #include "debug/GPUFetch.hh"
37 #include "debug/GPUPort.hh"
38 #include "debug/GPUTLB.hh"
42 #include "gpu-compute/shader.hh"
43 #include "gpu-compute/wavefront.hh"
45 
46 namespace gem5
47 {
48 
50 
51 FetchUnit::FetchUnit(const ComputeUnitParams &p, ComputeUnit &cu)
52  : timingSim(true), computeUnit(cu), fetchScheduler(p),
53  waveList(nullptr), fetchDepth(p.fetch_depth)
54 {
55 }
56 
58 {
59  fetchQueue.clear();
60  fetchStatusQueue.clear();
61 }
62 
63 void
65 {
67  fetchQueue.clear();
70 
71  for (int i = 0; i < computeUnit.shader->n_wf; ++i) {
72  Wavefront *wf = waveList->at(i);
73  assert(wf->wfSlotId == i);
74  fetchStatusQueue[i] = std::make_pair(wf, false);
75  fetchBuf[i].allocateBuf(fetchDepth, computeUnit.cacheLineSize(), wf);
76  fetchBuf[i].decoder(&decoder);
77  }
78 
80 }
81 
82 void
84 {
93  for (auto &fetch_buf : fetchBuf) {
94  if (!fetch_buf.hasFreeSpace()) {
95  fetch_buf.checkWaveReleaseBuf();
96  }
97  if (fetch_buf.hasFetchDataToProcess()) {
98  fetch_buf.decodeInsts();
99  }
100  }
101 
102  // re-evaluate waves which are marked as not ready for fetch
103  for (int j = 0; j < computeUnit.shader->n_wf; ++j) {
104  // Following code assumes 64-bit opertaion and all insts are
105  // represented by 64-bit pointers to inst objects.
106  Wavefront *curWave = fetchStatusQueue[j].first;
107  assert (curWave);
108 
109  // The wavefront has to be active, the IB occupancy has to be
110  // 4 or less instructions and it can not have any branches to
111  // prevent speculative instruction fetches
112  if (!fetchStatusQueue[j].second) {
113  if ((curWave->getStatus() == Wavefront::S_RUNNING ||
114  curWave->getStatus() == Wavefront::S_WAITCNT) &&
115  fetchBuf[j].hasFreeSpace() &&
116  !curWave->stopFetch() &&
117  !curWave->pendingFetch) {
118  fetchQueue.push_back(curWave);
119  fetchStatusQueue[j].second = true;
120  }
121  }
122  }
123 
124  // Fetch only if there is some wave ready to be fetched
125  // An empty fetchQueue will cause the schedular to panic
126  if (fetchQueue.size()) {
127  Wavefront *waveToBeFetched = fetchScheduler.chooseWave();
128  waveToBeFetched->pendingFetch = true;
129  fetchStatusQueue[waveToBeFetched->wfSlotId].second = false;
130  initiateFetch(waveToBeFetched);
131  }
132 }
133 
134 void
136 {
137  assert(fetchBuf.at(wavefront->wfSlotId).hasFreeSpace());
138 
145  Addr vaddr = fetchBuf.at(wavefront->wfSlotId).nextFetchAddr();
146 
147  // this should already be aligned to a cache line
150 
151  // shouldn't be fetching a line that is already buffered
152  assert(!fetchBuf.at(wavefront->wfSlotId).pcBuffered(vaddr));
153 
154  fetchBuf.at(wavefront->wfSlotId).reserveBuf(vaddr);
155 
156  DPRINTF(GPUFetch, "CU%d: WF[%d][%d]: Id%d: Initiate fetch "
157  "from pc: %d %#x\n", computeUnit.cu_id, wavefront->simdId,
158  wavefront->wfSlotId, wavefront->wfDynId, wavefront->pc(), vaddr);
159 
160  DPRINTF(GPUTLB, "CU%d: WF[%d][%d]: Initiating fetch translation: %#x\n",
161  computeUnit.cu_id, wavefront->simdId, wavefront->wfSlotId, vaddr);
162 
163  // set up virtual request
164  RequestPtr req = std::make_shared<Request>(
166  computeUnit.requestorId(), 0, 0, nullptr);
167 
168  PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
169 
170  if (timingSim) {
171  // SenderState needed on Return
172  pkt->senderState = new ComputeUnit::ITLBPort::SenderState(wavefront);
173 
174  // Sender State needed by TLB hierarchy
175  pkt->senderState =
178  false, pkt->senderState);
179 
181  assert(computeUnit.sqcTLBPort.retries.size() > 0);
182 
183  DPRINTF(GPUTLB, "Failed to send TLB req for FETCH addr %#x\n",
184  vaddr);
185 
186  computeUnit.sqcTLBPort.retries.push_back(pkt);
187  } else if (!computeUnit.sqcTLBPort.sendTimingReq(pkt)) {
188  // Stall the data port;
189  // No more packet is issued till
190  // ruby indicates resources are freed by
191  // a recvReqRetry() call back on this port.
193 
194  DPRINTF(GPUTLB, "Failed to send TLB req for FETCH addr %#x\n",
195  vaddr);
196 
197  computeUnit.sqcTLBPort.retries.push_back(pkt);
198  } else {
199  DPRINTF(GPUTLB, "sent FETCH translation request for %#x\n", vaddr);
200  }
201  } else {
202  pkt->senderState =
205 
207 
208  GpuTranslationState *sender_state =
209  safe_cast<GpuTranslationState*>(pkt->senderState);
210 
211  delete sender_state->tlbEntry;
212  delete sender_state;
213  // fetch the instructions from the SQC when we operate in
214  // functional mode only
215  fetch(pkt, wavefront);
216  }
217 }
218 
219 void
221 {
222  assert(pkt->req->hasPaddr());
223  assert(pkt->req->hasSize());
224 
225  DPRINTF(GPUFetch, "CU%d: WF[%d][%d]: Fetch Access: %#x\n",
226  computeUnit.cu_id, wavefront->simdId, wavefront->wfSlotId,
227  pkt->req->getPaddr());
228 
235  PacketPtr oldPkt = pkt;
236  pkt = new Packet(oldPkt->req, oldPkt->cmd);
237  delete oldPkt;
238 
245  if (!fetchBuf.at(wavefront->wfSlotId).isReserved(pkt->req->getVaddr())) {
246  wavefront->dropFetch = false;
247  wavefront->pendingFetch = false;
248  return;
249  }
250 
256  pkt->dataStatic(fetchBuf.at(wavefront->wfSlotId)
257  .reservedBuf(pkt->req->getVaddr()));
258 
259  // New SenderState for the memory access
260  pkt->senderState = new ComputeUnit::SQCPort::SenderState(wavefront);
261 
262  if (timingSim) {
263  // translation is done. Send the appropriate timing memory request.
264 
265  if (!computeUnit.sqcPort.sendTimingReq(pkt)) {
266  computeUnit.sqcPort.retries.push_back(std::make_pair(pkt,
267  wavefront));
268 
269  DPRINTF(GPUPort, "CU%d: WF[%d][%d]: Fetch addr %#x failed!\n",
270  computeUnit.cu_id, wavefront->simdId, wavefront->wfSlotId,
271  pkt->req->getPaddr());
272  } else {
273  DPRINTF(GPUPort, "CU%d: WF[%d][%d]: Fetch addr %#x sent!\n",
274  computeUnit.cu_id, wavefront->simdId, wavefront->wfSlotId,
275  pkt->req->getPaddr());
276  }
277  } else {
279  processFetchReturn(pkt);
280  }
281 }
282 
283 void
285 {
286  ComputeUnit::SQCPort::SenderState *sender_state =
287  safe_cast<ComputeUnit::SQCPort::SenderState*>(pkt->senderState);
288 
289  Wavefront *wavefront = sender_state->wavefront;
290 
291  DPRINTF(GPUFetch, "CU%d: WF[%d][%d]: Fetch addr %#x returned "
292  "%d bytes!\n", computeUnit.cu_id, wavefront->simdId,
293  wavefront->wfSlotId, pkt->req->getPaddr(), pkt->req->getSize());
294 
295  if (wavefront->dropFetch) {
296  assert(wavefront->instructionBuffer.empty());
297  assert(!fetchBuf.at(wavefront->wfSlotId).hasFetchDataToProcess());
298  wavefront->dropFetch = false;
299  } else {
300  fetchBuf.at(wavefront->wfSlotId).fetchDone(pkt->req->getVaddr());
301  }
302 
303  wavefront->pendingFetch = false;
304 
305  delete pkt->senderState;
306  delete pkt;
307 }
308 
309 void
310 FetchUnit::flushBuf(int wfSlotId)
311 {
312  fetchBuf.at(wfSlotId).flushBuf();
313 }
314 
315 void
317 {
318  waveList = wave_list;
319 }
320 
322 void
323 FetchUnit::FetchBufDesc::allocateBuf(int fetch_depth, int cache_line_size,
324  Wavefront *wf)
325 {
326  wavefront = wf;
327  fetchDepth = fetch_depth;
329  cacheLineSize = cache_line_size;
331 
332  // Calculate the number of bits to address a cache line
334  "Cache line size should be a power of two.");
336 
337  bufStart = new uint8_t[maxFbSize];
338  readPtr = bufStart;
340 
341  for (int i = 0; i < fetchDepth; ++i) {
342  freeList.emplace_back(readPtr + i * cacheLineSize);
343  }
344 }
345 
346 void
348 {
349  restartFromBranch = true;
354  freeList.clear();
355  bufferedPCs.clear();
356  reservedPCs.clear();
357  readPtr = bufStart;
358 
359  for (int i = 0; i < fetchDepth; ++i) {
360  freeList.push_back(bufStart + i * cacheLineSize);
361  }
362 
363  DPRINTF(GPUFetch, "WF[%d][%d]: Id%d Fetch dropped, flushing fetch "
364  "buffer\n", wavefront->simdId, wavefront->wfSlotId,
365  wavefront->wfDynId);
366 }
367 
368 Addr
370 {
371  Addr next_line = 0;
372 
373  if (bufferedAndReservedLines()) {
374  Addr last_line_fetched = 0;
375  if (!reservedLines()) {
380  last_line_fetched = bufferedPCs.rbegin()->first;
381  } else {
382  last_line_fetched = reservedPCs.rbegin()->first;
383  }
384 
385  next_line = last_line_fetched + cacheLineSize;
386 
391  assert(bufferedPCs.find(next_line) == bufferedPCs.end());
392  assert(reservedPCs.find(next_line) == reservedPCs.end());
393  } else {
402  next_line = ruby::makeLineAddress(wavefront->pc(), cacheLineBits);
403  readPtr = bufStart;
404 
411  if (restartFromBranch) {
412  restartFromBranch = false;
413  int byte_offset
414  = wavefront->pc() - ruby::makeLineAddress(wavefront->pc(),
415  cacheLineBits);
416  readPtr += byte_offset;
417  }
418  }
419 
420  return next_line;
421 }
422 
423 void
425 {
426  // we should have free buffer space, and the line
427  // at vaddr should not already be cached.
428  assert(hasFreeSpace());
429  assert(bufferedPCs.find(vaddr) == bufferedPCs.end());
430  assert(reservedPCs.find(vaddr) == reservedPCs.end());
431  assert(bufferedAndReservedLines() < fetchDepth);
432 
433  DPRINTF(GPUFetch, "WF[%d][%d]: Id%d reserved fetch buffer entry "
434  "for PC = %#x\n", wavefront->simdId, wavefront->wfSlotId,
435  wavefront->wfDynId, vaddr);
436 
443  uint8_t *inst_buf = freeList.front();
444  reservedPCs.emplace(vaddr, inst_buf);
445  freeList.pop_front();
446 }
447 
448 void
450 {
451  assert(bufferedPCs.find(vaddr) == bufferedPCs.end());
452  DPRINTF(GPUFetch, "WF[%d][%d]: Id%d done fetching for addr %#x\n",
453  wavefront->simdId, wavefront->wfSlotId,
454  wavefront->wfDynId, vaddr);
455 
461  auto reserved_pc = reservedPCs.find(vaddr);
462  assert(reserved_pc != reservedPCs.end());
463  bufferedPCs.emplace(vaddr, reserved_pc->second);
464 
465  if (readPtr == bufEnd) {
466  readPtr = bufStart;
467  }
468 
469  reserved_pc->second = nullptr;
470  reservedPCs.erase(reserved_pc);
471 }
472 
473 bool
475 {
476  return fetchBytesRemaining() >= sizeof(TheGpuISA::RawMachInst);
477 }
478 
479 void
481 {
482  Addr cur_wave_pc = roundDown(wavefront->pc(),
483  wavefront->computeUnit->cacheLineSize());
484  if (reservedPCs.find(cur_wave_pc) != reservedPCs.end()) {
485  DPRINTF(GPUFetch, "WF[%d][%d]: Id%d current wave PC(%#x) still "
486  "being fetched.\n", wavefront->simdId, wavefront->wfSlotId,
487  wavefront->wfDynId, cur_wave_pc);
488 
489  // should be reserved, but not buffered yet
490  assert(bufferedPCs.find(cur_wave_pc) == bufferedPCs.end());
491 
492  return;
493  }
494 
495  auto current_buffered_pc = bufferedPCs.find(cur_wave_pc);
496  auto oldest_buffered_pc = bufferedPCs.begin();
497 
498  DPRINTF(GPUFetch, "WF[%d][%d]: Id%d checking if PC block addr = %#x"
499  "(PC = %#x) can be released.\n", wavefront->simdId,
500  wavefront->wfSlotId, wavefront->wfDynId, cur_wave_pc,
501  wavefront->pc());
502 
503 #ifdef DEBUG
504  int idx = 0;
505  for (const auto &buf_pc : bufferedPCs) {
506  DPRINTF(GPUFetch, "PC[%d] = %#x\n", idx, buf_pc.first);
507  ++idx;
508  }
509 #endif
510 
511  // if we haven't buffered data for this PC, we shouldn't
512  // be fetching from it.
513  assert(current_buffered_pc != bufferedPCs.end());
514 
521  if (current_buffered_pc != oldest_buffered_pc) {
522  DPRINTF(GPUFetch, "WF[%d][%d]: Id%d done fetching for PC = %#x, "
523  "removing it from the fetch buffer.\n", wavefront->simdId,
524  wavefront->wfSlotId, wavefront->wfDynId,
525  oldest_buffered_pc->first);
526 
527  freeList.emplace_back(oldest_buffered_pc->second);
528  oldest_buffered_pc->second = nullptr;
529  bufferedPCs.erase(oldest_buffered_pc);
530  DPRINTF(GPUFetch, "WF[%d][%d]: Id%d has %d lines buffered.\n",
531  wavefront->simdId, wavefront->wfSlotId, wavefront->wfDynId,
532  bufferedLines());
533  }
534 }
535 
536 void
538 {
539  assert(readPtr);
540 
541  if (splitDecode()) {
542  decodeSplitInst();
543  }
544 
545  while (wavefront->instructionBuffer.size() < maxIbSize
546  && hasFetchDataToProcess()) {
547  if (splitDecode()) {
548  decodeSplitInst();
549  } else {
550  TheGpuISA::MachInst mach_inst
551  = reinterpret_cast<TheGpuISA::MachInst>(readPtr);
552  GPUStaticInst *gpu_static_inst = _decoder->decode(mach_inst);
553  readPtr += gpu_static_inst->instSize();
554 
555  assert(readPtr <= bufEnd);
556 
557  GPUDynInstPtr gpu_dyn_inst
558  = std::make_shared<GPUDynInst>(wavefront->computeUnit,
559  wavefront, gpu_static_inst,
560  wavefront->computeUnit->
561  getAndIncSeqNum());
562  wavefront->instructionBuffer.push_back(gpu_dyn_inst);
563 
564  DPRINTF(GPUFetch, "WF[%d][%d]: Id%ld decoded %s (%d bytes). "
565  "%d bytes remain.\n", wavefront->simdId,
566  wavefront->wfSlotId, wavefront->wfDynId,
567  gpu_static_inst->disassemble(),
568  gpu_static_inst->instSize(),
569  fetchBytesRemaining());
570  }
571  }
572 }
573 
574 void
576 {
577  TheGpuISA::RawMachInst split_inst = 0;
578  int dword_size = sizeof(uint32_t);
579  int num_dwords = sizeof(TheGpuISA::RawMachInst) / dword_size;
580 
581  for (int i = 0; i < num_dwords; ++i) {
582  replaceBits(split_inst, 32*(i+1)-1, 32*i,
583  *reinterpret_cast<uint32_t*>(readPtr));
584  if (readPtr + dword_size >= bufEnd) {
585  readPtr = bufStart;
586  }
587  }
588 
589  assert(readPtr == bufStart);
590 
591  TheGpuISA::MachInst mach_inst
592  = reinterpret_cast<TheGpuISA::MachInst>(&split_inst);
593  GPUStaticInst *gpu_static_inst = _decoder->decode(mach_inst);
594  readPtr += (gpu_static_inst->instSize() - dword_size);
595  assert(readPtr < bufEnd);
596 
597  GPUDynInstPtr gpu_dyn_inst
598  = std::make_shared<GPUDynInst>(wavefront->computeUnit,
599  wavefront, gpu_static_inst,
600  wavefront->computeUnit->
601  getAndIncSeqNum());
602  wavefront->instructionBuffer.push_back(gpu_dyn_inst);
603 
604  DPRINTF(GPUFetch, "WF[%d][%d]: Id%d decoded split inst %s (%#x) "
605  "(%d bytes). %d bytes remain in %d buffered lines.\n",
606  wavefront->simdId, wavefront->wfSlotId, wavefront->wfDynId,
607  gpu_static_inst->disassemble(), split_inst,
608  gpu_static_inst->instSize(), fetchBytesRemaining(),
609  bufferedLines());
610 }
611 
612 bool
614 {
619  bool is_split = (readPtr + sizeof(TheGpuISA::RawMachInst)) > bufEnd;
620 
621  return is_split;
622 }
623 
624 int
626 {
627  int bytes_remaining = 0;
628 
629  if (bufferedLines() && readPtr != bufEnd) {
630  auto last_buf_pc = bufferedPCs.rbegin();
631  uint8_t *end_ptr = last_buf_pc->second + cacheLineSize;
632  int byte_diff = end_ptr - readPtr;
633 
634  if (end_ptr > readPtr) {
635  bytes_remaining = byte_diff;
636  } else if (end_ptr < readPtr) {
637  bytes_remaining = bufferedBytes() + byte_diff;
638  }
639  }
640 
641  assert(bytes_remaining <= bufferedBytes());
642  return bytes_remaining;
643 }
644 
645 } // namespace gem5
gem5::ComputeUnit::SQCPort::SenderState
Definition: compute_unit.hh:611
gem5::RequestPort::sendTimingReq
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition: port.hh:495
gem5::Shader::gpuTc
ThreadContext * gpuTc
Definition: shader.hh:108
gem5::Wavefront::S_RUNNING
@ S_RUNNING
Definition: wavefront.hh:70
gem5::Gcn3ISA::MachInst
InstFormat * MachInst
used to represent the encoding of a GCN3 inst.
Definition: gpu_types.hh:61
gem5::FetchUnit::~FetchUnit
~FetchUnit()
Definition: fetch_unit.cc:57
gem5::FetchUnit::flushBuf
void flushBuf(int wfSlotId)
Definition: fetch_unit.cc:310
gem5::ComputeUnit::ITLBPort::isStalled
bool isStalled()
Definition: compute_unit.hh:726
shader.hh
gem5::Request::INST_FETCH
@ INST_FETCH
The request was an instruction fetch.
Definition: request.hh:115
gem5::FetchUnit::FetchBufDesc::maxIbSize
int maxIbSize
Definition: fetch_unit.hh:230
gem5::GPUStaticInst::disassemble
const std::string & disassemble()
Definition: gpu_static_inst.cc:47
gem5::FetchUnit::FetchBufDesc::cacheLineSize
int cacheLineSize
Definition: fetch_unit.hh:233
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::Wavefront
Definition: wavefront.hh:60
gem5::FetchUnit::FetchBufDesc::fetchDepth
int fetchDepth
Definition: fetch_unit.hh:228
compute_unit.hh
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::Wavefront::stopFetch
bool stopFetch()
Definition: wavefront.cc:727
gem5::ComputeUnit::ITLBPort::retries
std::deque< PacketPtr > retries
here we queue all the translation requests that were not successfully sent.
Definition: compute_unit.hh:734
gpu_static_inst.hh
gem5::FetchUnit::timingSim
bool timingSim
Definition: fetch_unit.hh:241
gem5::floorLog2
static constexpr std::enable_if_t< std::is_integral_v< T >, int > floorLog2(T x)
Definition: intmath.hh:59
gem5::Wavefront::pendingFetch
bool pendingFetch
Definition: wavefront.hh:111
gem5::ComputeUnit::SQCPort::SenderState::wavefront
Wavefront * wavefront
Definition: compute_unit.hh:613
gem5::FetchUnit::FetchBufDesc::splitDecode
bool splitDecode() const
check if the next instruction to be processed out of the fetch buffer is split across the end/beginni...
Definition: fetch_unit.cc:613
gem5::Wavefront::pc
Addr pc() const
Definition: wavefront.cc:1363
gem5::FetchUnit::fetchDepth
int fetchDepth
number of cache lines we can fetch and buffer.
Definition: fetch_unit.hh:270
std::vector
STL vector class.
Definition: stl.hh:37
fetch_unit.hh
gem5::FetchUnit::fetchBuf
std::vector< FetchBufDesc > fetchBuf
Definition: fetch_unit.hh:263
gem5::ComputeUnit::SQCPort::retries
std::deque< std::pair< PacketPtr, Wavefront * > > retries
Definition: compute_unit.hh:624
gem5::FetchUnit::init
void init()
Definition: fetch_unit.cc:64
gem5::GPUStaticInst
Definition: gpu_static_inst.hh:61
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::FetchUnit::FetchBufDesc::maxFbSize
int maxFbSize
Definition: fetch_unit.hh:232
gem5::ComputeUnit::shader
Shader * shader
Definition: compute_unit.hh:353
gem5::ruby::makeLineAddress
Addr makeLineAddress(Addr addr)
Definition: Address.cc:60
gem5::isPowerOf2
static constexpr bool isPowerOf2(const T &n)
Definition: intmath.hh:98
gem5::ComputeUnit::ITLBPort::stallPort
void stallPort()
Definition: compute_unit.hh:727
gem5::ComputeUnit::cu_id
int cu_id
Definition: compute_unit.hh:292
wavefront.hh
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:56
gem5::Packet::dataStatic
void dataStatic(T *p)
Set the data pointer to the following value that should not be freed.
Definition: packet.hh:1134
gem5::FetchUnit::fetchQueue
std::vector< Wavefront * > fetchQueue
Definition: fetch_unit.hh:253
gem5::FetchUnit::FetchBufDesc::fetchDone
void fetchDone(Addr vaddr)
Definition: fetch_unit.cc:449
gem5::Wavefront::maxIbSize
int maxIbSize
Definition: wavefront.hh:107
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::FetchUnit::FetchBufDesc::wavefront
Wavefront * wavefront
Definition: fetch_unit.hh:237
gem5::X86ISA::GpuTLB::TranslationState
TLB TranslationState: this currently is a somewhat bastardization of the usage of SenderState,...
Definition: tlb.hh:283
gem5::ComputeUnit
Definition: compute_unit.hh:201
gem5::FetchUnit::decoder
TheGpuISA::Decoder decoder
Definition: fetch_unit.hh:243
gem5::RequestPort::sendFunctional
void sendFunctional(PacketPtr pkt) const
Send a functional request packet, where the data is instantly updated everywhere in the memory system...
Definition: port.hh:485
gem5::FetchUnit::FetchBufDesc::readPtr
uint8_t * readPtr
pointer that points to the next chunk of inst data to be decoded.
Definition: fetch_unit.hh:226
gem5::FetchUnit::FetchBufDesc::nextFetchAddr
Addr nextFetchAddr()
Definition: fetch_unit.cc:369
gem5::ComputeUnit::sqcTLBPort
ITLBPort sqcTLBPort
Definition: compute_unit.hh:855
gem5::FetchUnit::FetchBufDesc::flushBuf
void flushBuf()
Definition: fetch_unit.cc:347
bitfield.hh
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::FetchUnit::initiateFetch
void initiateFetch(Wavefront *wavefront)
Definition: fetch_unit.cc:135
gem5::Wavefront::wfSlotId
const int wfSlotId
Definition: wavefront.hh:96
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::FetchUnit::FetchBufDesc::decodeSplitInst
void decodeSplitInst()
Definition: fetch_unit.cc:575
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::FetchUnit::FetchBufDesc
fetch buffer descriptor.
Definition: fetch_unit.hh:73
gem5::FetchUnit::FetchBufDesc::bufEnd
uint8_t * bufEnd
Definition: fetch_unit.hh:221
gem5::FetchUnit::FetchUnit
FetchUnit(const ComputeUnitParams &p, ComputeUnit &cu)
Definition: fetch_unit.cc:51
gpu_dyn_inst.hh
gem5::FetchUnit::FetchBufDesc::fetchBytesRemaining
int fetchBytesRemaining() const
calculates the number of fetched bytes that have yet to be decoded.
Definition: fetch_unit.cc:625
gem5::ComputeUnit::cacheLineSize
int cacheLineSize() const
Definition: compute_unit.hh:411
gem5::GPUStaticInst::instSize
virtual int instSize() const =0
gem5::roundDown
static constexpr T roundDown(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:279
gem5::Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:361
gem5::Wavefront::wfDynId
uint64_t wfDynId
Definition: wavefront.hh:226
RubySystem.hh
gem5::FetchUnit::FetchBufDesc::decodeInsts
void decodeInsts()
each time the fetch stage is ticked, we check if there are any data in the fetch buffer that may be d...
Definition: fetch_unit.cc:537
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uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
tlb.hh
gem5::Packet::senderState
SenderState * senderState
This packet's sender state.
Definition: packet.hh:534
gem5::GpuTranslationState
X86ISA::GpuTLB::TranslationState GpuTranslationState
Definition: tlb.hh:439
gem5::FetchUnit::bindWaveList
void bindWaveList(std::vector< Wavefront * > *list)
Definition: fetch_unit.cc:316
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49
gem5::FetchUnit::FetchBufDesc::allocateBuf
void allocateBuf(int fetch_depth, int cache_line_size, Wavefront *wf)
allocate the fetch buffer space, and set the fetch depth (number of lines that may be buffered),...
Definition: fetch_unit.cc:323
gem5::Shader::timingSim
bool timingSim
Definition: shader.hh:189
gem5::ComputeUnit::getCacheLineBits
int getCacheLineBits() const
Definition: compute_unit.hh:412
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::FetchUnit::FetchBufDesc::bufStart
uint8_t * bufStart
raw instruction buffer.
Definition: fetch_unit.hh:220
gem5::FetchUnit::FetchBufDesc::reserveBuf
void reserveBuf(Addr vaddr)
reserve an entry in the fetch buffer for PC = vaddr,
Definition: fetch_unit.cc:424
gem5::FetchUnit::fetchScheduler
Scheduler fetchScheduler
Definition: fetch_unit.hh:249
gem5::FetchUnit::FetchBufDesc::checkWaveReleaseBuf
void checkWaveReleaseBuf()
checks if the wavefront can release any of its fetch buffer entries.
Definition: fetch_unit.cc:480
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TlbEntry * tlbEntry
Definition: tlb.hh:295
gem5::Wavefront::S_WAITCNT
@ S_WAITCNT
wavefront has unsatisfied wait counts
Definition: wavefront.hh:88
gem5::FetchUnit::globalFetchUnitID
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Definition: fetch_unit.hh:66
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Definition: scheduler.cc:53
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int n_wf
Definition: shader.hh:203
gem5::FetchUnit::FetchBufDesc::cacheLineBits
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Definition: fetch_unit.hh:234
gem5::FetchUnit::waveList
std::vector< Wavefront * > * waveList
Definition: fetch_unit.hh:261
gem5::Wavefront::instructionBuffer
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Definition: wavefront.hh:109
gem5::FetchUnit::fetchStatusQueue
std::vector< std::pair< Wavefront *, bool > > fetchStatusQueue
Definition: fetch_unit.hh:258
gem5::Scheduler::bindList
void bindList(std::vector< Wavefront * > *sched_list)
Definition: scheduler.cc:59
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::Wavefront::getStatus
status_e getStatus()
Definition: wavefront.hh:137
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::FetchUnit::computeUnit
ComputeUnit & computeUnit
Definition: fetch_unit.hh:242
gem5::ComputeUnit::sqcPort
SQCPort sqcPort
Definition: compute_unit.hh:853
gem5::FetchUnit::exec
void exec()
Definition: fetch_unit.cc:83
gem5::FetchUnit::FetchBufDesc::hasFetchDataToProcess
bool hasFetchDataToProcess() const
checks if the buffer contains valid data.
Definition: fetch_unit.cc:474
gem5::FetchUnit::FetchBufDesc::freeList
std::deque< uint8_t * > freeList
represents the fetch buffer free list.
Definition: fetch_unit.hh:214
gem5::Wavefront::dropFetch
bool dropFetch
Definition: wavefront.hh:112
gem5::Gcn3ISA::RawMachInst
uint64_t RawMachInst
used to represnt a GPU inst in its raw format.
Definition: gpu_types.hh:42
gem5::FetchUnit::fetch
void fetch(PacketPtr pkt, Wavefront *wavefront)
Definition: fetch_unit.cc:220
gem5::ComputeUnit::requestorId
RequestorID requestorId()
Definition: compute_unit.hh:460
gem5::SenderState
RubyTester::SenderState SenderState
Definition: Check.cc:40
gem5::FetchUnit::processFetchReturn
void processFetchReturn(PacketPtr pkt)
Definition: fetch_unit.cc:284
gem5::Wavefront::simdId
const int simdId
Definition: wavefront.hh:99

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