gem5  v21.1.0.2
fetch_unit.cc
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33 
35 
36 #include "base/bitfield.hh"
37 #include "debug/GPUFetch.hh"
38 #include "debug/GPUPort.hh"
39 #include "debug/GPUTLB.hh"
43 #include "gpu-compute/shader.hh"
44 #include "gpu-compute/wavefront.hh"
46 
47 namespace gem5
48 {
49 
51 
52 FetchUnit::FetchUnit(const ComputeUnitParams &p, ComputeUnit &cu)
53  : timingSim(true), computeUnit(cu), fetchScheduler(p),
54  waveList(nullptr), fetchDepth(p.fetch_depth)
55 {
56 }
57 
59 {
60  fetchQueue.clear();
61  fetchStatusQueue.clear();
62 }
63 
64 void
66 {
68  fetchQueue.clear();
71 
72  for (int i = 0; i < computeUnit.shader->n_wf; ++i) {
73  Wavefront *wf = waveList->at(i);
74  assert(wf->wfSlotId == i);
75  fetchStatusQueue[i] = std::make_pair(wf, false);
76  fetchBuf[i].allocateBuf(fetchDepth, computeUnit.cacheLineSize(), wf);
77  fetchBuf[i].decoder(&decoder);
78  }
79 
81 }
82 
83 void
85 {
94  for (auto &fetch_buf : fetchBuf) {
95  if (!fetch_buf.hasFreeSpace()) {
96  fetch_buf.checkWaveReleaseBuf();
97  }
98  if (fetch_buf.hasFetchDataToProcess()) {
99  fetch_buf.decodeInsts();
100  }
101  }
102 
103  // re-evaluate waves which are marked as not ready for fetch
104  for (int j = 0; j < computeUnit.shader->n_wf; ++j) {
105  // Following code assumes 64-bit opertaion and all insts are
106  // represented by 64-bit pointers to inst objects.
107  Wavefront *curWave = fetchStatusQueue[j].first;
108  assert (curWave);
109 
110  // The wavefront has to be active, the IB occupancy has to be
111  // 4 or less instructions and it can not have any branches to
112  // prevent speculative instruction fetches
113  if (!fetchStatusQueue[j].second) {
114  if ((curWave->getStatus() == Wavefront::S_RUNNING ||
115  curWave->getStatus() == Wavefront::S_WAITCNT) &&
116  fetchBuf[j].hasFreeSpace() &&
117  !curWave->stopFetch() &&
118  !curWave->pendingFetch) {
119  fetchQueue.push_back(curWave);
120  fetchStatusQueue[j].second = true;
121  }
122  }
123  }
124 
125  // Fetch only if there is some wave ready to be fetched
126  // An empty fetchQueue will cause the schedular to panic
127  if (fetchQueue.size()) {
128  Wavefront *waveToBeFetched = fetchScheduler.chooseWave();
129  waveToBeFetched->pendingFetch = true;
130  fetchStatusQueue[waveToBeFetched->wfSlotId].second = false;
131  initiateFetch(waveToBeFetched);
132  }
133 }
134 
135 void
137 {
138  assert(fetchBuf.at(wavefront->wfSlotId).hasFreeSpace());
139 
146  Addr vaddr = fetchBuf.at(wavefront->wfSlotId).nextFetchAddr();
147 
148  // this should already be aligned to a cache line
151 
152  // shouldn't be fetching a line that is already buffered
153  assert(!fetchBuf.at(wavefront->wfSlotId).pcBuffered(vaddr));
154 
155  fetchBuf.at(wavefront->wfSlotId).reserveBuf(vaddr);
156 
157  DPRINTF(GPUFetch, "CU%d: WF[%d][%d]: Id%d: Initiate fetch "
158  "from pc: %d %#x\n", computeUnit.cu_id, wavefront->simdId,
159  wavefront->wfSlotId, wavefront->wfDynId, wavefront->pc(), vaddr);
160 
161  DPRINTF(GPUTLB, "CU%d: WF[%d][%d]: Initiating fetch translation: %#x\n",
162  computeUnit.cu_id, wavefront->simdId, wavefront->wfSlotId, vaddr);
163 
164  // set up virtual request
165  RequestPtr req = std::make_shared<Request>(
167  computeUnit.requestorId(), 0, 0, nullptr);
168 
169  PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
170 
171  if (timingSim) {
172  // SenderState needed on Return
173  pkt->senderState = new ComputeUnit::ITLBPort::SenderState(wavefront);
174 
175  // Sender State needed by TLB hierarchy
176  pkt->senderState =
177  new TheISA::GpuTLB::TranslationState(BaseMMU::Execute,
179  false, pkt->senderState);
180 
182  assert(computeUnit.sqcTLBPort.retries.size() > 0);
183 
184  DPRINTF(GPUTLB, "Failed to send TLB req for FETCH addr %#x\n",
185  vaddr);
186 
187  computeUnit.sqcTLBPort.retries.push_back(pkt);
188  } else if (!computeUnit.sqcTLBPort.sendTimingReq(pkt)) {
189  // Stall the data port;
190  // No more packet is issued till
191  // ruby indicates resources are freed by
192  // a recvReqRetry() call back on this port.
194 
195  DPRINTF(GPUTLB, "Failed to send TLB req for FETCH addr %#x\n",
196  vaddr);
197 
198  computeUnit.sqcTLBPort.retries.push_back(pkt);
199  } else {
200  DPRINTF(GPUTLB, "sent FETCH translation request for %#x\n", vaddr);
201  }
202  } else {
203  pkt->senderState =
204  new TheISA::GpuTLB::TranslationState(BaseMMU::Execute,
206 
208 
209  TheISA::GpuTLB::TranslationState *sender_state =
210  safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
211 
212  delete sender_state->tlbEntry;
213  delete sender_state;
214  // fetch the instructions from the SQC when we operate in
215  // functional mode only
216  fetch(pkt, wavefront);
217  }
218 }
219 
220 void
222 {
223  assert(pkt->req->hasPaddr());
224  assert(pkt->req->hasSize());
225 
226  DPRINTF(GPUFetch, "CU%d: WF[%d][%d]: Fetch Access: %#x\n",
227  computeUnit.cu_id, wavefront->simdId, wavefront->wfSlotId,
228  pkt->req->getPaddr());
229 
236  PacketPtr oldPkt = pkt;
237  pkt = new Packet(oldPkt->req, oldPkt->cmd);
238  delete oldPkt;
239 
246  if (!fetchBuf.at(wavefront->wfSlotId).isReserved(pkt->req->getVaddr())) {
247  wavefront->dropFetch = false;
248  wavefront->pendingFetch = false;
249  return;
250  }
251 
257  pkt->dataStatic(fetchBuf.at(wavefront->wfSlotId)
258  .reservedBuf(pkt->req->getVaddr()));
259 
260  // New SenderState for the memory access
261  pkt->senderState = new ComputeUnit::SQCPort::SenderState(wavefront);
262 
263  if (timingSim) {
264  // translation is done. Send the appropriate timing memory request.
265 
266  if (!computeUnit.sqcPort.sendTimingReq(pkt)) {
267  computeUnit.sqcPort.retries.push_back(std::make_pair(pkt,
268  wavefront));
269 
270  DPRINTF(GPUPort, "CU%d: WF[%d][%d]: Fetch addr %#x failed!\n",
271  computeUnit.cu_id, wavefront->simdId, wavefront->wfSlotId,
272  pkt->req->getPaddr());
273  } else {
274  DPRINTF(GPUPort, "CU%d: WF[%d][%d]: Fetch addr %#x sent!\n",
275  computeUnit.cu_id, wavefront->simdId, wavefront->wfSlotId,
276  pkt->req->getPaddr());
277  }
278  } else {
280  processFetchReturn(pkt);
281  }
282 }
283 
284 void
286 {
287  ComputeUnit::SQCPort::SenderState *sender_state =
288  safe_cast<ComputeUnit::SQCPort::SenderState*>(pkt->senderState);
289 
290  Wavefront *wavefront = sender_state->wavefront;
291 
292  DPRINTF(GPUFetch, "CU%d: WF[%d][%d]: Fetch addr %#x returned "
293  "%d bytes!\n", computeUnit.cu_id, wavefront->simdId,
294  wavefront->wfSlotId, pkt->req->getPaddr(), pkt->req->getSize());
295 
296  if (wavefront->dropFetch) {
297  assert(wavefront->instructionBuffer.empty());
298  assert(!fetchBuf.at(wavefront->wfSlotId).hasFetchDataToProcess());
299  wavefront->dropFetch = false;
300  } else {
301  fetchBuf.at(wavefront->wfSlotId).fetchDone(pkt->req->getVaddr());
302  }
303 
304  wavefront->pendingFetch = false;
305 
306  delete pkt->senderState;
307  delete pkt;
308 }
309 
310 void
311 FetchUnit::flushBuf(int wfSlotId)
312 {
313  fetchBuf.at(wfSlotId).flushBuf();
314 }
315 
316 void
318 {
319  waveList = wave_list;
320 }
321 
323 void
324 FetchUnit::FetchBufDesc::allocateBuf(int fetch_depth, int cache_line_size,
325  Wavefront *wf)
326 {
327  wavefront = wf;
328  fetchDepth = fetch_depth;
330  cacheLineSize = cache_line_size;
332 
333  // Calculate the number of bits to address a cache line
335  "Cache line size should be a power of two.");
337 
338  bufStart = new uint8_t[maxFbSize];
339  readPtr = bufStart;
341 
342  for (int i = 0; i < fetchDepth; ++i) {
343  freeList.emplace_back(readPtr + i * cacheLineSize);
344  }
345 }
346 
347 void
349 {
350  restartFromBranch = true;
355  freeList.clear();
356  bufferedPCs.clear();
357  reservedPCs.clear();
358  readPtr = bufStart;
359 
360  for (int i = 0; i < fetchDepth; ++i) {
361  freeList.push_back(bufStart + i * cacheLineSize);
362  }
363 
364  DPRINTF(GPUFetch, "WF[%d][%d]: Id%d Fetch dropped, flushing fetch "
365  "buffer\n", wavefront->simdId, wavefront->wfSlotId,
366  wavefront->wfDynId);
367 }
368 
369 Addr
371 {
372  Addr next_line = 0;
373 
374  if (bufferedAndReservedLines()) {
375  Addr last_line_fetched = 0;
376  if (!reservedLines()) {
381  last_line_fetched = bufferedPCs.rbegin()->first;
382  } else {
383  last_line_fetched = reservedPCs.rbegin()->first;
384  }
385 
386  next_line = last_line_fetched + cacheLineSize;
387 
392  assert(bufferedPCs.find(next_line) == bufferedPCs.end());
393  assert(reservedPCs.find(next_line) == reservedPCs.end());
394  } else {
403  next_line = ruby::makeLineAddress(wavefront->pc(), cacheLineBits);
404  readPtr = bufStart;
405 
412  if (restartFromBranch) {
413  restartFromBranch = false;
414  int byte_offset
415  = wavefront->pc() - ruby::makeLineAddress(wavefront->pc(),
416  cacheLineBits);
417  readPtr += byte_offset;
418  }
419  }
420 
421  return next_line;
422 }
423 
424 void
426 {
427  // we should have free buffer space, and the line
428  // at vaddr should not already be cached.
429  assert(hasFreeSpace());
430  assert(bufferedPCs.find(vaddr) == bufferedPCs.end());
431  assert(reservedPCs.find(vaddr) == reservedPCs.end());
432  assert(bufferedAndReservedLines() < fetchDepth);
433 
434  DPRINTF(GPUFetch, "WF[%d][%d]: Id%d reserved fetch buffer entry "
435  "for PC = %#x\n", wavefront->simdId, wavefront->wfSlotId,
436  wavefront->wfDynId, vaddr);
437 
444  uint8_t *inst_buf = freeList.front();
445  reservedPCs.emplace(vaddr, inst_buf);
446  freeList.pop_front();
447 }
448 
449 void
451 {
452  assert(bufferedPCs.find(vaddr) == bufferedPCs.end());
453  DPRINTF(GPUFetch, "WF[%d][%d]: Id%d done fetching for addr %#x\n",
454  wavefront->simdId, wavefront->wfSlotId,
455  wavefront->wfDynId, vaddr);
456 
462  auto reserved_pc = reservedPCs.find(vaddr);
463  assert(reserved_pc != reservedPCs.end());
464  bufferedPCs.emplace(vaddr, reserved_pc->second);
465 
466  if (readPtr == bufEnd) {
467  readPtr = bufStart;
468  }
469 
470  reserved_pc->second = nullptr;
471  reservedPCs.erase(reserved_pc);
472 }
473 
474 bool
476 {
477  return fetchBytesRemaining() >= sizeof(TheGpuISA::RawMachInst);
478 }
479 
480 void
482 {
483  Addr cur_wave_pc = roundDown(wavefront->pc(),
484  wavefront->computeUnit->cacheLineSize());
485  if (reservedPCs.find(cur_wave_pc) != reservedPCs.end()) {
486  DPRINTF(GPUFetch, "WF[%d][%d]: Id%d current wave PC(%#x) still "
487  "being fetched.\n", wavefront->simdId, wavefront->wfSlotId,
488  wavefront->wfDynId, cur_wave_pc);
489 
490  // should be reserved, but not buffered yet
491  assert(bufferedPCs.find(cur_wave_pc) == bufferedPCs.end());
492 
493  return;
494  }
495 
496  auto current_buffered_pc = bufferedPCs.find(cur_wave_pc);
497  auto oldest_buffered_pc = bufferedPCs.begin();
498 
499  DPRINTF(GPUFetch, "WF[%d][%d]: Id%d checking if PC block addr = %#x"
500  "(PC = %#x) can be released.\n", wavefront->simdId,
501  wavefront->wfSlotId, wavefront->wfDynId, cur_wave_pc,
502  wavefront->pc());
503 
504 #ifdef DEBUG
505  int idx = 0;
506  for (const auto &buf_pc : bufferedPCs) {
507  DPRINTF(GPUFetch, "PC[%d] = %#x\n", idx, buf_pc.first);
508  ++idx;
509  }
510 #endif
511 
512  // if we haven't buffered data for this PC, we shouldn't
513  // be fetching from it.
514  assert(current_buffered_pc != bufferedPCs.end());
515 
522  if (current_buffered_pc != oldest_buffered_pc) {
523  DPRINTF(GPUFetch, "WF[%d][%d]: Id%d done fetching for PC = %#x, "
524  "removing it from the fetch buffer.\n", wavefront->simdId,
525  wavefront->wfSlotId, wavefront->wfDynId,
526  oldest_buffered_pc->first);
527 
528  freeList.emplace_back(oldest_buffered_pc->second);
529  oldest_buffered_pc->second = nullptr;
530  bufferedPCs.erase(oldest_buffered_pc);
531  DPRINTF(GPUFetch, "WF[%d][%d]: Id%d has %d lines buffered.\n",
532  wavefront->simdId, wavefront->wfSlotId, wavefront->wfDynId,
533  bufferedLines());
534  }
535 }
536 
537 void
539 {
540  assert(readPtr);
541 
542  if (splitDecode()) {
543  decodeSplitInst();
544  }
545 
546  while (wavefront->instructionBuffer.size() < maxIbSize
547  && hasFetchDataToProcess()) {
548  if (splitDecode()) {
549  decodeSplitInst();
550  } else {
551  TheGpuISA::MachInst mach_inst
552  = reinterpret_cast<TheGpuISA::MachInst>(readPtr);
553  GPUStaticInst *gpu_static_inst = _decoder->decode(mach_inst);
554  readPtr += gpu_static_inst->instSize();
555 
556  assert(readPtr <= bufEnd);
557 
558  GPUDynInstPtr gpu_dyn_inst
559  = std::make_shared<GPUDynInst>(wavefront->computeUnit,
560  wavefront, gpu_static_inst,
561  wavefront->computeUnit->
562  getAndIncSeqNum());
563  wavefront->instructionBuffer.push_back(gpu_dyn_inst);
564 
565  DPRINTF(GPUFetch, "WF[%d][%d]: Id%ld decoded %s (%d bytes). "
566  "%d bytes remain.\n", wavefront->simdId,
567  wavefront->wfSlotId, wavefront->wfDynId,
568  gpu_static_inst->disassemble(),
569  gpu_static_inst->instSize(),
570  fetchBytesRemaining());
571  }
572  }
573 }
574 
575 void
577 {
578  TheGpuISA::RawMachInst split_inst = 0;
579  int dword_size = sizeof(uint32_t);
580  int num_dwords = sizeof(TheGpuISA::RawMachInst) / dword_size;
581 
582  for (int i = 0; i < num_dwords; ++i) {
583  replaceBits(split_inst, 32*(i+1)-1, 32*i,
584  *reinterpret_cast<uint32_t*>(readPtr));
585  if (readPtr + dword_size >= bufEnd) {
586  readPtr = bufStart;
587  }
588  }
589 
590  assert(readPtr == bufStart);
591 
592  TheGpuISA::MachInst mach_inst
593  = reinterpret_cast<TheGpuISA::MachInst>(&split_inst);
594  GPUStaticInst *gpu_static_inst = _decoder->decode(mach_inst);
595  readPtr += (gpu_static_inst->instSize() - dword_size);
596  assert(readPtr < bufEnd);
597 
598  GPUDynInstPtr gpu_dyn_inst
599  = std::make_shared<GPUDynInst>(wavefront->computeUnit,
600  wavefront, gpu_static_inst,
601  wavefront->computeUnit->
602  getAndIncSeqNum());
603  wavefront->instructionBuffer.push_back(gpu_dyn_inst);
604 
605  DPRINTF(GPUFetch, "WF[%d][%d]: Id%d decoded split inst %s (%#x) "
606  "(%d bytes). %d bytes remain in %d buffered lines.\n",
607  wavefront->simdId, wavefront->wfSlotId, wavefront->wfDynId,
608  gpu_static_inst->disassemble(), split_inst,
609  gpu_static_inst->instSize(), fetchBytesRemaining(),
610  bufferedLines());
611 }
612 
613 bool
615 {
620  bool is_split = (readPtr + sizeof(TheGpuISA::RawMachInst)) > bufEnd;
621 
622  return is_split;
623 }
624 
625 int
627 {
628  int bytes_remaining = 0;
629 
630  if (bufferedLines() && readPtr != bufEnd) {
631  auto last_buf_pc = bufferedPCs.rbegin();
632  uint8_t *end_ptr = last_buf_pc->second + cacheLineSize;
633  int byte_diff = end_ptr - readPtr;
634 
635  if (end_ptr > readPtr) {
636  bytes_remaining = byte_diff;
637  } else if (end_ptr < readPtr) {
638  bytes_remaining = bufferedBytes() + byte_diff;
639  }
640  }
641 
642  assert(bytes_remaining <= bufferedBytes());
643  return bytes_remaining;
644 }
645 
646 } // namespace gem5
gem5::ComputeUnit::SQCPort::SenderState
Definition: compute_unit.hh:613
gem5::RequestPort::sendTimingReq
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition: port.hh:495
gem5::Shader::gpuTc
ThreadContext * gpuTc
Definition: shader.hh:110
gem5::Wavefront::S_RUNNING
@ S_RUNNING
Definition: wavefront.hh:72
gem5::Gcn3ISA::MachInst
InstFormat * MachInst
used to represent the encoding of a GCN3 inst.
Definition: gpu_types.hh:63
gem5::FetchUnit::~FetchUnit
~FetchUnit()
Definition: fetch_unit.cc:58
gem5::FetchUnit::flushBuf
void flushBuf(int wfSlotId)
Definition: fetch_unit.cc:311
gem5::ComputeUnit::ITLBPort::isStalled
bool isStalled()
Definition: compute_unit.hh:728
shader.hh
gem5::FetchUnit::FetchBufDesc::maxIbSize
int maxIbSize
Definition: fetch_unit.hh:232
gem5::GPUStaticInst::disassemble
const std::string & disassemble()
Definition: gpu_static_inst.cc:49
gem5::FetchUnit::FetchBufDesc::cacheLineSize
int cacheLineSize
Definition: fetch_unit.hh:235
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::Wavefront
Definition: wavefront.hh:62
gem5::FetchUnit::FetchBufDesc::fetchDepth
int fetchDepth
Definition: fetch_unit.hh:230
compute_unit.hh
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::Wavefront::stopFetch
bool stopFetch()
Definition: wavefront.cc:729
gem5::ComputeUnit::ITLBPort::retries
std::deque< PacketPtr > retries
here we queue all the translation requests that were not successfully sent.
Definition: compute_unit.hh:736
gpu_static_inst.hh
gem5::FetchUnit::timingSim
bool timingSim
Definition: fetch_unit.hh:243
gem5::Wavefront::pendingFetch
bool pendingFetch
Definition: wavefront.hh:113
gem5::ComputeUnit::SQCPort::SenderState::wavefront
Wavefront * wavefront
Definition: compute_unit.hh:615
gem5::FetchUnit::FetchBufDesc::splitDecode
bool splitDecode() const
check if the next instruction to be processed out of the fetch buffer is split across the end/beginni...
Definition: fetch_unit.cc:614
gem5::Wavefront::pc
Addr pc() const
Definition: wavefront.cc:1365
gem5::FetchUnit::fetchDepth
int fetchDepth
number of cache lines we can fetch and buffer.
Definition: fetch_unit.hh:272
std::vector
STL vector class.
Definition: stl.hh:37
fetch_unit.hh
gem5::FetchUnit::fetchBuf
std::vector< FetchBufDesc > fetchBuf
Definition: fetch_unit.hh:265
gem5::ComputeUnit::SQCPort::retries
std::deque< std::pair< PacketPtr, Wavefront * > > retries
Definition: compute_unit.hh:626
gem5::FetchUnit::init
void init()
Definition: fetch_unit.cc:65
gem5::GPUStaticInst
Definition: gpu_static_inst.hh:63
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::FetchUnit::FetchBufDesc::maxFbSize
int maxFbSize
Definition: fetch_unit.hh:234
gem5::ComputeUnit::shader
Shader * shader
Definition: compute_unit.hh:355
gem5::ruby::makeLineAddress
Addr makeLineAddress(Addr addr)
Definition: Address.cc:60
gem5::isPowerOf2
static constexpr bool isPowerOf2(const T &n)
Definition: intmath.hh:98
gem5::ComputeUnit::ITLBPort::stallPort
void stallPort()
Definition: compute_unit.hh:729
gem5::ComputeUnit::cu_id
int cu_id
Definition: compute_unit.hh:294
wavefront.hh
gem5::BaseMMU::Execute
@ Execute
Definition: mmu.hh:53
gem5::Packet::dataStatic
void dataStatic(T *p)
Set the data pointer to the following value that should not be freed.
Definition: packet.hh:1134
gem5::FetchUnit::fetchQueue
std::vector< Wavefront * > fetchQueue
Definition: fetch_unit.hh:255
gem5::FetchUnit::FetchBufDesc::fetchDone
void fetchDone(Addr vaddr)
Definition: fetch_unit.cc:450
gem5::Wavefront::maxIbSize
int maxIbSize
Definition: wavefront.hh:109
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::FetchUnit::FetchBufDesc::wavefront
Wavefront * wavefront
Definition: fetch_unit.hh:239
gem5::ComputeUnit
Definition: compute_unit.hh:203
gem5::FetchUnit::decoder
TheGpuISA::Decoder decoder
Definition: fetch_unit.hh:245
gem5::RequestPort::sendFunctional
void sendFunctional(PacketPtr pkt) const
Send a functional request packet, where the data is instantly updated everywhere in the memory system...
Definition: port.hh:485
gem5::FetchUnit::FetchBufDesc::readPtr
uint8_t * readPtr
pointer that points to the next chunk of inst data to be decoded.
Definition: fetch_unit.hh:228
gem5::FetchUnit::FetchBufDesc::nextFetchAddr
Addr nextFetchAddr()
Definition: fetch_unit.cc:370
gem5::ComputeUnit::sqcTLBPort
ITLBPort sqcTLBPort
Definition: compute_unit.hh:857
gem5::FetchUnit::FetchBufDesc::flushBuf
void flushBuf()
Definition: fetch_unit.cc:348
bitfield.hh
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::FetchUnit::initiateFetch
void initiateFetch(Wavefront *wavefront)
Definition: fetch_unit.cc:136
gem5::Wavefront::wfSlotId
const int wfSlotId
Definition: wavefront.hh:98
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::FetchUnit::FetchBufDesc::decodeSplitInst
void decodeSplitInst()
Definition: fetch_unit.cc:576
gem5::Request::INST_FETCH
@ INST_FETCH
The request was an instruction fetch.
Definition: request.hh:115
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::FetchUnit::FetchBufDesc
fetch buffer descriptor.
Definition: fetch_unit.hh:75
gem5::FetchUnit::FetchBufDesc::bufEnd
uint8_t * bufEnd
Definition: fetch_unit.hh:223
gem5::FetchUnit::FetchUnit
FetchUnit(const ComputeUnitParams &p, ComputeUnit &cu)
Definition: fetch_unit.cc:52
gpu_dyn_inst.hh
gem5::FetchUnit::FetchBufDesc::fetchBytesRemaining
int fetchBytesRemaining() const
calculates the number of fetched bytes that have yet to be decoded.
Definition: fetch_unit.cc:626
gem5::ComputeUnit::cacheLineSize
int cacheLineSize() const
Definition: compute_unit.hh:413
gem5::GPUStaticInst::instSize
virtual int instSize() const =0
gem5::roundDown
static constexpr T roundDown(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:279
gem5::Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:361
gem5::Wavefront::wfDynId
uint64_t wfDynId
Definition: wavefront.hh:228
RubySystem.hh
gem5::FetchUnit::FetchBufDesc::decodeInsts
void decodeInsts()
each time the fetch stage is ticked, we check if there are any data in the fetch buffer that may be d...
Definition: fetch_unit.cc:538
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Packet::senderState
SenderState * senderState
This packet's sender state.
Definition: packet.hh:534
gem5::FetchUnit::bindWaveList
void bindWaveList(std::vector< Wavefront * > *list)
Definition: fetch_unit.cc:317
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:51
gem5::FetchUnit::FetchBufDesc::allocateBuf
void allocateBuf(int fetch_depth, int cache_line_size, Wavefront *wf)
allocate the fetch buffer space, and set the fetch depth (number of lines that may be buffered),...
Definition: fetch_unit.cc:324
gem5::Shader::timingSim
bool timingSim
Definition: shader.hh:191
gem5::ComputeUnit::getCacheLineBits
int getCacheLineBits() const
Definition: compute_unit.hh:414
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::FetchUnit::FetchBufDesc::bufStart
uint8_t * bufStart
raw instruction buffer.
Definition: fetch_unit.hh:222
gem5::FetchUnit::FetchBufDesc::reserveBuf
void reserveBuf(Addr vaddr)
reserve an entry in the fetch buffer for PC = vaddr,
Definition: fetch_unit.cc:425
gem5::FetchUnit::fetchScheduler
Scheduler fetchScheduler
Definition: fetch_unit.hh:251
gem5::FetchUnit::FetchBufDesc::checkWaveReleaseBuf
void checkWaveReleaseBuf()
checks if the wavefront can release any of its fetch buffer entries.
Definition: fetch_unit.cc:481
gem5::Wavefront::S_WAITCNT
@ S_WAITCNT
wavefront has unsatisfied wait counts
Definition: wavefront.hh:90
gem5::FetchUnit::globalFetchUnitID
static uint32_t globalFetchUnitID
Definition: fetch_unit.hh:68
gem5::Scheduler::chooseWave
Wavefront * chooseWave()
Definition: scheduler.cc:55
gem5::floorLog2
static constexpr std::enable_if_t< std::is_integral< T >::value, int > floorLog2(T x)
Definition: intmath.hh:59
gem5::Shader::n_wf
int n_wf
Definition: shader.hh:205
gem5::FetchUnit::FetchBufDesc::cacheLineBits
int cacheLineBits
Definition: fetch_unit.hh:236
gem5::FetchUnit::waveList
std::vector< Wavefront * > * waveList
Definition: fetch_unit.hh:263
gem5::Wavefront::instructionBuffer
std::deque< GPUDynInstPtr > instructionBuffer
Definition: wavefront.hh:111
gem5::FetchUnit::fetchStatusQueue
std::vector< std::pair< Wavefront *, bool > > fetchStatusQueue
Definition: fetch_unit.hh:260
gem5::Scheduler::bindList
void bindList(std::vector< Wavefront * > *sched_list)
Definition: scheduler.cc:61
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::Wavefront::getStatus
status_e getStatus()
Definition: wavefront.hh:139
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::FetchUnit::computeUnit
ComputeUnit & computeUnit
Definition: fetch_unit.hh:244
gem5::ComputeUnit::sqcPort
SQCPort sqcPort
Definition: compute_unit.hh:855
gem5::FetchUnit::exec
void exec()
Definition: fetch_unit.cc:84
gem5::FetchUnit::FetchBufDesc::hasFetchDataToProcess
bool hasFetchDataToProcess() const
checks if the buffer contains valid data.
Definition: fetch_unit.cc:475
gem5::FetchUnit::FetchBufDesc::freeList
std::deque< uint8_t * > freeList
represents the fetch buffer free list.
Definition: fetch_unit.hh:216
gem5::Wavefront::dropFetch
bool dropFetch
Definition: wavefront.hh:114
gem5::Gcn3ISA::RawMachInst
uint64_t RawMachInst
used to represnt a GPU inst in its raw format.
Definition: gpu_types.hh:44
gem5::FetchUnit::fetch
void fetch(PacketPtr pkt, Wavefront *wavefront)
Definition: fetch_unit.cc:221
gem5::ComputeUnit::requestorId
RequestorID requestorId()
Definition: compute_unit.hh:462
gem5::SenderState
RubyTester::SenderState SenderState
Definition: Check.cc:40
gem5::FetchUnit::processFetchReturn
void processFetchReturn(PacketPtr pkt)
Definition: fetch_unit.cc:285
gem5::Wavefront::simdId
const int simdId
Definition: wavefront.hh:101

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