gem5 v24.0.0.0
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vopc.cc
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1/*
2 * Copyright (c) 2024 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include "arch/amdgpu/vega/insts/instructions.hh"
33
34namespace gem5
35{
36
37namespace VegaISA
38{
39 // --- Inst_VOPC__V_CMP_CLASS_F32 class methods ---
40
41 Inst_VOPC__V_CMP_CLASS_F32::Inst_VOPC__V_CMP_CLASS_F32(InFmt_VOPC *iFmt)
42 : Inst_VOPC(iFmt, "v_cmp_class_f32")
43 {
44 setFlag(ALU);
45 setFlag(F32);
46 } // Inst_VOPC__V_CMP_CLASS_F32
47
48 Inst_VOPC__V_CMP_CLASS_F32::~Inst_VOPC__V_CMP_CLASS_F32()
49 {
50 } // ~Inst_VOPC__V_CMP_CLASS_F32
51
52 // --- description from .arch file ---
53 // VCC = IEEE numeric class function specified in S1.u, performed on S0.f
54 // The function reports true if the floating point value is *any* of the
55 // --- numeric types selected in S1.u according to the following list:
56 // S1.u[0] -- value is a signaling NaN.
57 // S1.u[1] -- value is a quiet NaN.
58 // S1.u[2] -- value is negative infinity.
59 // S1.u[3] -- value is a negative normal value.
60 // S1.u[4] -- value is a negative denormal value.
61 // S1.u[5] -- value is negative zero.
62 // S1.u[6] -- value is positive zero.
63 // S1.u[7] -- value is a positive denormal value.
64 // S1.u[8] -- value is a positive normal value.
65 // S1.u[9] -- value is positive infinity.
66 void
67 Inst_VOPC__V_CMP_CLASS_F32::execute(GPUDynInstPtr gpuDynInst)
68 {
69 Wavefront *wf = gpuDynInst->wavefront();
70 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
71 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
72 ConstScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
73
74 src0.readSrc();
75 src1.read();
76
77 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
78 if (wf->execMask(lane)) {
79 if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
80 // is NaN
81 if (std::isnan(src0[lane])) {
82 vcc.setBit(lane, 1);
83 continue;
84 }
85 }
86 if (bits(src1[lane], 2)) {
87 // is -infinity
88 if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
89 vcc.setBit(lane, 1);
90 continue;
91 }
92 }
93 if (bits(src1[lane], 3)) {
94 // is -normal
95 if (std::isnormal(src0[lane])
96 && std::signbit(src0[lane])) {
97 vcc.setBit(lane, 1);
98 continue;
99 }
100 }
101 if (bits(src1[lane], 4)) {
102 // is -denormal
103 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
104 && std::signbit(src0[lane])) {
105 vcc.setBit(lane, 1);
106 continue;
107 }
108 }
109 if (bits(src1[lane], 5)) {
110 // is -zero
111 if (std::fpclassify(src0[lane]) == FP_ZERO
112 && std::signbit(src0[lane])) {
113 vcc.setBit(lane, 1);
114 continue;
115 }
116 }
117 if (bits(src1[lane], 6)) {
118 // is +zero
119 if (std::fpclassify(src0[lane]) == FP_ZERO
120 && !std::signbit(src0[lane])) {
121 vcc.setBit(lane, 1);
122 continue;
123 }
124 }
125 if (bits(src1[lane], 7)) {
126 // is +denormal
127 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
128 && !std::signbit(src0[lane])) {
129 vcc.setBit(lane, 1);
130 continue;
131 }
132 }
133 if (bits(src1[lane], 8)) {
134 // is +normal
135 if (std::isnormal(src0[lane])
136 && !std::signbit(src0[lane])) {
137 vcc.setBit(lane, 1);
138 continue;
139 }
140 }
141 if (bits(src1[lane], 9)) {
142 // is +infinity
143 if (std::isinf(src0[lane]) && !std::signbit(src0[lane])) {
144 vcc.setBit(lane, 1);
145 continue;
146 }
147 }
148 }
149 }
150
151 vcc.write();
152 } // execute
153 // --- Inst_VOPC__V_CMPX_CLASS_F32 class methods ---
154
155 Inst_VOPC__V_CMPX_CLASS_F32::Inst_VOPC__V_CMPX_CLASS_F32(InFmt_VOPC *iFmt)
156 : Inst_VOPC(iFmt, "v_cmpx_class_f32")
157 {
158 setFlag(ALU);
159 setFlag(F32);
160 setFlag(WritesEXEC);
161 } // Inst_VOPC__V_CMPX_CLASS_F32
162
163 Inst_VOPC__V_CMPX_CLASS_F32::~Inst_VOPC__V_CMPX_CLASS_F32()
164 {
165 } // ~Inst_VOPC__V_CMPX_CLASS_F32
166
167 // --- description from .arch file ---
168 // EXEC, VCC = IEEE numeric class function specified in S1.u, performed on
169 // S0.f The function reports true if the floating point value is *any* of
170 // the numeric types selected in S1.u according to the following list:
171 // S1.u[0] -- value is a signaling NaN.
172 // S1.u[1] -- value is a quiet NaN.
173 // S1.u[2] -- value is negative infinity.
174 // S1.u[3] -- value is a negative normal value.
175 // S1.u[4] -- value is a negative denormal value.
176 // S1.u[5] -- value is negative zero.
177 // S1.u[6] -- value is positive zero.
178 // S1.u[7] -- value is a positive denormal value.
179 // S1.u[8] -- value is a positive normal value.
180 // S1.u[9] -- value is positive infinity.
181 void
182 Inst_VOPC__V_CMPX_CLASS_F32::execute(GPUDynInstPtr gpuDynInst)
183 {
184 Wavefront *wf = gpuDynInst->wavefront();
185 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
186 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
187 ConstScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
188
189 src0.readSrc();
190 src1.read();
191
192 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
193 if (wf->execMask(lane)) {
194 if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
195 // is NaN
196 if (std::isnan(src0[lane])) {
197 vcc.setBit(lane, 1);
198 continue;
199 }
200 }
201 if (bits(src1[lane], 2)) {
202 // is -infinity
203 if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
204 vcc.setBit(lane, 1);
205 continue;
206 }
207 }
208 if (bits(src1[lane], 3)) {
209 // is -normal
210 if (std::isnormal(src0[lane])
211 && std::signbit(src0[lane])) {
212 vcc.setBit(lane, 1);
213 continue;
214 }
215 }
216 if (bits(src1[lane], 4)) {
217 // is -denormal
218 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
219 && std::signbit(src0[lane])) {
220 vcc.setBit(lane, 1);
221 continue;
222 }
223 }
224 if (bits(src1[lane], 5)) {
225 // is -zero
226 if (std::fpclassify(src0[lane]) == FP_ZERO
227 && std::signbit(src0[lane])) {
228 vcc.setBit(lane, 1);
229 continue;
230 }
231 }
232 if (bits(src1[lane], 6)) {
233 // is +zero
234 if (std::fpclassify(src0[lane]) == FP_ZERO
235 && !std::signbit(src0[lane])) {
236 vcc.setBit(lane, 1);
237 continue;
238 }
239 }
240 if (bits(src1[lane], 7)) {
241 // is +denormal
242 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
243 && !std::signbit(src0[lane])) {
244 vcc.setBit(lane, 1);
245 continue;
246 }
247 }
248 if (bits(src1[lane], 8)) {
249 // is +normal
250 if (std::isnormal(src0[lane])
251 && !std::signbit(src0[lane])) {
252 vcc.setBit(lane, 1);
253 continue;
254 }
255 }
256 if (bits(src1[lane], 9)) {
257 // is +infinity
258 if (std::isinf(src0[lane]) && !std::signbit(src0[lane])) {
259 vcc.setBit(lane, 1);
260 continue;
261 }
262 }
263 }
264 }
265
266 vcc.write();
267 wf->execMask() = vcc.rawData();
268 } // execute
269 // --- Inst_VOPC__V_CMP_CLASS_F64 class methods ---
270
271 Inst_VOPC__V_CMP_CLASS_F64::Inst_VOPC__V_CMP_CLASS_F64(InFmt_VOPC *iFmt)
272 : Inst_VOPC(iFmt, "v_cmp_class_f64")
273 {
274 setFlag(ALU);
275 setFlag(F64);
276 } // Inst_VOPC__V_CMP_CLASS_F64
277
278 Inst_VOPC__V_CMP_CLASS_F64::~Inst_VOPC__V_CMP_CLASS_F64()
279 {
280 } // ~Inst_VOPC__V_CMP_CLASS_F64
281
282 // --- description from .arch file ---
283 // VCC = IEEE numeric class function specified in S1.u, performed on S0.d
284 // The function reports true if the floating point value is *any* of the
285 // --- numeric types selected in S1.u according to the following list:
286 // S1.u[0] -- value is a signaling NaN.
287 // S1.u[1] -- value is a quiet NaN.
288 // S1.u[2] -- value is negative infinity.
289 // S1.u[3] -- value is a negative normal value.
290 // S1.u[4] -- value is a negative denormal value.
291 // S1.u[5] -- value is negative zero.
292 // S1.u[6] -- value is positive zero.
293 // S1.u[7] -- value is a positive denormal value.
294 // S1.u[8] -- value is a positive normal value.
295 // S1.u[9] -- value is positive infinity.
296 void
297 Inst_VOPC__V_CMP_CLASS_F64::execute(GPUDynInstPtr gpuDynInst)
298 {
299 Wavefront *wf = gpuDynInst->wavefront();
300 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
301 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
302 ConstScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
303
304 src0.readSrc();
305 src1.read();
306
307 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
308 if (wf->execMask(lane)) {
309 if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
310 // is NaN
311 if (std::isnan(src0[lane])) {
312 vcc.setBit(lane, 1);
313 continue;
314 }
315 }
316 if (bits(src1[lane], 2)) {
317 // is -infinity
318 if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
319 vcc.setBit(lane, 1);
320 continue;
321 }
322 }
323 if (bits(src1[lane], 3)) {
324 // is -normal
325 if (std::isnormal(src0[lane])
326 && std::signbit(src0[lane])) {
327 vcc.setBit(lane, 1);
328 continue;
329 }
330 }
331 if (bits(src1[lane], 4)) {
332 // is -denormal
333 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
334 && std::signbit(src0[lane])) {
335 vcc.setBit(lane, 1);
336 continue;
337 }
338 }
339 if (bits(src1[lane], 5)) {
340 // is -zero
341 if (std::fpclassify(src0[lane]) == FP_ZERO
342 && std::signbit(src0[lane])) {
343 vcc.setBit(lane, 1);
344 continue;
345 }
346 }
347 if (bits(src1[lane], 6)) {
348 // is +zero
349 if (std::fpclassify(src0[lane]) == FP_ZERO
350 && !std::signbit(src0[lane])) {
351 vcc.setBit(lane, 1);
352 continue;
353 }
354 }
355 if (bits(src1[lane], 7)) {
356 // is +denormal
357 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
358 && !std::signbit(src0[lane])) {
359 vcc.setBit(lane, 1);
360 continue;
361 }
362 }
363 if (bits(src1[lane], 8)) {
364 // is +normal
365 if (std::isnormal(src0[lane])
366 && !std::signbit(src0[lane])) {
367 vcc.setBit(lane, 1);
368 continue;
369 }
370 }
371 if (bits(src1[lane], 9)) {
372 // is +infinity
373 if (std::isinf(src0[lane])
374 && !std::signbit(src0[lane])) {
375 vcc.setBit(lane, 1);
376 continue;
377 }
378 }
379 }
380 }
381
382 vcc.write();
383 } // execute
384 // --- Inst_VOPC__V_CMPX_CLASS_F64 class methods ---
385
386 Inst_VOPC__V_CMPX_CLASS_F64::Inst_VOPC__V_CMPX_CLASS_F64(InFmt_VOPC *iFmt)
387 : Inst_VOPC(iFmt, "v_cmpx_class_f64")
388 {
389 setFlag(ALU);
390 setFlag(F64);
391 setFlag(WritesEXEC);
392 } // Inst_VOPC__V_CMPX_CLASS_F64
393
394 Inst_VOPC__V_CMPX_CLASS_F64::~Inst_VOPC__V_CMPX_CLASS_F64()
395 {
396 } // ~Inst_VOPC__V_CMPX_CLASS_F64
397
398 // --- description from .arch file ---
399 // EXEC, VCC = IEEE numeric class function specified in S1.u, performed on
400 // S0.d The function reports true if the floating point value is *any* of
401 // the numeric types selected in S1.u according to the following list:
402 // S1.u[0] -- value is a signaling NaN.
403 // S1.u[1] -- value is a quiet NaN.
404 // S1.u[2] -- value is negative infinity.
405 // S1.u[3] -- value is a negative normal value.
406 // S1.u[4] -- value is a negative denormal value.
407 // S1.u[5] -- value is negative zero.
408 // S1.u[6] -- value is positive zero.
409 // S1.u[7] -- value is a positive denormal value.
410 // S1.u[8] -- value is a positive normal value.
411 // S1.u[9] -- value is positive infinity.
412 void
413 Inst_VOPC__V_CMPX_CLASS_F64::execute(GPUDynInstPtr gpuDynInst)
414 {
415 Wavefront *wf = gpuDynInst->wavefront();
416 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
417 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
418 ConstScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
419
420 src0.readSrc();
421 src1.read();
422
423 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
424 if (wf->execMask(lane)) {
425 if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
426 // is NaN
427 if (std::isnan(src0[lane])) {
428 vcc.setBit(lane, 1);
429 continue;
430 }
431 }
432 if (bits(src1[lane], 2)) {
433 // is -infinity
434 if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
435 vcc.setBit(lane, 1);
436 continue;
437 }
438 }
439 if (bits(src1[lane], 3)) {
440 // is -normal
441 if (std::isnormal(src0[lane])
442 && std::signbit(src0[lane])) {
443 vcc.setBit(lane, 1);
444 continue;
445 }
446 }
447 if (bits(src1[lane], 4)) {
448 // is -denormal
449 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
450 && std::signbit(src0[lane])) {
451 vcc.setBit(lane, 1);
452 continue;
453 }
454 }
455 if (bits(src1[lane], 5)) {
456 // is -zero
457 if (std::fpclassify(src0[lane]) == FP_ZERO
458 && std::signbit(src0[lane])) {
459 vcc.setBit(lane, 1);
460 continue;
461 }
462 }
463 if (bits(src1[lane], 6)) {
464 // is +zero
465 if (std::fpclassify(src0[lane]) == FP_ZERO
466 && !std::signbit(src0[lane])) {
467 vcc.setBit(lane, 1);
468 continue;
469 }
470 }
471 if (bits(src1[lane], 7)) {
472 // is +denormal
473 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
474 && !std::signbit(src0[lane])) {
475 vcc.setBit(lane, 1);
476 continue;
477 }
478 }
479 if (bits(src1[lane], 8)) {
480 // is +normal
481 if (std::isnormal(src0[lane])
482 && !std::signbit(src0[lane])) {
483 vcc.setBit(lane, 1);
484 continue;
485 }
486 }
487 if (bits(src1[lane], 9)) {
488 // is +infinity
489 if (std::isinf(src0[lane])
490 && !std::signbit(src0[lane])) {
491 vcc.setBit(lane, 1);
492 continue;
493 }
494 }
495 }
496 }
497
498 vcc.write();
499 wf->execMask() = vcc.rawData();
500 } // execute
501 // --- Inst_VOPC__V_CMP_CLASS_F16 class methods ---
502
503 Inst_VOPC__V_CMP_CLASS_F16::Inst_VOPC__V_CMP_CLASS_F16(InFmt_VOPC *iFmt)
504 : Inst_VOPC(iFmt, "v_cmp_class_f16")
505 {
506 setFlag(ALU);
507 setFlag(F16);
508 } // Inst_VOPC__V_CMP_CLASS_F16
509
510 Inst_VOPC__V_CMP_CLASS_F16::~Inst_VOPC__V_CMP_CLASS_F16()
511 {
512 } // ~Inst_VOPC__V_CMP_CLASS_F16
513
514 // --- description from .arch file ---
515 // VCC = IEEE numeric class function specified in S1.u, performed on S0.f16
516 // The function reports true if the floating point value is *any* of the
517 // --- numeric types selected in S1.u according to the following list:
518 // S1.u[0] -- value is a signaling NaN.
519 // S1.u[1] -- value is a quiet NaN.
520 // S1.u[2] -- value is negative infinity.
521 // S1.u[3] -- value is a negative normal value.
522 // S1.u[4] -- value is a negative denormal value.
523 // S1.u[5] -- value is negative zero.
524 // S1.u[6] -- value is positive zero.
525 // S1.u[7] -- value is a positive denormal value.
526 // S1.u[8] -- value is a positive normal value.
527 // S1.u[9] -- value is positive infinity.
528 void
533 // --- Inst_VOPC__V_CMPX_CLASS_F16 class methods ---
534
535 Inst_VOPC__V_CMPX_CLASS_F16::Inst_VOPC__V_CMPX_CLASS_F16(InFmt_VOPC *iFmt)
536 : Inst_VOPC(iFmt, "v_cmpx_class_f16")
537 {
538 setFlag(ALU);
539 setFlag(F16);
540 setFlag(WritesEXEC);
541 } // Inst_VOPC__V_CMPX_CLASS_F16
542
543 Inst_VOPC__V_CMPX_CLASS_F16::~Inst_VOPC__V_CMPX_CLASS_F16()
544 {
545 } // ~Inst_VOPC__V_CMPX_CLASS_F16
546
547 // --- description from .arch file ---
548 // EXEC, VCC = IEEE numeric class function specified in S1.u, performed on
549 // --- S0.f16
550 // The function reports true if the floating point value is *any* of the
551 // --- numeric types selected in S1.u according to the following list:
552 // S1.u[0] -- value is a signaling NaN.
553 // S1.u[1] -- value is a quiet NaN.
554 // S1.u[2] -- value is negative infinity.
555 // S1.u[3] -- value is a negative normal value.
556 // S1.u[4] -- value is a negative denormal value.
557 // S1.u[5] -- value is negative zero.
558 // S1.u[6] -- value is positive zero.
559 // S1.u[7] -- value is a positive denormal value.
560 // S1.u[8] -- value is a positive normal value.
561 // S1.u[9] -- value is positive infinity.
562 void
567 // --- Inst_VOPC__V_CMP_F_F16 class methods ---
568
569 Inst_VOPC__V_CMP_F_F16::Inst_VOPC__V_CMP_F_F16(InFmt_VOPC *iFmt)
570 : Inst_VOPC(iFmt, "v_cmp_f_f16")
571 {
572 setFlag(ALU);
573 setFlag(F16);
574 } // Inst_VOPC__V_CMP_F_F16
575
576 Inst_VOPC__V_CMP_F_F16::~Inst_VOPC__V_CMP_F_F16()
577 {
578 } // ~Inst_VOPC__V_CMP_F_F16
579
580 // --- description from .arch file ---
581 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
582 void
583 Inst_VOPC__V_CMP_F_F16::execute(GPUDynInstPtr gpuDynInst)
584 {
585 panicUnimplemented();
586 } // execute
587 // --- Inst_VOPC__V_CMP_LT_F16 class methods ---
588
589 Inst_VOPC__V_CMP_LT_F16::Inst_VOPC__V_CMP_LT_F16(InFmt_VOPC *iFmt)
590 : Inst_VOPC(iFmt, "v_cmp_lt_f16")
591 {
592 setFlag(ALU);
593 setFlag(F16);
594 } // Inst_VOPC__V_CMP_LT_F16
595
596 Inst_VOPC__V_CMP_LT_F16::~Inst_VOPC__V_CMP_LT_F16()
597 {
598 } // ~Inst_VOPC__V_CMP_LT_F16
599
600 // --- description from .arch file ---
601 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
602 void
603 Inst_VOPC__V_CMP_LT_F16::execute(GPUDynInstPtr gpuDynInst)
604 {
605 panicUnimplemented();
606 } // execute
607 // --- Inst_VOPC__V_CMP_EQ_F16 class methods ---
608
609 Inst_VOPC__V_CMP_EQ_F16::Inst_VOPC__V_CMP_EQ_F16(InFmt_VOPC *iFmt)
610 : Inst_VOPC(iFmt, "v_cmp_eq_f16")
611 {
612 setFlag(ALU);
613 setFlag(F16);
614 } // Inst_VOPC__V_CMP_EQ_F16
615
616 Inst_VOPC__V_CMP_EQ_F16::~Inst_VOPC__V_CMP_EQ_F16()
617 {
618 } // ~Inst_VOPC__V_CMP_EQ_F16
619
620 // --- description from .arch file ---
621 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
622 void
623 Inst_VOPC__V_CMP_EQ_F16::execute(GPUDynInstPtr gpuDynInst)
624 {
625 panicUnimplemented();
626 } // execute
627 // --- Inst_VOPC__V_CMP_LE_F16 class methods ---
628
629 Inst_VOPC__V_CMP_LE_F16::Inst_VOPC__V_CMP_LE_F16(InFmt_VOPC *iFmt)
630 : Inst_VOPC(iFmt, "v_cmp_le_f16")
631 {
632 setFlag(ALU);
633 setFlag(F16);
634 } // Inst_VOPC__V_CMP_LE_F16
635
636 Inst_VOPC__V_CMP_LE_F16::~Inst_VOPC__V_CMP_LE_F16()
637 {
638 } // ~Inst_VOPC__V_CMP_LE_F16
639
640 // --- description from .arch file ---
641 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
642 void
643 Inst_VOPC__V_CMP_LE_F16::execute(GPUDynInstPtr gpuDynInst)
644 {
645 panicUnimplemented();
646 } // execute
647 // --- Inst_VOPC__V_CMP_GT_F16 class methods ---
648
649 Inst_VOPC__V_CMP_GT_F16::Inst_VOPC__V_CMP_GT_F16(InFmt_VOPC *iFmt)
650 : Inst_VOPC(iFmt, "v_cmp_gt_f16")
651 {
652 setFlag(ALU);
653 setFlag(F16);
654 } // Inst_VOPC__V_CMP_GT_F16
655
656 Inst_VOPC__V_CMP_GT_F16::~Inst_VOPC__V_CMP_GT_F16()
657 {
658 } // ~Inst_VOPC__V_CMP_GT_F16
659
660 // --- description from .arch file ---
661 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
662 void
663 Inst_VOPC__V_CMP_GT_F16::execute(GPUDynInstPtr gpuDynInst)
664 {
665 panicUnimplemented();
666 } // execute
667 // --- Inst_VOPC__V_CMP_LG_F16 class methods ---
668
669 Inst_VOPC__V_CMP_LG_F16::Inst_VOPC__V_CMP_LG_F16(InFmt_VOPC *iFmt)
670 : Inst_VOPC(iFmt, "v_cmp_lg_f16")
671 {
672 setFlag(ALU);
673 setFlag(F16);
674 } // Inst_VOPC__V_CMP_LG_F16
675
676 Inst_VOPC__V_CMP_LG_F16::~Inst_VOPC__V_CMP_LG_F16()
677 {
678 } // ~Inst_VOPC__V_CMP_LG_F16
679
680 // --- description from .arch file ---
681 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
682 void
683 Inst_VOPC__V_CMP_LG_F16::execute(GPUDynInstPtr gpuDynInst)
684 {
685 panicUnimplemented();
686 } // execute
687 // --- Inst_VOPC__V_CMP_GE_F16 class methods ---
688
689 Inst_VOPC__V_CMP_GE_F16::Inst_VOPC__V_CMP_GE_F16(InFmt_VOPC *iFmt)
690 : Inst_VOPC(iFmt, "v_cmp_ge_f16")
691 {
692 setFlag(ALU);
693 setFlag(F16);
694 } // Inst_VOPC__V_CMP_GE_F16
695
696 Inst_VOPC__V_CMP_GE_F16::~Inst_VOPC__V_CMP_GE_F16()
697 {
698 } // ~Inst_VOPC__V_CMP_GE_F16
699
700 // --- description from .arch file ---
701 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
702 void
703 Inst_VOPC__V_CMP_GE_F16::execute(GPUDynInstPtr gpuDynInst)
704 {
705 panicUnimplemented();
706 } // execute
707 // --- Inst_VOPC__V_CMP_O_F16 class methods ---
708
709 Inst_VOPC__V_CMP_O_F16::Inst_VOPC__V_CMP_O_F16(InFmt_VOPC *iFmt)
710 : Inst_VOPC(iFmt, "v_cmp_o_f16")
711 {
712 setFlag(ALU);
713 setFlag(F16);
714 } // Inst_VOPC__V_CMP_O_F16
715
716 Inst_VOPC__V_CMP_O_F16::~Inst_VOPC__V_CMP_O_F16()
717 {
718 } // ~Inst_VOPC__V_CMP_O_F16
719
720 // --- description from .arch file ---
721 // D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC encoding.
722 void
723 Inst_VOPC__V_CMP_O_F16::execute(GPUDynInstPtr gpuDynInst)
724 {
725 panicUnimplemented();
726 } // execute
727 // --- Inst_VOPC__V_CMP_U_F16 class methods ---
728
729 Inst_VOPC__V_CMP_U_F16::Inst_VOPC__V_CMP_U_F16(InFmt_VOPC *iFmt)
730 : Inst_VOPC(iFmt, "v_cmp_u_f16")
731 {
732 setFlag(ALU);
733 setFlag(F16);
734 } // Inst_VOPC__V_CMP_U_F16
735
736 Inst_VOPC__V_CMP_U_F16::~Inst_VOPC__V_CMP_U_F16()
737 {
738 } // ~Inst_VOPC__V_CMP_U_F16
739
740 // --- description from .arch file ---
741 // D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC encoding.
742 void
743 Inst_VOPC__V_CMP_U_F16::execute(GPUDynInstPtr gpuDynInst)
744 {
745 panicUnimplemented();
746 } // execute
747 // --- Inst_VOPC__V_CMP_NGE_F16 class methods ---
748
749 Inst_VOPC__V_CMP_NGE_F16::Inst_VOPC__V_CMP_NGE_F16(InFmt_VOPC *iFmt)
750 : Inst_VOPC(iFmt, "v_cmp_nge_f16")
751 {
752 setFlag(ALU);
753 setFlag(F16);
754 } // Inst_VOPC__V_CMP_NGE_F16
755
756 Inst_VOPC__V_CMP_NGE_F16::~Inst_VOPC__V_CMP_NGE_F16()
757 {
758 } // ~Inst_VOPC__V_CMP_NGE_F16
759
760 // --- description from .arch file ---
761 // D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
762 void
763 Inst_VOPC__V_CMP_NGE_F16::execute(GPUDynInstPtr gpuDynInst)
764 {
765 panicUnimplemented();
766 } // execute
767 // --- Inst_VOPC__V_CMP_NLG_F16 class methods ---
768
769 Inst_VOPC__V_CMP_NLG_F16::Inst_VOPC__V_CMP_NLG_F16(InFmt_VOPC *iFmt)
770 : Inst_VOPC(iFmt, "v_cmp_nlg_f16")
771 {
772 setFlag(ALU);
773 setFlag(F16);
774 } // Inst_VOPC__V_CMP_NLG_F16
775
776 Inst_VOPC__V_CMP_NLG_F16::~Inst_VOPC__V_CMP_NLG_F16()
777 {
778 } // ~Inst_VOPC__V_CMP_NLG_F16
779
780 // --- description from .arch file ---
781 // D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
782 void
783 Inst_VOPC__V_CMP_NLG_F16::execute(GPUDynInstPtr gpuDynInst)
784 {
785 panicUnimplemented();
786 } // execute
787 // --- Inst_VOPC__V_CMP_NGT_F16 class methods ---
788
789 Inst_VOPC__V_CMP_NGT_F16::Inst_VOPC__V_CMP_NGT_F16(InFmt_VOPC *iFmt)
790 : Inst_VOPC(iFmt, "v_cmp_ngt_f16")
791 {
792 setFlag(ALU);
793 setFlag(F16);
794 } // Inst_VOPC__V_CMP_NGT_F16
795
796 Inst_VOPC__V_CMP_NGT_F16::~Inst_VOPC__V_CMP_NGT_F16()
797 {
798 } // ~Inst_VOPC__V_CMP_NGT_F16
799
800 // --- description from .arch file ---
801 // D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
802 void
803 Inst_VOPC__V_CMP_NGT_F16::execute(GPUDynInstPtr gpuDynInst)
804 {
805 panicUnimplemented();
806 } // execute
807 // --- Inst_VOPC__V_CMP_NLE_F16 class methods ---
808
809 Inst_VOPC__V_CMP_NLE_F16::Inst_VOPC__V_CMP_NLE_F16(InFmt_VOPC *iFmt)
810 : Inst_VOPC(iFmt, "v_cmp_nle_f16")
811 {
812 setFlag(ALU);
813 setFlag(F16);
814 } // Inst_VOPC__V_CMP_NLE_F16
815
816 Inst_VOPC__V_CMP_NLE_F16::~Inst_VOPC__V_CMP_NLE_F16()
817 {
818 } // ~Inst_VOPC__V_CMP_NLE_F16
819
820 // --- description from .arch file ---
821 // D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
822 void
823 Inst_VOPC__V_CMP_NLE_F16::execute(GPUDynInstPtr gpuDynInst)
824 {
825 panicUnimplemented();
826 } // execute
827 // --- Inst_VOPC__V_CMP_NEQ_F16 class methods ---
828
829 Inst_VOPC__V_CMP_NEQ_F16::Inst_VOPC__V_CMP_NEQ_F16(InFmt_VOPC *iFmt)
830 : Inst_VOPC(iFmt, "v_cmp_neq_f16")
831 {
832 setFlag(ALU);
833 setFlag(F16);
834 } // Inst_VOPC__V_CMP_NEQ_F16
835
836 Inst_VOPC__V_CMP_NEQ_F16::~Inst_VOPC__V_CMP_NEQ_F16()
837 {
838 } // ~Inst_VOPC__V_CMP_NEQ_F16
839
840 // --- description from .arch file ---
841 // D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
842 void
843 Inst_VOPC__V_CMP_NEQ_F16::execute(GPUDynInstPtr gpuDynInst)
844 {
845 panicUnimplemented();
846 } // execute
847 // --- Inst_VOPC__V_CMP_NLT_F16 class methods ---
848
849 Inst_VOPC__V_CMP_NLT_F16::Inst_VOPC__V_CMP_NLT_F16(InFmt_VOPC *iFmt)
850 : Inst_VOPC(iFmt, "v_cmp_nlt_f16")
851 {
852 setFlag(ALU);
853 setFlag(F16);
854 } // Inst_VOPC__V_CMP_NLT_F16
855
856 Inst_VOPC__V_CMP_NLT_F16::~Inst_VOPC__V_CMP_NLT_F16()
857 {
858 } // ~Inst_VOPC__V_CMP_NLT_F16
859
860 // --- description from .arch file ---
861 // D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
862 void
863 Inst_VOPC__V_CMP_NLT_F16::execute(GPUDynInstPtr gpuDynInst)
864 {
865 panicUnimplemented();
866 } // execute
867 // --- Inst_VOPC__V_CMP_TRU_F16 class methods ---
868
869 Inst_VOPC__V_CMP_TRU_F16::Inst_VOPC__V_CMP_TRU_F16(InFmt_VOPC *iFmt)
870 : Inst_VOPC(iFmt, "v_cmp_tru_f16")
871 {
872 setFlag(ALU);
873 setFlag(F16);
874 } // Inst_VOPC__V_CMP_TRU_F16
875
876 Inst_VOPC__V_CMP_TRU_F16::~Inst_VOPC__V_CMP_TRU_F16()
877 {
878 } // ~Inst_VOPC__V_CMP_TRU_F16
879
880 // --- description from .arch file ---
881 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
882 void
883 Inst_VOPC__V_CMP_TRU_F16::execute(GPUDynInstPtr gpuDynInst)
884 {
885 panicUnimplemented();
886 } // execute
887 // --- Inst_VOPC__V_CMPX_F_F16 class methods ---
888
889 Inst_VOPC__V_CMPX_F_F16::Inst_VOPC__V_CMPX_F_F16(InFmt_VOPC *iFmt)
890 : Inst_VOPC(iFmt, "v_cmpx_f_f16")
891 {
892 setFlag(ALU);
893 setFlag(F16);
894 setFlag(WritesEXEC);
895 } // Inst_VOPC__V_CMPX_F_F16
896
897 Inst_VOPC__V_CMPX_F_F16::~Inst_VOPC__V_CMPX_F_F16()
898 {
899 } // ~Inst_VOPC__V_CMPX_F_F16
900
901 // --- description from .arch file ---
902 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
903 void
904 Inst_VOPC__V_CMPX_F_F16::execute(GPUDynInstPtr gpuDynInst)
905 {
906 panicUnimplemented();
907 } // execute
908 // --- Inst_VOPC__V_CMPX_LT_F16 class methods ---
909
910 Inst_VOPC__V_CMPX_LT_F16::Inst_VOPC__V_CMPX_LT_F16(InFmt_VOPC *iFmt)
911 : Inst_VOPC(iFmt, "v_cmpx_lt_f16")
912 {
913 setFlag(ALU);
914 setFlag(F16);
915 setFlag(WritesEXEC);
916 } // Inst_VOPC__V_CMPX_LT_F16
917
918 Inst_VOPC__V_CMPX_LT_F16::~Inst_VOPC__V_CMPX_LT_F16()
919 {
920 } // ~Inst_VOPC__V_CMPX_LT_F16
921
922 // --- description from .arch file ---
923 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
924 void
925 Inst_VOPC__V_CMPX_LT_F16::execute(GPUDynInstPtr gpuDynInst)
926 {
927 panicUnimplemented();
928 } // execute
929 // --- Inst_VOPC__V_CMPX_EQ_F16 class methods ---
930
931 Inst_VOPC__V_CMPX_EQ_F16::Inst_VOPC__V_CMPX_EQ_F16(InFmt_VOPC *iFmt)
932 : Inst_VOPC(iFmt, "v_cmpx_eq_f16")
933 {
934 setFlag(ALU);
935 setFlag(F16);
936 setFlag(WritesEXEC);
937 } // Inst_VOPC__V_CMPX_EQ_F16
938
939 Inst_VOPC__V_CMPX_EQ_F16::~Inst_VOPC__V_CMPX_EQ_F16()
940 {
941 } // ~Inst_VOPC__V_CMPX_EQ_F16
942
943 // --- description from .arch file ---
944 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
945 void
946 Inst_VOPC__V_CMPX_EQ_F16::execute(GPUDynInstPtr gpuDynInst)
947 {
948 panicUnimplemented();
949 } // execute
950 // --- Inst_VOPC__V_CMPX_LE_F16 class methods ---
951
952 Inst_VOPC__V_CMPX_LE_F16::Inst_VOPC__V_CMPX_LE_F16(InFmt_VOPC *iFmt)
953 : Inst_VOPC(iFmt, "v_cmpx_le_f16")
954 {
955 setFlag(ALU);
956 setFlag(F16);
957 setFlag(WritesEXEC);
958 } // Inst_VOPC__V_CMPX_LE_F16
959
960 Inst_VOPC__V_CMPX_LE_F16::~Inst_VOPC__V_CMPX_LE_F16()
961 {
962 } // ~Inst_VOPC__V_CMPX_LE_F16
963
964 // --- description from .arch file ---
965 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
966 void
967 Inst_VOPC__V_CMPX_LE_F16::execute(GPUDynInstPtr gpuDynInst)
968 {
969 panicUnimplemented();
970 } // execute
971 // --- Inst_VOPC__V_CMPX_GT_F16 class methods ---
972
973 Inst_VOPC__V_CMPX_GT_F16::Inst_VOPC__V_CMPX_GT_F16(InFmt_VOPC *iFmt)
974 : Inst_VOPC(iFmt, "v_cmpx_gt_f16")
975 {
976 setFlag(ALU);
977 setFlag(F16);
978 setFlag(WritesEXEC);
979 } // Inst_VOPC__V_CMPX_GT_F16
980
981 Inst_VOPC__V_CMPX_GT_F16::~Inst_VOPC__V_CMPX_GT_F16()
982 {
983 } // ~Inst_VOPC__V_CMPX_GT_F16
984
985 // --- description from .arch file ---
986 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
987 void
988 Inst_VOPC__V_CMPX_GT_F16::execute(GPUDynInstPtr gpuDynInst)
989 {
990 panicUnimplemented();
991 } // execute
992 // --- Inst_VOPC__V_CMPX_LG_F16 class methods ---
993
994 Inst_VOPC__V_CMPX_LG_F16::Inst_VOPC__V_CMPX_LG_F16(InFmt_VOPC *iFmt)
995 : Inst_VOPC(iFmt, "v_cmpx_lg_f16")
996 {
997 setFlag(ALU);
998 setFlag(F16);
999 setFlag(WritesEXEC);
1000 } // Inst_VOPC__V_CMPX_LG_F16
1001
1002 Inst_VOPC__V_CMPX_LG_F16::~Inst_VOPC__V_CMPX_LG_F16()
1003 {
1004 } // ~Inst_VOPC__V_CMPX_LG_F16
1005
1006 // --- description from .arch file ---
1007 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
1008 void
1009 Inst_VOPC__V_CMPX_LG_F16::execute(GPUDynInstPtr gpuDynInst)
1010 {
1011 panicUnimplemented();
1012 } // execute
1013 // --- Inst_VOPC__V_CMPX_GE_F16 class methods ---
1014
1015 Inst_VOPC__V_CMPX_GE_F16::Inst_VOPC__V_CMPX_GE_F16(InFmt_VOPC *iFmt)
1016 : Inst_VOPC(iFmt, "v_cmpx_ge_f16")
1017 {
1018 setFlag(ALU);
1019 setFlag(F16);
1020 setFlag(WritesEXEC);
1021 } // Inst_VOPC__V_CMPX_GE_F16
1022
1023 Inst_VOPC__V_CMPX_GE_F16::~Inst_VOPC__V_CMPX_GE_F16()
1024 {
1025 } // ~Inst_VOPC__V_CMPX_GE_F16
1026
1027 // --- description from .arch file ---
1028 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
1029 void
1030 Inst_VOPC__V_CMPX_GE_F16::execute(GPUDynInstPtr gpuDynInst)
1031 {
1032 panicUnimplemented();
1033 } // execute
1034 // --- Inst_VOPC__V_CMPX_O_F16 class methods ---
1035
1036 Inst_VOPC__V_CMPX_O_F16::Inst_VOPC__V_CMPX_O_F16(InFmt_VOPC *iFmt)
1037 : Inst_VOPC(iFmt, "v_cmpx_o_f16")
1038 {
1039 setFlag(ALU);
1040 setFlag(F16);
1041 setFlag(WritesEXEC);
1042 } // Inst_VOPC__V_CMPX_O_F16
1043
1044 Inst_VOPC__V_CMPX_O_F16::~Inst_VOPC__V_CMPX_O_F16()
1045 {
1046 } // ~Inst_VOPC__V_CMPX_O_F16
1047
1048 // --- description from .arch file ---
1049 // EXEC,D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC
1050 // encoding.
1051 void
1052 Inst_VOPC__V_CMPX_O_F16::execute(GPUDynInstPtr gpuDynInst)
1053 {
1054 panicUnimplemented();
1055 } // execute
1056 // --- Inst_VOPC__V_CMPX_U_F16 class methods ---
1057
1058 Inst_VOPC__V_CMPX_U_F16::Inst_VOPC__V_CMPX_U_F16(InFmt_VOPC *iFmt)
1059 : Inst_VOPC(iFmt, "v_cmpx_u_f16")
1060 {
1061 setFlag(ALU);
1062 setFlag(F16);
1063 setFlag(WritesEXEC);
1064 } // Inst_VOPC__V_CMPX_U_F16
1065
1066 Inst_VOPC__V_CMPX_U_F16::~Inst_VOPC__V_CMPX_U_F16()
1067 {
1068 } // ~Inst_VOPC__V_CMPX_U_F16
1069
1070 // --- description from .arch file ---
1071 // EXEC,D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC
1072 // encoding.
1073 void
1074 Inst_VOPC__V_CMPX_U_F16::execute(GPUDynInstPtr gpuDynInst)
1075 {
1076 panicUnimplemented();
1077 } // execute
1078 // --- Inst_VOPC__V_CMPX_NGE_F16 class methods ---
1079
1080 Inst_VOPC__V_CMPX_NGE_F16::Inst_VOPC__V_CMPX_NGE_F16(InFmt_VOPC *iFmt)
1081 : Inst_VOPC(iFmt, "v_cmpx_nge_f16")
1082 {
1083 setFlag(ALU);
1084 setFlag(F16);
1085 setFlag(WritesEXEC);
1086 } // Inst_VOPC__V_CMPX_NGE_F16
1087
1088 Inst_VOPC__V_CMPX_NGE_F16::~Inst_VOPC__V_CMPX_NGE_F16()
1089 {
1090 } // ~Inst_VOPC__V_CMPX_NGE_F16
1091
1092 // --- description from .arch file ---
1093 // EXEC,D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
1094 void
1095 Inst_VOPC__V_CMPX_NGE_F16::execute(GPUDynInstPtr gpuDynInst)
1096 {
1097 panicUnimplemented();
1098 } // execute
1099 // --- Inst_VOPC__V_CMPX_NLG_F16 class methods ---
1100
1101 Inst_VOPC__V_CMPX_NLG_F16::Inst_VOPC__V_CMPX_NLG_F16(InFmt_VOPC *iFmt)
1102 : Inst_VOPC(iFmt, "v_cmpx_nlg_f16")
1103 {
1104 setFlag(ALU);
1105 setFlag(F16);
1106 setFlag(WritesEXEC);
1107 } // Inst_VOPC__V_CMPX_NLG_F16
1108
1109 Inst_VOPC__V_CMPX_NLG_F16::~Inst_VOPC__V_CMPX_NLG_F16()
1110 {
1111 } // ~Inst_VOPC__V_CMPX_NLG_F16
1112
1113 // --- description from .arch file ---
1114 // EXEC,D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
1115 void
1116 Inst_VOPC__V_CMPX_NLG_F16::execute(GPUDynInstPtr gpuDynInst)
1117 {
1118 panicUnimplemented();
1119 } // execute
1120 // --- Inst_VOPC__V_CMPX_NGT_F16 class methods ---
1121
1122 Inst_VOPC__V_CMPX_NGT_F16::Inst_VOPC__V_CMPX_NGT_F16(InFmt_VOPC *iFmt)
1123 : Inst_VOPC(iFmt, "v_cmpx_ngt_f16")
1124 {
1125 setFlag(ALU);
1126 setFlag(F16);
1127 setFlag(WritesEXEC);
1128 } // Inst_VOPC__V_CMPX_NGT_F16
1129
1130 Inst_VOPC__V_CMPX_NGT_F16::~Inst_VOPC__V_CMPX_NGT_F16()
1131 {
1132 } // ~Inst_VOPC__V_CMPX_NGT_F16
1133
1134 // --- description from .arch file ---
1135 // EXEC,D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
1136 void
1137 Inst_VOPC__V_CMPX_NGT_F16::execute(GPUDynInstPtr gpuDynInst)
1138 {
1139 panicUnimplemented();
1140 } // execute
1141 // --- Inst_VOPC__V_CMPX_NLE_F16 class methods ---
1142
1143 Inst_VOPC__V_CMPX_NLE_F16::Inst_VOPC__V_CMPX_NLE_F16(InFmt_VOPC *iFmt)
1144 : Inst_VOPC(iFmt, "v_cmpx_nle_f16")
1145 {
1146 setFlag(ALU);
1147 setFlag(F16);
1148 setFlag(WritesEXEC);
1149 } // Inst_VOPC__V_CMPX_NLE_F16
1150
1151 Inst_VOPC__V_CMPX_NLE_F16::~Inst_VOPC__V_CMPX_NLE_F16()
1152 {
1153 } // ~Inst_VOPC__V_CMPX_NLE_F16
1154
1155 // --- description from .arch file ---
1156 // EXEC,D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
1157 void
1158 Inst_VOPC__V_CMPX_NLE_F16::execute(GPUDynInstPtr gpuDynInst)
1159 {
1160 panicUnimplemented();
1161 } // execute
1162 // --- Inst_VOPC__V_CMPX_NEQ_F16 class methods ---
1163
1164 Inst_VOPC__V_CMPX_NEQ_F16::Inst_VOPC__V_CMPX_NEQ_F16(InFmt_VOPC *iFmt)
1165 : Inst_VOPC(iFmt, "v_cmpx_neq_f16")
1166 {
1167 setFlag(ALU);
1168 setFlag(F16);
1169 setFlag(WritesEXEC);
1170 } // Inst_VOPC__V_CMPX_NEQ_F16
1171
1172 Inst_VOPC__V_CMPX_NEQ_F16::~Inst_VOPC__V_CMPX_NEQ_F16()
1173 {
1174 } // ~Inst_VOPC__V_CMPX_NEQ_F16
1175
1176 // --- description from .arch file ---
1177 // EXEC,D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
1178 void
1179 Inst_VOPC__V_CMPX_NEQ_F16::execute(GPUDynInstPtr gpuDynInst)
1180 {
1181 panicUnimplemented();
1182 } // execute
1183 // --- Inst_VOPC__V_CMPX_NLT_F16 class methods ---
1184
1185 Inst_VOPC__V_CMPX_NLT_F16::Inst_VOPC__V_CMPX_NLT_F16(InFmt_VOPC *iFmt)
1186 : Inst_VOPC(iFmt, "v_cmpx_nlt_f16")
1187 {
1188 setFlag(ALU);
1189 setFlag(F16);
1190 setFlag(WritesEXEC);
1191 } // Inst_VOPC__V_CMPX_NLT_F16
1192
1193 Inst_VOPC__V_CMPX_NLT_F16::~Inst_VOPC__V_CMPX_NLT_F16()
1194 {
1195 } // ~Inst_VOPC__V_CMPX_NLT_F16
1196
1197 // --- description from .arch file ---
1198 // EXEC,D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
1199 void
1200 Inst_VOPC__V_CMPX_NLT_F16::execute(GPUDynInstPtr gpuDynInst)
1201 {
1202 panicUnimplemented();
1203 } // execute
1204 // --- Inst_VOPC__V_CMPX_TRU_F16 class methods ---
1205
1206 Inst_VOPC__V_CMPX_TRU_F16::Inst_VOPC__V_CMPX_TRU_F16(InFmt_VOPC *iFmt)
1207 : Inst_VOPC(iFmt, "v_cmpx_tru_f16")
1208 {
1209 setFlag(ALU);
1210 setFlag(F16);
1211 setFlag(WritesEXEC);
1212 } // Inst_VOPC__V_CMPX_TRU_F16
1213
1214 Inst_VOPC__V_CMPX_TRU_F16::~Inst_VOPC__V_CMPX_TRU_F16()
1215 {
1216 } // ~Inst_VOPC__V_CMPX_TRU_F16
1217
1218 // --- description from .arch file ---
1219 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
1220 void
1221 Inst_VOPC__V_CMPX_TRU_F16::execute(GPUDynInstPtr gpuDynInst)
1222 {
1223 panicUnimplemented();
1224 } // execute
1225 // --- Inst_VOPC__V_CMP_F_F32 class methods ---
1226
1227 Inst_VOPC__V_CMP_F_F32::Inst_VOPC__V_CMP_F_F32(InFmt_VOPC *iFmt)
1228 : Inst_VOPC(iFmt, "v_cmp_f_f32")
1229 {
1230 setFlag(ALU);
1231 setFlag(F32);
1232 } // Inst_VOPC__V_CMP_F_F32
1233
1234 Inst_VOPC__V_CMP_F_F32::~Inst_VOPC__V_CMP_F_F32()
1235 {
1236 } // ~Inst_VOPC__V_CMP_F_F32
1237
1238 // --- description from .arch file ---
1239 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
1240 void
1241 Inst_VOPC__V_CMP_F_F32::execute(GPUDynInstPtr gpuDynInst)
1242 {
1243 Wavefront *wf = gpuDynInst->wavefront();
1244 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1245
1246 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1247 if (wf->execMask(lane)) {
1248 vcc.setBit(lane, 0);
1249 }
1250 }
1251
1252 vcc.write();
1253 } // execute
1254 // --- Inst_VOPC__V_CMP_LT_F32 class methods ---
1255
1256 Inst_VOPC__V_CMP_LT_F32::Inst_VOPC__V_CMP_LT_F32(InFmt_VOPC *iFmt)
1257 : Inst_VOPC(iFmt, "v_cmp_lt_f32")
1258 {
1259 setFlag(ALU);
1260 setFlag(F32);
1261 } // Inst_VOPC__V_CMP_LT_F32
1262
1263 Inst_VOPC__V_CMP_LT_F32::~Inst_VOPC__V_CMP_LT_F32()
1264 {
1265 } // ~Inst_VOPC__V_CMP_LT_F32
1266
1267 // --- description from .arch file ---
1268 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
1269 void
1270 Inst_VOPC__V_CMP_LT_F32::execute(GPUDynInstPtr gpuDynInst)
1271 {
1272 Wavefront *wf = gpuDynInst->wavefront();
1273 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1274 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1275 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1276
1277 src0.readSrc();
1278 src1.read();
1279
1280 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1281 if (wf->execMask(lane)) {
1282 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
1283 }
1284 }
1285
1286 vcc.write();
1287 } // execute
1288 // --- Inst_VOPC__V_CMP_EQ_F32 class methods ---
1289
1290 Inst_VOPC__V_CMP_EQ_F32::Inst_VOPC__V_CMP_EQ_F32(InFmt_VOPC *iFmt)
1291 : Inst_VOPC(iFmt, "v_cmp_eq_f32")
1292 {
1293 setFlag(ALU);
1294 setFlag(F32);
1295 } // Inst_VOPC__V_CMP_EQ_F32
1296
1297 Inst_VOPC__V_CMP_EQ_F32::~Inst_VOPC__V_CMP_EQ_F32()
1298 {
1299 } // ~Inst_VOPC__V_CMP_EQ_F32
1300
1301 // --- description from .arch file ---
1302 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
1303 void
1304 Inst_VOPC__V_CMP_EQ_F32::execute(GPUDynInstPtr gpuDynInst)
1305 {
1306 Wavefront *wf = gpuDynInst->wavefront();
1307 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1308 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1309 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1310
1311 src0.readSrc();
1312 src1.read();
1313
1314 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1315 if (wf->execMask(lane)) {
1316 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
1317 }
1318 }
1319
1320 vcc.write();
1321 } // execute
1322 // --- Inst_VOPC__V_CMP_LE_F32 class methods ---
1323
1324 Inst_VOPC__V_CMP_LE_F32::Inst_VOPC__V_CMP_LE_F32(InFmt_VOPC *iFmt)
1325 : Inst_VOPC(iFmt, "v_cmp_le_f32")
1326 {
1327 setFlag(ALU);
1328 setFlag(F32);
1329 } // Inst_VOPC__V_CMP_LE_F32
1330
1331 Inst_VOPC__V_CMP_LE_F32::~Inst_VOPC__V_CMP_LE_F32()
1332 {
1333 } // ~Inst_VOPC__V_CMP_LE_F32
1334
1335 // --- description from .arch file ---
1336 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
1337 void
1338 Inst_VOPC__V_CMP_LE_F32::execute(GPUDynInstPtr gpuDynInst)
1339 {
1340 Wavefront *wf = gpuDynInst->wavefront();
1341 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1342 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1343 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1344
1345 src0.readSrc();
1346 src1.read();
1347
1348 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1349 if (wf->execMask(lane)) {
1350 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
1351 }
1352 }
1353
1354 vcc.write();
1355 } // execute
1356 // --- Inst_VOPC__V_CMP_GT_F32 class methods ---
1357
1358 Inst_VOPC__V_CMP_GT_F32::Inst_VOPC__V_CMP_GT_F32(InFmt_VOPC *iFmt)
1359 : Inst_VOPC(iFmt, "v_cmp_gt_f32")
1360 {
1361 setFlag(ALU);
1362 setFlag(F32);
1363 } // Inst_VOPC__V_CMP_GT_F32
1364
1365 Inst_VOPC__V_CMP_GT_F32::~Inst_VOPC__V_CMP_GT_F32()
1366 {
1367 } // ~Inst_VOPC__V_CMP_GT_F32
1368
1369 // --- description from .arch file ---
1370 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
1371 void
1372 Inst_VOPC__V_CMP_GT_F32::execute(GPUDynInstPtr gpuDynInst)
1373 {
1374 Wavefront *wf = gpuDynInst->wavefront();
1375 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1376 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1377 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1378
1379 src0.readSrc();
1380 src1.read();
1381
1382 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1383 if (wf->execMask(lane)) {
1384 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
1385 }
1386 }
1387
1388 vcc.write();
1389 } // execute
1390 // --- Inst_VOPC__V_CMP_LG_F32 class methods ---
1391
1392 Inst_VOPC__V_CMP_LG_F32::Inst_VOPC__V_CMP_LG_F32(InFmt_VOPC *iFmt)
1393 : Inst_VOPC(iFmt, "v_cmp_lg_f32")
1394 {
1395 setFlag(ALU);
1396 setFlag(F32);
1397 } // Inst_VOPC__V_CMP_LG_F32
1398
1399 Inst_VOPC__V_CMP_LG_F32::~Inst_VOPC__V_CMP_LG_F32()
1400 {
1401 } // ~Inst_VOPC__V_CMP_LG_F32
1402
1403 // --- description from .arch file ---
1404 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
1405 void
1406 Inst_VOPC__V_CMP_LG_F32::execute(GPUDynInstPtr gpuDynInst)
1407 {
1408 Wavefront *wf = gpuDynInst->wavefront();
1409 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1410 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1411 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1412
1413 src0.readSrc();
1414 src1.read();
1415
1416 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1417 if (wf->execMask(lane)) {
1418 vcc.setBit(lane, (src0[lane] < src1[lane]
1419 || src0[lane] > src1[lane]) ? 1 : 0);
1420 }
1421 }
1422
1423 vcc.write();
1424 } // execute
1425 // --- Inst_VOPC__V_CMP_GE_F32 class methods ---
1426
1427 Inst_VOPC__V_CMP_GE_F32::Inst_VOPC__V_CMP_GE_F32(InFmt_VOPC *iFmt)
1428 : Inst_VOPC(iFmt, "v_cmp_ge_f32")
1429 {
1430 setFlag(ALU);
1431 setFlag(F32);
1432 } // Inst_VOPC__V_CMP_GE_F32
1433
1434 Inst_VOPC__V_CMP_GE_F32::~Inst_VOPC__V_CMP_GE_F32()
1435 {
1436 } // ~Inst_VOPC__V_CMP_GE_F32
1437
1438 // --- description from .arch file ---
1439 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
1440 void
1441 Inst_VOPC__V_CMP_GE_F32::execute(GPUDynInstPtr gpuDynInst)
1442 {
1443 Wavefront *wf = gpuDynInst->wavefront();
1444 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1445 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1446 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1447
1448 src0.readSrc();
1449 src1.read();
1450
1451 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1452 if (wf->execMask(lane)) {
1453 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
1454 }
1455 }
1456
1457 vcc.write();
1458 } // execute
1459 // --- Inst_VOPC__V_CMP_O_F32 class methods ---
1460
1461 Inst_VOPC__V_CMP_O_F32::Inst_VOPC__V_CMP_O_F32(InFmt_VOPC *iFmt)
1462 : Inst_VOPC(iFmt, "v_cmp_o_f32")
1463 {
1464 setFlag(ALU);
1465 setFlag(F32);
1466 } // Inst_VOPC__V_CMP_O_F32
1467
1468 Inst_VOPC__V_CMP_O_F32::~Inst_VOPC__V_CMP_O_F32()
1469 {
1470 } // ~Inst_VOPC__V_CMP_O_F32
1471
1472 // --- description from .arch file ---
1473 // D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC encoding.
1474 void
1475 Inst_VOPC__V_CMP_O_F32::execute(GPUDynInstPtr gpuDynInst)
1476 {
1477 Wavefront *wf = gpuDynInst->wavefront();
1478 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1479 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1480 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1481
1482 src0.readSrc();
1483 src1.read();
1484
1485 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1486 if (wf->execMask(lane)) {
1487 vcc.setBit(lane, (!std::isnan(src0[lane])
1488 && !std::isnan(src1[lane])) ? 1 : 0);
1489 }
1490 }
1491
1492 vcc.write();
1493 } // execute
1494 // --- Inst_VOPC__V_CMP_U_F32 class methods ---
1495
1496 Inst_VOPC__V_CMP_U_F32::Inst_VOPC__V_CMP_U_F32(InFmt_VOPC *iFmt)
1497 : Inst_VOPC(iFmt, "v_cmp_u_f32")
1498 {
1499 setFlag(ALU);
1500 setFlag(F32);
1501 } // Inst_VOPC__V_CMP_U_F32
1502
1503 Inst_VOPC__V_CMP_U_F32::~Inst_VOPC__V_CMP_U_F32()
1504 {
1505 } // ~Inst_VOPC__V_CMP_U_F32
1506
1507 // --- description from .arch file ---
1508 // D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC encoding.
1509 void
1510 Inst_VOPC__V_CMP_U_F32::execute(GPUDynInstPtr gpuDynInst)
1511 {
1512 Wavefront *wf = gpuDynInst->wavefront();
1513 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1514 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1515 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1516
1517 src0.readSrc();
1518 src1.read();
1519
1520 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1521 if (wf->execMask(lane)) {
1522 vcc.setBit(lane, (std::isnan(src0[lane])
1523 || std::isnan(src1[lane])) ? 1 : 0);
1524 }
1525 }
1526
1527 vcc.write();
1528 } // execute
1529 // --- Inst_VOPC__V_CMP_NGE_F32 class methods ---
1530
1531 Inst_VOPC__V_CMP_NGE_F32::Inst_VOPC__V_CMP_NGE_F32(InFmt_VOPC *iFmt)
1532 : Inst_VOPC(iFmt, "v_cmp_nge_f32")
1533 {
1534 setFlag(ALU);
1535 setFlag(F32);
1536 } // Inst_VOPC__V_CMP_NGE_F32
1537
1538 Inst_VOPC__V_CMP_NGE_F32::~Inst_VOPC__V_CMP_NGE_F32()
1539 {
1540 } // ~Inst_VOPC__V_CMP_NGE_F32
1541
1542 // --- description from .arch file ---
1543 // D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
1544 void
1545 Inst_VOPC__V_CMP_NGE_F32::execute(GPUDynInstPtr gpuDynInst)
1546 {
1547 Wavefront *wf = gpuDynInst->wavefront();
1548 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1549 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1550 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1551
1552 src0.readSrc();
1553 src1.read();
1554
1555 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1556 if (wf->execMask(lane)) {
1557 vcc.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
1558 }
1559 }
1560
1561 vcc.write();
1562 } // execute
1563 // --- Inst_VOPC__V_CMP_NLG_F32 class methods ---
1564
1565 Inst_VOPC__V_CMP_NLG_F32::Inst_VOPC__V_CMP_NLG_F32(InFmt_VOPC *iFmt)
1566 : Inst_VOPC(iFmt, "v_cmp_nlg_f32")
1567 {
1568 setFlag(ALU);
1569 setFlag(F32);
1570 } // Inst_VOPC__V_CMP_NLG_F32
1571
1572 Inst_VOPC__V_CMP_NLG_F32::~Inst_VOPC__V_CMP_NLG_F32()
1573 {
1574 } // ~Inst_VOPC__V_CMP_NLG_F32
1575
1576 // --- description from .arch file ---
1577 // D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
1578 void
1579 Inst_VOPC__V_CMP_NLG_F32::execute(GPUDynInstPtr gpuDynInst)
1580 {
1581 Wavefront *wf = gpuDynInst->wavefront();
1582 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1583 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1584 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1585
1586 src0.readSrc();
1587 src1.read();
1588
1589 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1590 if (wf->execMask(lane)) {
1591 vcc.setBit(lane, !(src0[lane] < src1[lane]
1592 || src0[lane] > src1[lane]) ? 1 : 0);
1593 }
1594 }
1595
1596 vcc.write();
1597 } // execute
1598 // --- Inst_VOPC__V_CMP_NGT_F32 class methods ---
1599
1600 Inst_VOPC__V_CMP_NGT_F32::Inst_VOPC__V_CMP_NGT_F32(InFmt_VOPC *iFmt)
1601 : Inst_VOPC(iFmt, "v_cmp_ngt_f32")
1602 {
1603 setFlag(ALU);
1604 setFlag(F32);
1605 } // Inst_VOPC__V_CMP_NGT_F32
1606
1607 Inst_VOPC__V_CMP_NGT_F32::~Inst_VOPC__V_CMP_NGT_F32()
1608 {
1609 } // ~Inst_VOPC__V_CMP_NGT_F32
1610
1611 // --- description from .arch file ---
1612 // D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
1613 void
1614 Inst_VOPC__V_CMP_NGT_F32::execute(GPUDynInstPtr gpuDynInst)
1615 {
1616 Wavefront *wf = gpuDynInst->wavefront();
1617 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1618 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1619 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1620
1621 src0.readSrc();
1622 src1.read();
1623
1624 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1625 if (wf->execMask(lane)) {
1626 vcc.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
1627 }
1628 }
1629
1630 vcc.write();
1631 } // execute
1632 // --- Inst_VOPC__V_CMP_NLE_F32 class methods ---
1633
1634 Inst_VOPC__V_CMP_NLE_F32::Inst_VOPC__V_CMP_NLE_F32(InFmt_VOPC *iFmt)
1635 : Inst_VOPC(iFmt, "v_cmp_nle_f32")
1636 {
1637 setFlag(ALU);
1638 setFlag(F32);
1639 } // Inst_VOPC__V_CMP_NLE_F32
1640
1641 Inst_VOPC__V_CMP_NLE_F32::~Inst_VOPC__V_CMP_NLE_F32()
1642 {
1643 } // ~Inst_VOPC__V_CMP_NLE_F32
1644
1645 // --- description from .arch file ---
1646 // D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
1647 void
1648 Inst_VOPC__V_CMP_NLE_F32::execute(GPUDynInstPtr gpuDynInst)
1649 {
1650 Wavefront *wf = gpuDynInst->wavefront();
1651 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1652 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1653 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1654
1655 src0.readSrc();
1656 src1.read();
1657
1658 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1659 if (wf->execMask(lane)) {
1660 vcc.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
1661 }
1662 }
1663
1664 vcc.write();
1665 } // execute
1666 // --- Inst_VOPC__V_CMP_NEQ_F32 class methods ---
1667
1668 Inst_VOPC__V_CMP_NEQ_F32::Inst_VOPC__V_CMP_NEQ_F32(InFmt_VOPC *iFmt)
1669 : Inst_VOPC(iFmt, "v_cmp_neq_f32")
1670 {
1671 setFlag(ALU);
1672 setFlag(F32);
1673 } // Inst_VOPC__V_CMP_NEQ_F32
1674
1675 Inst_VOPC__V_CMP_NEQ_F32::~Inst_VOPC__V_CMP_NEQ_F32()
1676 {
1677 } // ~Inst_VOPC__V_CMP_NEQ_F32
1678
1679 // --- description from .arch file ---
1680 // D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
1681 void
1682 Inst_VOPC__V_CMP_NEQ_F32::execute(GPUDynInstPtr gpuDynInst)
1683 {
1684 Wavefront *wf = gpuDynInst->wavefront();
1685 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1686 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1687 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1688
1689 src0.readSrc();
1690 src1.read();
1691
1692 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1693 if (wf->execMask(lane)) {
1694 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
1695 }
1696 }
1697
1698 vcc.write();
1699 } // execute
1700 // --- Inst_VOPC__V_CMP_NLT_F32 class methods ---
1701
1702 Inst_VOPC__V_CMP_NLT_F32::Inst_VOPC__V_CMP_NLT_F32(InFmt_VOPC *iFmt)
1703 : Inst_VOPC(iFmt, "v_cmp_nlt_f32")
1704 {
1705 setFlag(ALU);
1706 setFlag(F32);
1707 } // Inst_VOPC__V_CMP_NLT_F32
1708
1709 Inst_VOPC__V_CMP_NLT_F32::~Inst_VOPC__V_CMP_NLT_F32()
1710 {
1711 } // ~Inst_VOPC__V_CMP_NLT_F32
1712
1713 // --- description from .arch file ---
1714 // D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
1715 void
1716 Inst_VOPC__V_CMP_NLT_F32::execute(GPUDynInstPtr gpuDynInst)
1717 {
1718 Wavefront *wf = gpuDynInst->wavefront();
1719 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1720 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1721 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1722
1723 src0.readSrc();
1724 src1.read();
1725
1726 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1727 if (wf->execMask(lane)) {
1728 vcc.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
1729 }
1730 }
1731
1732 vcc.write();
1733 } // execute
1734 // --- Inst_VOPC__V_CMP_TRU_F32 class methods ---
1735
1736 Inst_VOPC__V_CMP_TRU_F32::Inst_VOPC__V_CMP_TRU_F32(InFmt_VOPC *iFmt)
1737 : Inst_VOPC(iFmt, "v_cmp_tru_f32")
1738 {
1739 setFlag(ALU);
1740 setFlag(F32);
1741 } // Inst_VOPC__V_CMP_TRU_F32
1742
1743 Inst_VOPC__V_CMP_TRU_F32::~Inst_VOPC__V_CMP_TRU_F32()
1744 {
1745 } // ~Inst_VOPC__V_CMP_TRU_F32
1746
1747 // --- description from .arch file ---
1748 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
1749 void
1750 Inst_VOPC__V_CMP_TRU_F32::execute(GPUDynInstPtr gpuDynInst)
1751 {
1752 Wavefront *wf = gpuDynInst->wavefront();
1753 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1754
1755 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1756 if (wf->execMask(lane)) {
1757 vcc.setBit(lane, 1);
1758 }
1759 }
1760
1761 vcc.write();
1762 } // execute
1763 // --- Inst_VOPC__V_CMPX_F_F32 class methods ---
1764
1765 Inst_VOPC__V_CMPX_F_F32::Inst_VOPC__V_CMPX_F_F32(InFmt_VOPC *iFmt)
1766 : Inst_VOPC(iFmt, "v_cmpx_f_f32")
1767 {
1768 setFlag(ALU);
1769 setFlag(F32);
1770 setFlag(WritesEXEC);
1771 } // Inst_VOPC__V_CMPX_F_F32
1772
1773 Inst_VOPC__V_CMPX_F_F32::~Inst_VOPC__V_CMPX_F_F32()
1774 {
1775 } // ~Inst_VOPC__V_CMPX_F_F32
1776
1777 // --- description from .arch file ---
1778 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
1779 void
1780 Inst_VOPC__V_CMPX_F_F32::execute(GPUDynInstPtr gpuDynInst)
1781 {
1782 Wavefront *wf = gpuDynInst->wavefront();
1783 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1784
1785 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1786 if (wf->execMask(lane)) {
1787 vcc.setBit(lane, 0);
1788 }
1789 }
1790
1791 vcc.write();
1792 wf->execMask() = vcc.rawData();
1793 } // execute
1794 // --- Inst_VOPC__V_CMPX_LT_F32 class methods ---
1795
1796 Inst_VOPC__V_CMPX_LT_F32::Inst_VOPC__V_CMPX_LT_F32(InFmt_VOPC *iFmt)
1797 : Inst_VOPC(iFmt, "v_cmpx_lt_f32")
1798 {
1799 setFlag(ALU);
1800 setFlag(F32);
1801 setFlag(WritesEXEC);
1802 } // Inst_VOPC__V_CMPX_LT_F32
1803
1804 Inst_VOPC__V_CMPX_LT_F32::~Inst_VOPC__V_CMPX_LT_F32()
1805 {
1806 } // ~Inst_VOPC__V_CMPX_LT_F32
1807
1808 // --- description from .arch file ---
1809 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
1810 void
1811 Inst_VOPC__V_CMPX_LT_F32::execute(GPUDynInstPtr gpuDynInst)
1812 {
1813 Wavefront *wf = gpuDynInst->wavefront();
1814 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1815 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1816 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1817
1818 src0.readSrc();
1819 src1.read();
1820
1821 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1822 if (wf->execMask(lane)) {
1823 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
1824 }
1825 }
1826
1827 vcc.write();
1828 wf->execMask() = vcc.rawData();
1829 } // execute
1830 // --- Inst_VOPC__V_CMPX_EQ_F32 class methods ---
1831
1832 Inst_VOPC__V_CMPX_EQ_F32::Inst_VOPC__V_CMPX_EQ_F32(InFmt_VOPC *iFmt)
1833 : Inst_VOPC(iFmt, "v_cmpx_eq_f32")
1834 {
1835 setFlag(ALU);
1836 setFlag(F32);
1837 setFlag(WritesEXEC);
1838 } // Inst_VOPC__V_CMPX_EQ_F32
1839
1840 Inst_VOPC__V_CMPX_EQ_F32::~Inst_VOPC__V_CMPX_EQ_F32()
1841 {
1842 } // ~Inst_VOPC__V_CMPX_EQ_F32
1843
1844 // --- description from .arch file ---
1845 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
1846 void
1847 Inst_VOPC__V_CMPX_EQ_F32::execute(GPUDynInstPtr gpuDynInst)
1848 {
1849 Wavefront *wf = gpuDynInst->wavefront();
1850 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1851 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1852 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1853
1854 src0.readSrc();
1855 src1.read();
1856
1857 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1858 if (wf->execMask(lane)) {
1859 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
1860 }
1861 }
1862
1863 vcc.write();
1864 wf->execMask() = vcc.rawData();
1865 } // execute
1866 // --- Inst_VOPC__V_CMPX_LE_F32 class methods ---
1867
1868 Inst_VOPC__V_CMPX_LE_F32::Inst_VOPC__V_CMPX_LE_F32(InFmt_VOPC *iFmt)
1869 : Inst_VOPC(iFmt, "v_cmpx_le_f32")
1870 {
1871 setFlag(ALU);
1872 setFlag(F32);
1873 setFlag(WritesEXEC);
1874 } // Inst_VOPC__V_CMPX_LE_F32
1875
1876 Inst_VOPC__V_CMPX_LE_F32::~Inst_VOPC__V_CMPX_LE_F32()
1877 {
1878 } // ~Inst_VOPC__V_CMPX_LE_F32
1879
1880 // --- description from .arch file ---
1881 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
1882 void
1883 Inst_VOPC__V_CMPX_LE_F32::execute(GPUDynInstPtr gpuDynInst)
1884 {
1885 Wavefront *wf = gpuDynInst->wavefront();
1886 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1887 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1888 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1889
1890 src0.readSrc();
1891 src1.read();
1892
1893 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1894 if (wf->execMask(lane)) {
1895 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
1896 }
1897 }
1898
1899 vcc.write();
1900 wf->execMask() = vcc.rawData();
1901 } // execute
1902 // --- Inst_VOPC__V_CMPX_GT_F32 class methods ---
1903
1904 Inst_VOPC__V_CMPX_GT_F32::Inst_VOPC__V_CMPX_GT_F32(InFmt_VOPC *iFmt)
1905 : Inst_VOPC(iFmt, "v_cmpx_gt_f32")
1906 {
1907 setFlag(ALU);
1908 setFlag(F32);
1909 setFlag(WritesEXEC);
1910 } // Inst_VOPC__V_CMPX_GT_F32
1911
1912 Inst_VOPC__V_CMPX_GT_F32::~Inst_VOPC__V_CMPX_GT_F32()
1913 {
1914 } // ~Inst_VOPC__V_CMPX_GT_F32
1915
1916 // --- description from .arch file ---
1917 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
1918 void
1919 Inst_VOPC__V_CMPX_GT_F32::execute(GPUDynInstPtr gpuDynInst)
1920 {
1921 Wavefront *wf = gpuDynInst->wavefront();
1922 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1923 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1924 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1925
1926 src0.readSrc();
1927 src1.read();
1928
1929 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1930 if (wf->execMask(lane)) {
1931 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
1932 }
1933 }
1934
1935 vcc.write();
1936 wf->execMask() = vcc.rawData();
1937 } // execute
1938 // --- Inst_VOPC__V_CMPX_LG_F32 class methods ---
1939
1940 Inst_VOPC__V_CMPX_LG_F32::Inst_VOPC__V_CMPX_LG_F32(InFmt_VOPC *iFmt)
1941 : Inst_VOPC(iFmt, "v_cmpx_lg_f32")
1942 {
1943 setFlag(ALU);
1944 setFlag(F32);
1945 setFlag(WritesEXEC);
1946 } // Inst_VOPC__V_CMPX_LG_F32
1947
1948 Inst_VOPC__V_CMPX_LG_F32::~Inst_VOPC__V_CMPX_LG_F32()
1949 {
1950 } // ~Inst_VOPC__V_CMPX_LG_F32
1951
1952 // --- description from .arch file ---
1953 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
1954 void
1955 Inst_VOPC__V_CMPX_LG_F32::execute(GPUDynInstPtr gpuDynInst)
1956 {
1957 Wavefront *wf = gpuDynInst->wavefront();
1958 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1959 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1960 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1961
1962 src0.readSrc();
1963 src1.read();
1964
1965 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1966 if (wf->execMask(lane)) {
1967 vcc.setBit(lane, (src0[lane] < src1[lane]
1968 || src0[lane] > src1[lane]) ? 1 : 0);
1969 }
1970 }
1971
1972 vcc.write();
1973 wf->execMask() = vcc.rawData();
1974 } // execute
1975 // --- Inst_VOPC__V_CMPX_GE_F32 class methods ---
1976
1977 Inst_VOPC__V_CMPX_GE_F32::Inst_VOPC__V_CMPX_GE_F32(InFmt_VOPC *iFmt)
1978 : Inst_VOPC(iFmt, "v_cmpx_ge_f32")
1979 {
1980 setFlag(ALU);
1981 setFlag(F32);
1982 setFlag(WritesEXEC);
1983 } // Inst_VOPC__V_CMPX_GE_F32
1984
1985 Inst_VOPC__V_CMPX_GE_F32::~Inst_VOPC__V_CMPX_GE_F32()
1986 {
1987 } // ~Inst_VOPC__V_CMPX_GE_F32
1988
1989 // --- description from .arch file ---
1990 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
1991 void
1992 Inst_VOPC__V_CMPX_GE_F32::execute(GPUDynInstPtr gpuDynInst)
1993 {
1994 Wavefront *wf = gpuDynInst->wavefront();
1995 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1996 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1997 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1998
1999 src0.readSrc();
2000 src1.read();
2001
2002 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2003 if (wf->execMask(lane)) {
2004 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
2005 }
2006 }
2007
2008 vcc.write();
2009 wf->execMask() = vcc.rawData();
2010 } // execute
2011 // --- Inst_VOPC__V_CMPX_O_F32 class methods ---
2012
2013 Inst_VOPC__V_CMPX_O_F32::Inst_VOPC__V_CMPX_O_F32(InFmt_VOPC *iFmt)
2014 : Inst_VOPC(iFmt, "v_cmpx_o_f32")
2015 {
2016 setFlag(ALU);
2017 setFlag(F32);
2018 setFlag(WritesEXEC);
2019 } // Inst_VOPC__V_CMPX_O_F32
2020
2021 Inst_VOPC__V_CMPX_O_F32::~Inst_VOPC__V_CMPX_O_F32()
2022 {
2023 } // ~Inst_VOPC__V_CMPX_O_F32
2024
2025 // --- description from .arch file ---
2026 // EXEC,D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC
2027 // encoding.
2028 void
2029 Inst_VOPC__V_CMPX_O_F32::execute(GPUDynInstPtr gpuDynInst)
2030 {
2031 Wavefront *wf = gpuDynInst->wavefront();
2032 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2033 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2034 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2035
2036 src0.readSrc();
2037 src1.read();
2038
2039 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2040 if (wf->execMask(lane)) {
2041 vcc.setBit(lane, (!std::isnan(src0[lane])
2042 && !std::isnan(src1[lane])) ? 1 : 0);
2043 }
2044 }
2045
2046 vcc.write();
2047 wf->execMask() = vcc.rawData();
2048 } // execute
2049 // --- Inst_VOPC__V_CMPX_U_F32 class methods ---
2050
2051 Inst_VOPC__V_CMPX_U_F32::Inst_VOPC__V_CMPX_U_F32(InFmt_VOPC *iFmt)
2052 : Inst_VOPC(iFmt, "v_cmpx_u_f32")
2053 {
2054 setFlag(ALU);
2055 setFlag(F32);
2056 setFlag(WritesEXEC);
2057 } // Inst_VOPC__V_CMPX_U_F32
2058
2059 Inst_VOPC__V_CMPX_U_F32::~Inst_VOPC__V_CMPX_U_F32()
2060 {
2061 } // ~Inst_VOPC__V_CMPX_U_F32
2062
2063 // --- description from .arch file ---
2064 // EXEC,D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC
2065 // encoding.
2066 void
2067 Inst_VOPC__V_CMPX_U_F32::execute(GPUDynInstPtr gpuDynInst)
2068 {
2069 Wavefront *wf = gpuDynInst->wavefront();
2070 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2071 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2072 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2073
2074 src0.readSrc();
2075 src1.read();
2076
2077 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2078 if (wf->execMask(lane)) {
2079 vcc.setBit(lane, (std::isnan(src0[lane])
2080 || std::isnan(src1[lane])) ? 1 : 0);
2081 }
2082 }
2083
2084 vcc.write();
2085 wf->execMask() = vcc.rawData();
2086 } // execute
2087 // --- Inst_VOPC__V_CMPX_NGE_F32 class methods ---
2088
2089 Inst_VOPC__V_CMPX_NGE_F32::Inst_VOPC__V_CMPX_NGE_F32(InFmt_VOPC *iFmt)
2090 : Inst_VOPC(iFmt, "v_cmpx_nge_f32")
2091 {
2092 setFlag(ALU);
2093 setFlag(F32);
2094 setFlag(WritesEXEC);
2095 } // Inst_VOPC__V_CMPX_NGE_F32
2096
2097 Inst_VOPC__V_CMPX_NGE_F32::~Inst_VOPC__V_CMPX_NGE_F32()
2098 {
2099 } // ~Inst_VOPC__V_CMPX_NGE_F32
2100
2101 // --- description from .arch file ---
2102 // EXEC,D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
2103 void
2104 Inst_VOPC__V_CMPX_NGE_F32::execute(GPUDynInstPtr gpuDynInst)
2105 {
2106 Wavefront *wf = gpuDynInst->wavefront();
2107 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2108 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2109 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2110
2111 src0.readSrc();
2112 src1.read();
2113
2114 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2115 if (wf->execMask(lane)) {
2116 vcc.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
2117 }
2118 }
2119
2120 vcc.write();
2121 wf->execMask() = vcc.rawData();
2122 } // execute
2123 // --- Inst_VOPC__V_CMPX_NLG_F32 class methods ---
2124
2125 Inst_VOPC__V_CMPX_NLG_F32::Inst_VOPC__V_CMPX_NLG_F32(InFmt_VOPC *iFmt)
2126 : Inst_VOPC(iFmt, "v_cmpx_nlg_f32")
2127 {
2128 setFlag(ALU);
2129 setFlag(F32);
2130 setFlag(WritesEXEC);
2131 } // Inst_VOPC__V_CMPX_NLG_F32
2132
2133 Inst_VOPC__V_CMPX_NLG_F32::~Inst_VOPC__V_CMPX_NLG_F32()
2134 {
2135 } // ~Inst_VOPC__V_CMPX_NLG_F32
2136
2137 // --- description from .arch file ---
2138 // EXEC,D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
2139 void
2140 Inst_VOPC__V_CMPX_NLG_F32::execute(GPUDynInstPtr gpuDynInst)
2141 {
2142 Wavefront *wf = gpuDynInst->wavefront();
2143 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2144 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2145 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2146
2147 src0.readSrc();
2148 src1.read();
2149
2150 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2151 if (wf->execMask(lane)) {
2152 vcc.setBit(lane, !(src0[lane] < src1[lane]
2153 || src0[lane] > src1[lane]) ? 1 : 0);
2154 }
2155 }
2156
2157 vcc.write();
2158 wf->execMask() = vcc.rawData();
2159 } // execute
2160 // --- Inst_VOPC__V_CMPX_NGT_F32 class methods ---
2161
2162 Inst_VOPC__V_CMPX_NGT_F32::Inst_VOPC__V_CMPX_NGT_F32(InFmt_VOPC *iFmt)
2163 : Inst_VOPC(iFmt, "v_cmpx_ngt_f32")
2164 {
2165 setFlag(ALU);
2166 setFlag(F32);
2167 setFlag(WritesEXEC);
2168 } // Inst_VOPC__V_CMPX_NGT_F32
2169
2170 Inst_VOPC__V_CMPX_NGT_F32::~Inst_VOPC__V_CMPX_NGT_F32()
2171 {
2172 } // ~Inst_VOPC__V_CMPX_NGT_F32
2173
2174 // --- description from .arch file ---
2175 // EXEC,D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
2176 void
2177 Inst_VOPC__V_CMPX_NGT_F32::execute(GPUDynInstPtr gpuDynInst)
2178 {
2179 Wavefront *wf = gpuDynInst->wavefront();
2180 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2181 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2182 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2183
2184 src0.readSrc();
2185 src1.read();
2186
2187 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2188 if (wf->execMask(lane)) {
2189 vcc.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
2190 }
2191 }
2192
2193 vcc.write();
2194 wf->execMask() = vcc.rawData();
2195 } // execute
2196 // --- Inst_VOPC__V_CMPX_NLE_F32 class methods ---
2197
2198 Inst_VOPC__V_CMPX_NLE_F32::Inst_VOPC__V_CMPX_NLE_F32(InFmt_VOPC *iFmt)
2199 : Inst_VOPC(iFmt, "v_cmpx_nle_f32")
2200 {
2201 setFlag(ALU);
2202 setFlag(F32);
2203 setFlag(WritesEXEC);
2204 } // Inst_VOPC__V_CMPX_NLE_F32
2205
2206 Inst_VOPC__V_CMPX_NLE_F32::~Inst_VOPC__V_CMPX_NLE_F32()
2207 {
2208 } // ~Inst_VOPC__V_CMPX_NLE_F32
2209
2210 // --- description from .arch file ---
2211 // EXEC,D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
2212 void
2213 Inst_VOPC__V_CMPX_NLE_F32::execute(GPUDynInstPtr gpuDynInst)
2214 {
2215 Wavefront *wf = gpuDynInst->wavefront();
2216 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2217 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2218 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2219
2220 src0.readSrc();
2221 src1.read();
2222
2223 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2224 if (wf->execMask(lane)) {
2225 vcc.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
2226 }
2227 }
2228
2229 vcc.write();
2230 wf->execMask() = vcc.rawData();
2231 } // execute
2232 // --- Inst_VOPC__V_CMPX_NEQ_F32 class methods ---
2233
2234 Inst_VOPC__V_CMPX_NEQ_F32::Inst_VOPC__V_CMPX_NEQ_F32(InFmt_VOPC *iFmt)
2235 : Inst_VOPC(iFmt, "v_cmpx_neq_f32")
2236 {
2237 setFlag(ALU);
2238 setFlag(F32);
2239 setFlag(WritesEXEC);
2240 } // Inst_VOPC__V_CMPX_NEQ_F32
2241
2242 Inst_VOPC__V_CMPX_NEQ_F32::~Inst_VOPC__V_CMPX_NEQ_F32()
2243 {
2244 } // ~Inst_VOPC__V_CMPX_NEQ_F32
2245
2246 // --- description from .arch file ---
2247 // EXEC,D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
2248 void
2249 Inst_VOPC__V_CMPX_NEQ_F32::execute(GPUDynInstPtr gpuDynInst)
2250 {
2251 Wavefront *wf = gpuDynInst->wavefront();
2252 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2253 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2254 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2255
2256 src0.readSrc();
2257 src1.read();
2258
2259 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2260 if (wf->execMask(lane)) {
2261 vcc.setBit(lane, !(src0[lane] == src1[lane]) ? 1 : 0);
2262 }
2263 }
2264
2265 vcc.write();
2266 wf->execMask() = vcc.rawData();
2267 } // execute
2268 // --- Inst_VOPC__V_CMPX_NLT_F32 class methods ---
2269
2270 Inst_VOPC__V_CMPX_NLT_F32::Inst_VOPC__V_CMPX_NLT_F32(InFmt_VOPC *iFmt)
2271 : Inst_VOPC(iFmt, "v_cmpx_nlt_f32")
2272 {
2273 setFlag(ALU);
2274 setFlag(F32);
2275 setFlag(WritesEXEC);
2276 } // Inst_VOPC__V_CMPX_NLT_F32
2277
2278 Inst_VOPC__V_CMPX_NLT_F32::~Inst_VOPC__V_CMPX_NLT_F32()
2279 {
2280 } // ~Inst_VOPC__V_CMPX_NLT_F32
2281
2282 // --- description from .arch file ---
2283 // EXEC,D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
2284 void
2285 Inst_VOPC__V_CMPX_NLT_F32::execute(GPUDynInstPtr gpuDynInst)
2286 {
2287 Wavefront *wf = gpuDynInst->wavefront();
2288 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2289 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2290 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2291
2292 src0.readSrc();
2293 src1.read();
2294
2295 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2296 if (wf->execMask(lane)) {
2297 vcc.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
2298 }
2299 }
2300
2301 vcc.write();
2302 wf->execMask() = vcc.rawData();
2303 } // execute
2304 // --- Inst_VOPC__V_CMPX_TRU_F32 class methods ---
2305
2306 Inst_VOPC__V_CMPX_TRU_F32::Inst_VOPC__V_CMPX_TRU_F32(InFmt_VOPC *iFmt)
2307 : Inst_VOPC(iFmt, "v_cmpx_tru_f32")
2308 {
2309 setFlag(ALU);
2310 setFlag(F32);
2311 setFlag(WritesEXEC);
2312 } // Inst_VOPC__V_CMPX_TRU_F32
2313
2314 Inst_VOPC__V_CMPX_TRU_F32::~Inst_VOPC__V_CMPX_TRU_F32()
2315 {
2316 } // ~Inst_VOPC__V_CMPX_TRU_F32
2317
2318 // --- description from .arch file ---
2319 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
2320 void
2321 Inst_VOPC__V_CMPX_TRU_F32::execute(GPUDynInstPtr gpuDynInst)
2322 {
2323 Wavefront *wf = gpuDynInst->wavefront();
2324 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2325
2326 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2327 if (wf->execMask(lane)) {
2328 vcc.setBit(lane, 1);
2329 }
2330 }
2331
2332 vcc.write();
2333 wf->execMask() = vcc.rawData();
2334 } // execute
2335 // --- Inst_VOPC__V_CMP_F_F64 class methods ---
2336
2337 Inst_VOPC__V_CMP_F_F64::Inst_VOPC__V_CMP_F_F64(InFmt_VOPC *iFmt)
2338 : Inst_VOPC(iFmt, "v_cmp_f_f64")
2339 {
2340 setFlag(ALU);
2341 setFlag(F64);
2342 } // Inst_VOPC__V_CMP_F_F64
2343
2344 Inst_VOPC__V_CMP_F_F64::~Inst_VOPC__V_CMP_F_F64()
2345 {
2346 } // ~Inst_VOPC__V_CMP_F_F64
2347
2348 // --- description from .arch file ---
2349 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
2350 void
2351 Inst_VOPC__V_CMP_F_F64::execute(GPUDynInstPtr gpuDynInst)
2352 {
2353 Wavefront *wf = gpuDynInst->wavefront();
2354 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2355
2356 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2357 if (wf->execMask(lane)) {
2358 vcc.setBit(lane, 0);
2359 }
2360 }
2361
2362 vcc.write();
2363 } // execute
2364 // --- Inst_VOPC__V_CMP_LT_F64 class methods ---
2365
2366 Inst_VOPC__V_CMP_LT_F64::Inst_VOPC__V_CMP_LT_F64(InFmt_VOPC *iFmt)
2367 : Inst_VOPC(iFmt, "v_cmp_lt_f64")
2368 {
2369 setFlag(ALU);
2370 setFlag(F64);
2371 } // Inst_VOPC__V_CMP_LT_F64
2372
2373 Inst_VOPC__V_CMP_LT_F64::~Inst_VOPC__V_CMP_LT_F64()
2374 {
2375 } // ~Inst_VOPC__V_CMP_LT_F64
2376
2377 // --- description from .arch file ---
2378 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
2379 void
2380 Inst_VOPC__V_CMP_LT_F64::execute(GPUDynInstPtr gpuDynInst)
2381 {
2382 Wavefront *wf = gpuDynInst->wavefront();
2383 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2384 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2385 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2386
2387 src0.readSrc();
2388 src1.read();
2389
2390 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2391 if (wf->execMask(lane)) {
2392 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
2393 }
2394 }
2395
2396 vcc.write();
2397 } // execute
2398 // --- Inst_VOPC__V_CMP_EQ_F64 class methods ---
2399
2400 Inst_VOPC__V_CMP_EQ_F64::Inst_VOPC__V_CMP_EQ_F64(InFmt_VOPC *iFmt)
2401 : Inst_VOPC(iFmt, "v_cmp_eq_f64")
2402 {
2403 setFlag(ALU);
2404 setFlag(F64);
2405 } // Inst_VOPC__V_CMP_EQ_F64
2406
2407 Inst_VOPC__V_CMP_EQ_F64::~Inst_VOPC__V_CMP_EQ_F64()
2408 {
2409 } // ~Inst_VOPC__V_CMP_EQ_F64
2410
2411 // --- description from .arch file ---
2412 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
2413 void
2414 Inst_VOPC__V_CMP_EQ_F64::execute(GPUDynInstPtr gpuDynInst)
2415 {
2416 Wavefront *wf = gpuDynInst->wavefront();
2417 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2418 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2419 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2420
2421 src0.readSrc();
2422 src1.read();
2423
2424 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2425 if (wf->execMask(lane)) {
2426 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
2427 }
2428 }
2429
2430 vcc.write();
2431 } // execute
2432 // --- Inst_VOPC__V_CMP_LE_F64 class methods ---
2433
2434 Inst_VOPC__V_CMP_LE_F64::Inst_VOPC__V_CMP_LE_F64(InFmt_VOPC *iFmt)
2435 : Inst_VOPC(iFmt, "v_cmp_le_f64")
2436 {
2437 setFlag(ALU);
2438 setFlag(F64);
2439 } // Inst_VOPC__V_CMP_LE_F64
2440
2441 Inst_VOPC__V_CMP_LE_F64::~Inst_VOPC__V_CMP_LE_F64()
2442 {
2443 } // ~Inst_VOPC__V_CMP_LE_F64
2444
2445 // --- description from .arch file ---
2446 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
2447 void
2448 Inst_VOPC__V_CMP_LE_F64::execute(GPUDynInstPtr gpuDynInst)
2449 {
2450 Wavefront *wf = gpuDynInst->wavefront();
2451 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2452 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2453 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2454
2455 src0.readSrc();
2456 src1.read();
2457
2458 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2459 if (wf->execMask(lane)) {
2460 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
2461 }
2462 }
2463
2464 vcc.write();
2465 } // execute
2466 // --- Inst_VOPC__V_CMP_GT_F64 class methods ---
2467
2468 Inst_VOPC__V_CMP_GT_F64::Inst_VOPC__V_CMP_GT_F64(InFmt_VOPC *iFmt)
2469 : Inst_VOPC(iFmt, "v_cmp_gt_f64")
2470 {
2471 setFlag(ALU);
2472 setFlag(F64);
2473 } // Inst_VOPC__V_CMP_GT_F64
2474
2475 Inst_VOPC__V_CMP_GT_F64::~Inst_VOPC__V_CMP_GT_F64()
2476 {
2477 } // ~Inst_VOPC__V_CMP_GT_F64
2478
2479 // --- description from .arch file ---
2480 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
2481 void
2482 Inst_VOPC__V_CMP_GT_F64::execute(GPUDynInstPtr gpuDynInst)
2483 {
2484 Wavefront *wf = gpuDynInst->wavefront();
2485 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2486 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2487 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2488
2489 src0.readSrc();
2490 src1.read();
2491
2492 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2493 if (wf->execMask(lane)) {
2494 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
2495 }
2496 }
2497
2498 vcc.write();
2499 } // execute
2500 // --- Inst_VOPC__V_CMP_LG_F64 class methods ---
2501
2502 Inst_VOPC__V_CMP_LG_F64::Inst_VOPC__V_CMP_LG_F64(InFmt_VOPC *iFmt)
2503 : Inst_VOPC(iFmt, "v_cmp_lg_f64")
2504 {
2505 setFlag(ALU);
2506 setFlag(F64);
2507 } // Inst_VOPC__V_CMP_LG_F64
2508
2509 Inst_VOPC__V_CMP_LG_F64::~Inst_VOPC__V_CMP_LG_F64()
2510 {
2511 } // ~Inst_VOPC__V_CMP_LG_F64
2512
2513 // --- description from .arch file ---
2514 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
2515 void
2516 Inst_VOPC__V_CMP_LG_F64::execute(GPUDynInstPtr gpuDynInst)
2517 {
2518 Wavefront *wf = gpuDynInst->wavefront();
2519 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2520 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2521 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2522
2523 src0.readSrc();
2524 src1.read();
2525
2526 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2527 if (wf->execMask(lane)) {
2528 vcc.setBit(lane, (src0[lane] < src1[lane]
2529 || src0[lane] > src1[lane]) ? 1 : 0);
2530 }
2531 }
2532
2533 vcc.write();
2534 } // execute
2535 // --- Inst_VOPC__V_CMP_GE_F64 class methods ---
2536
2537 Inst_VOPC__V_CMP_GE_F64::Inst_VOPC__V_CMP_GE_F64(InFmt_VOPC *iFmt)
2538 : Inst_VOPC(iFmt, "v_cmp_ge_f64")
2539 {
2540 setFlag(ALU);
2541 setFlag(F64);
2542 } // Inst_VOPC__V_CMP_GE_F64
2543
2544 Inst_VOPC__V_CMP_GE_F64::~Inst_VOPC__V_CMP_GE_F64()
2545 {
2546 } // ~Inst_VOPC__V_CMP_GE_F64
2547
2548 // --- description from .arch file ---
2549 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
2550 void
2551 Inst_VOPC__V_CMP_GE_F64::execute(GPUDynInstPtr gpuDynInst)
2552 {
2553 Wavefront *wf = gpuDynInst->wavefront();
2554 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2555 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2556 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2557
2558 src0.readSrc();
2559 src1.read();
2560
2561 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2562 if (wf->execMask(lane)) {
2563 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
2564 }
2565 }
2566
2567 vcc.write();
2568 } // execute
2569 // --- Inst_VOPC__V_CMP_O_F64 class methods ---
2570
2571 Inst_VOPC__V_CMP_O_F64::Inst_VOPC__V_CMP_O_F64(InFmt_VOPC *iFmt)
2572 : Inst_VOPC(iFmt, "v_cmp_o_f64")
2573 {
2574 setFlag(ALU);
2575 setFlag(F64);
2576 } // Inst_VOPC__V_CMP_O_F64
2577
2578 Inst_VOPC__V_CMP_O_F64::~Inst_VOPC__V_CMP_O_F64()
2579 {
2580 } // ~Inst_VOPC__V_CMP_O_F64
2581
2582 // --- description from .arch file ---
2583 // D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC encoding.
2584 void
2585 Inst_VOPC__V_CMP_O_F64::execute(GPUDynInstPtr gpuDynInst)
2586 {
2587 Wavefront *wf = gpuDynInst->wavefront();
2588 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2589 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2590 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2591
2592 src0.readSrc();
2593 src1.read();
2594
2595 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2596 if (wf->execMask(lane)) {
2597 vcc.setBit(lane, (!std::isnan(src0[lane])
2598 && !std::isnan(src1[lane])) ? 1 : 0);
2599 }
2600 }
2601
2602 vcc.write();
2603 } // execute
2604 // --- Inst_VOPC__V_CMP_U_F64 class methods ---
2605
2606 Inst_VOPC__V_CMP_U_F64::Inst_VOPC__V_CMP_U_F64(InFmt_VOPC *iFmt)
2607 : Inst_VOPC(iFmt, "v_cmp_u_f64")
2608 {
2609 setFlag(ALU);
2610 setFlag(F64);
2611 } // Inst_VOPC__V_CMP_U_F64
2612
2613 Inst_VOPC__V_CMP_U_F64::~Inst_VOPC__V_CMP_U_F64()
2614 {
2615 } // ~Inst_VOPC__V_CMP_U_F64
2616
2617 // --- description from .arch file ---
2618 // D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC encoding.
2619 void
2620 Inst_VOPC__V_CMP_U_F64::execute(GPUDynInstPtr gpuDynInst)
2621 {
2622 Wavefront *wf = gpuDynInst->wavefront();
2623 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2624 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2625 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2626
2627 src0.readSrc();
2628 src1.read();
2629
2630 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2631 if (wf->execMask(lane)) {
2632 vcc.setBit(lane, (std::isnan(src0[lane])
2633 || std::isnan(src1[lane])) ? 1 : 0);
2634 }
2635 }
2636
2637 vcc.write();
2638 } // execute
2639 // --- Inst_VOPC__V_CMP_NGE_F64 class methods ---
2640
2641 Inst_VOPC__V_CMP_NGE_F64::Inst_VOPC__V_CMP_NGE_F64(InFmt_VOPC *iFmt)
2642 : Inst_VOPC(iFmt, "v_cmp_nge_f64")
2643 {
2644 setFlag(ALU);
2645 setFlag(F64);
2646 } // Inst_VOPC__V_CMP_NGE_F64
2647
2648 Inst_VOPC__V_CMP_NGE_F64::~Inst_VOPC__V_CMP_NGE_F64()
2649 {
2650 } // ~Inst_VOPC__V_CMP_NGE_F64
2651
2652 // --- description from .arch file ---
2653 // D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
2654 void
2655 Inst_VOPC__V_CMP_NGE_F64::execute(GPUDynInstPtr gpuDynInst)
2656 {
2657 Wavefront *wf = gpuDynInst->wavefront();
2658 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2659 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2660 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2661
2662 src0.readSrc();
2663 src1.read();
2664
2665 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2666 if (wf->execMask(lane)) {
2667 vcc.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
2668 }
2669 }
2670
2671 vcc.write();
2672 } // execute
2673 // --- Inst_VOPC__V_CMP_NLG_F64 class methods ---
2674
2675 Inst_VOPC__V_CMP_NLG_F64::Inst_VOPC__V_CMP_NLG_F64(InFmt_VOPC *iFmt)
2676 : Inst_VOPC(iFmt, "v_cmp_nlg_f64")
2677 {
2678 setFlag(ALU);
2679 setFlag(F64);
2680 } // Inst_VOPC__V_CMP_NLG_F64
2681
2682 Inst_VOPC__V_CMP_NLG_F64::~Inst_VOPC__V_CMP_NLG_F64()
2683 {
2684 } // ~Inst_VOPC__V_CMP_NLG_F64
2685
2686 // --- description from .arch file ---
2687 // D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
2688 void
2689 Inst_VOPC__V_CMP_NLG_F64::execute(GPUDynInstPtr gpuDynInst)
2690 {
2691 Wavefront *wf = gpuDynInst->wavefront();
2692 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2693 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2694 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2695
2696 src0.readSrc();
2697 src1.read();
2698
2699 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2700 if (wf->execMask(lane)) {
2701 vcc.setBit(lane, !(src0[lane] < src1[lane]
2702 || src0[lane] > src1[lane]) ? 1 : 0);
2703 }
2704 }
2705
2706 vcc.write();
2707 } // execute
2708 // --- Inst_VOPC__V_CMP_NGT_F64 class methods ---
2709
2710 Inst_VOPC__V_CMP_NGT_F64::Inst_VOPC__V_CMP_NGT_F64(InFmt_VOPC *iFmt)
2711 : Inst_VOPC(iFmt, "v_cmp_ngt_f64")
2712 {
2713 setFlag(ALU);
2714 setFlag(F64);
2715 } // Inst_VOPC__V_CMP_NGT_F64
2716
2717 Inst_VOPC__V_CMP_NGT_F64::~Inst_VOPC__V_CMP_NGT_F64()
2718 {
2719 } // ~Inst_VOPC__V_CMP_NGT_F64
2720
2721 // --- description from .arch file ---
2722 // D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
2723 void
2724 Inst_VOPC__V_CMP_NGT_F64::execute(GPUDynInstPtr gpuDynInst)
2725 {
2726 Wavefront *wf = gpuDynInst->wavefront();
2727 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2728 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2729 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2730
2731 src0.readSrc();
2732 src1.read();
2733
2734 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2735 if (wf->execMask(lane)) {
2736 vcc.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
2737 }
2738 }
2739
2740 vcc.write();
2741 } // execute
2742 // --- Inst_VOPC__V_CMP_NLE_F64 class methods ---
2743
2744 Inst_VOPC__V_CMP_NLE_F64::Inst_VOPC__V_CMP_NLE_F64(InFmt_VOPC *iFmt)
2745 : Inst_VOPC(iFmt, "v_cmp_nle_f64")
2746 {
2747 setFlag(ALU);
2748 setFlag(F64);
2749 } // Inst_VOPC__V_CMP_NLE_F64
2750
2751 Inst_VOPC__V_CMP_NLE_F64::~Inst_VOPC__V_CMP_NLE_F64()
2752 {
2753 } // ~Inst_VOPC__V_CMP_NLE_F64
2754
2755 // --- description from .arch file ---
2756 // D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
2757 void
2758 Inst_VOPC__V_CMP_NLE_F64::execute(GPUDynInstPtr gpuDynInst)
2759 {
2760 Wavefront *wf = gpuDynInst->wavefront();
2761 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2762 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2763 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2764
2765 src0.readSrc();
2766 src1.read();
2767
2768 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2769 if (wf->execMask(lane)) {
2770 vcc.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
2771 }
2772 }
2773
2774 vcc.write();
2775 } // execute
2776 // --- Inst_VOPC__V_CMP_NEQ_F64 class methods ---
2777
2778 Inst_VOPC__V_CMP_NEQ_F64::Inst_VOPC__V_CMP_NEQ_F64(InFmt_VOPC *iFmt)
2779 : Inst_VOPC(iFmt, "v_cmp_neq_f64")
2780 {
2781 setFlag(ALU);
2782 setFlag(F64);
2783 } // Inst_VOPC__V_CMP_NEQ_F64
2784
2785 Inst_VOPC__V_CMP_NEQ_F64::~Inst_VOPC__V_CMP_NEQ_F64()
2786 {
2787 } // ~Inst_VOPC__V_CMP_NEQ_F64
2788
2789 // --- description from .arch file ---
2790 // D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
2791 void
2792 Inst_VOPC__V_CMP_NEQ_F64::execute(GPUDynInstPtr gpuDynInst)
2793 {
2794 Wavefront *wf = gpuDynInst->wavefront();
2795 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2796 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2797 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2798
2799 src0.readSrc();
2800 src1.read();
2801
2802 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2803 if (wf->execMask(lane)) {
2804 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
2805 }
2806 }
2807
2808 vcc.write();
2809 } // execute
2810 // --- Inst_VOPC__V_CMP_NLT_F64 class methods ---
2811
2812 Inst_VOPC__V_CMP_NLT_F64::Inst_VOPC__V_CMP_NLT_F64(InFmt_VOPC *iFmt)
2813 : Inst_VOPC(iFmt, "v_cmp_nlt_f64")
2814 {
2815 setFlag(ALU);
2816 setFlag(F64);
2817 } // Inst_VOPC__V_CMP_NLT_F64
2818
2819 Inst_VOPC__V_CMP_NLT_F64::~Inst_VOPC__V_CMP_NLT_F64()
2820 {
2821 } // ~Inst_VOPC__V_CMP_NLT_F64
2822
2823 // --- description from .arch file ---
2824 // D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
2825 void
2826 Inst_VOPC__V_CMP_NLT_F64::execute(GPUDynInstPtr gpuDynInst)
2827 {
2828 Wavefront *wf = gpuDynInst->wavefront();
2829 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2830 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2831 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2832
2833 src0.readSrc();
2834 src1.read();
2835
2836 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2837 if (wf->execMask(lane)) {
2838 vcc.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
2839 }
2840 }
2841
2842 vcc.write();
2843 } // execute
2844 // --- Inst_VOPC__V_CMP_TRU_F64 class methods ---
2845
2846 Inst_VOPC__V_CMP_TRU_F64::Inst_VOPC__V_CMP_TRU_F64(InFmt_VOPC *iFmt)
2847 : Inst_VOPC(iFmt, "v_cmp_tru_f64")
2848 {
2849 setFlag(ALU);
2850 setFlag(F64);
2851 } // Inst_VOPC__V_CMP_TRU_F64
2852
2853 Inst_VOPC__V_CMP_TRU_F64::~Inst_VOPC__V_CMP_TRU_F64()
2854 {
2855 } // ~Inst_VOPC__V_CMP_TRU_F64
2856
2857 // --- description from .arch file ---
2858 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
2859 void
2860 Inst_VOPC__V_CMP_TRU_F64::execute(GPUDynInstPtr gpuDynInst)
2861 {
2862 Wavefront *wf = gpuDynInst->wavefront();
2863 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2864
2865 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2866 if (wf->execMask(lane)) {
2867 vcc.setBit(lane, 1);
2868 }
2869 }
2870
2871 vcc.write();
2872 } // execute
2873 // --- Inst_VOPC__V_CMPX_F_F64 class methods ---
2874
2875 Inst_VOPC__V_CMPX_F_F64::Inst_VOPC__V_CMPX_F_F64(InFmt_VOPC *iFmt)
2876 : Inst_VOPC(iFmt, "v_cmpx_f_f64")
2877 {
2878 setFlag(ALU);
2879 setFlag(F64);
2880 setFlag(WritesEXEC);
2881 } // Inst_VOPC__V_CMPX_F_F64
2882
2883 Inst_VOPC__V_CMPX_F_F64::~Inst_VOPC__V_CMPX_F_F64()
2884 {
2885 } // ~Inst_VOPC__V_CMPX_F_F64
2886
2887 // --- description from .arch file ---
2888 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
2889 void
2890 Inst_VOPC__V_CMPX_F_F64::execute(GPUDynInstPtr gpuDynInst)
2891 {
2892 Wavefront *wf = gpuDynInst->wavefront();
2893 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2894
2895 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2896 if (wf->execMask(lane)) {
2897 vcc.setBit(lane, 0);
2898 }
2899 }
2900
2901 vcc.write();
2902 wf->execMask() = vcc.rawData();
2903 } // execute
2904 // --- Inst_VOPC__V_CMPX_LT_F64 class methods ---
2905
2906 Inst_VOPC__V_CMPX_LT_F64::Inst_VOPC__V_CMPX_LT_F64(InFmt_VOPC *iFmt)
2907 : Inst_VOPC(iFmt, "v_cmpx_lt_f64")
2908 {
2909 setFlag(ALU);
2910 setFlag(F64);
2911 setFlag(WritesEXEC);
2912 } // Inst_VOPC__V_CMPX_LT_F64
2913
2914 Inst_VOPC__V_CMPX_LT_F64::~Inst_VOPC__V_CMPX_LT_F64()
2915 {
2916 } // ~Inst_VOPC__V_CMPX_LT_F64
2917
2918 // --- description from .arch file ---
2919 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
2920 void
2921 Inst_VOPC__V_CMPX_LT_F64::execute(GPUDynInstPtr gpuDynInst)
2922 {
2923 Wavefront *wf = gpuDynInst->wavefront();
2924 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2925 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2926 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2927
2928 src0.readSrc();
2929 src1.read();
2930
2931 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2932 if (wf->execMask(lane)) {
2933 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
2934 }
2935 }
2936
2937 vcc.write();
2938 wf->execMask() = vcc.rawData();
2939 } // execute
2940 // --- Inst_VOPC__V_CMPX_EQ_F64 class methods ---
2941
2942 Inst_VOPC__V_CMPX_EQ_F64::Inst_VOPC__V_CMPX_EQ_F64(InFmt_VOPC *iFmt)
2943 : Inst_VOPC(iFmt, "v_cmpx_eq_f64")
2944 {
2945 setFlag(ALU);
2946 setFlag(F64);
2947 setFlag(WritesEXEC);
2948 } // Inst_VOPC__V_CMPX_EQ_F64
2949
2950 Inst_VOPC__V_CMPX_EQ_F64::~Inst_VOPC__V_CMPX_EQ_F64()
2951 {
2952 } // ~Inst_VOPC__V_CMPX_EQ_F64
2953
2954 // --- description from .arch file ---
2955 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
2956 void
2957 Inst_VOPC__V_CMPX_EQ_F64::execute(GPUDynInstPtr gpuDynInst)
2958 {
2959 Wavefront *wf = gpuDynInst->wavefront();
2960 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2961 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2962 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2963
2964 src0.readSrc();
2965 src1.read();
2966
2967 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2968 if (wf->execMask(lane)) {
2969 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
2970 }
2971 }
2972
2973 vcc.write();
2974 wf->execMask() = vcc.rawData();
2975 } // execute
2976 // --- Inst_VOPC__V_CMPX_LE_F64 class methods ---
2977
2978 Inst_VOPC__V_CMPX_LE_F64::Inst_VOPC__V_CMPX_LE_F64(InFmt_VOPC *iFmt)
2979 : Inst_VOPC(iFmt, "v_cmpx_le_f64")
2980 {
2981 setFlag(ALU);
2982 setFlag(F64);
2983 setFlag(WritesEXEC);
2984 } // Inst_VOPC__V_CMPX_LE_F64
2985
2986 Inst_VOPC__V_CMPX_LE_F64::~Inst_VOPC__V_CMPX_LE_F64()
2987 {
2988 } // ~Inst_VOPC__V_CMPX_LE_F64
2989
2990 // --- description from .arch file ---
2991 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
2992 void
2993 Inst_VOPC__V_CMPX_LE_F64::execute(GPUDynInstPtr gpuDynInst)
2994 {
2995 Wavefront *wf = gpuDynInst->wavefront();
2996 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2997 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2998 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2999
3000 src0.readSrc();
3001 src1.read();
3002
3003 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3004 if (wf->execMask(lane)) {
3005 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
3006 }
3007 }
3008
3009 wf->execMask() = vcc.rawData();
3010 vcc.write();
3011 } // execute
3012 // --- Inst_VOPC__V_CMPX_GT_F64 class methods ---
3013
3014 Inst_VOPC__V_CMPX_GT_F64::Inst_VOPC__V_CMPX_GT_F64(InFmt_VOPC *iFmt)
3015 : Inst_VOPC(iFmt, "v_cmpx_gt_f64")
3016 {
3017 setFlag(ALU);
3018 setFlag(F64);
3019 setFlag(WritesEXEC);
3020 } // Inst_VOPC__V_CMPX_GT_F64
3021
3022 Inst_VOPC__V_CMPX_GT_F64::~Inst_VOPC__V_CMPX_GT_F64()
3023 {
3024 } // ~Inst_VOPC__V_CMPX_GT_F64
3025
3026 // --- description from .arch file ---
3027 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
3028 void
3029 Inst_VOPC__V_CMPX_GT_F64::execute(GPUDynInstPtr gpuDynInst)
3030 {
3031 Wavefront *wf = gpuDynInst->wavefront();
3032 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3033 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3034 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3035
3036 src0.readSrc();
3037 src1.read();
3038
3039 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3040 if (wf->execMask(lane)) {
3041 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
3042 }
3043 }
3044
3045 wf->execMask() = vcc.rawData();
3046 vcc.write();
3047 } // execute
3048 // --- Inst_VOPC__V_CMPX_LG_F64 class methods ---
3049
3050 Inst_VOPC__V_CMPX_LG_F64::Inst_VOPC__V_CMPX_LG_F64(InFmt_VOPC *iFmt)
3051 : Inst_VOPC(iFmt, "v_cmpx_lg_f64")
3052 {
3053 setFlag(ALU);
3054 setFlag(F64);
3055 setFlag(WritesEXEC);
3056 } // Inst_VOPC__V_CMPX_LG_F64
3057
3058 Inst_VOPC__V_CMPX_LG_F64::~Inst_VOPC__V_CMPX_LG_F64()
3059 {
3060 } // ~Inst_VOPC__V_CMPX_LG_F64
3061
3062 // --- description from .arch file ---
3063 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
3064 void
3065 Inst_VOPC__V_CMPX_LG_F64::execute(GPUDynInstPtr gpuDynInst)
3066 {
3067 Wavefront *wf = gpuDynInst->wavefront();
3068 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3069 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3070 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3071
3072 src0.readSrc();
3073 src1.read();
3074
3075 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3076 if (wf->execMask(lane)) {
3077 vcc.setBit(lane, (src0[lane] < src1[lane]
3078 || src0[lane] > src1[lane]) ? 1 : 0);
3079 }
3080 }
3081
3082 wf->execMask() = vcc.rawData();
3083 vcc.write();
3084 } // execute
3085 // --- Inst_VOPC__V_CMPX_GE_F64 class methods ---
3086
3087 Inst_VOPC__V_CMPX_GE_F64::Inst_VOPC__V_CMPX_GE_F64(InFmt_VOPC *iFmt)
3088 : Inst_VOPC(iFmt, "v_cmpx_ge_f64")
3089 {
3090 setFlag(ALU);
3091 setFlag(F64);
3092 setFlag(WritesEXEC);
3093 } // Inst_VOPC__V_CMPX_GE_F64
3094
3095 Inst_VOPC__V_CMPX_GE_F64::~Inst_VOPC__V_CMPX_GE_F64()
3096 {
3097 } // ~Inst_VOPC__V_CMPX_GE_F64
3098
3099 // --- description from .arch file ---
3100 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
3101 void
3102 Inst_VOPC__V_CMPX_GE_F64::execute(GPUDynInstPtr gpuDynInst)
3103 {
3104 Wavefront *wf = gpuDynInst->wavefront();
3105 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3106 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3107 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3108
3109 src0.readSrc();
3110 src1.read();
3111
3112 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3113 if (wf->execMask(lane)) {
3114 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
3115 }
3116 }
3117
3118 wf->execMask() = vcc.rawData();
3119 vcc.write();
3120 } // execute
3121 // --- Inst_VOPC__V_CMPX_O_F64 class methods ---
3122
3123 Inst_VOPC__V_CMPX_O_F64::Inst_VOPC__V_CMPX_O_F64(InFmt_VOPC *iFmt)
3124 : Inst_VOPC(iFmt, "v_cmpx_o_f64")
3125 {
3126 setFlag(ALU);
3127 setFlag(F64);
3128 setFlag(WritesEXEC);
3129 } // Inst_VOPC__V_CMPX_O_F64
3130
3131 Inst_VOPC__V_CMPX_O_F64::~Inst_VOPC__V_CMPX_O_F64()
3132 {
3133 } // ~Inst_VOPC__V_CMPX_O_F64
3134
3135 // --- description from .arch file ---
3136 // EXEC,D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC
3137 // encoding.
3138 void
3139 Inst_VOPC__V_CMPX_O_F64::execute(GPUDynInstPtr gpuDynInst)
3140 {
3141 Wavefront *wf = gpuDynInst->wavefront();
3142 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3143 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3144 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3145
3146 src0.readSrc();
3147 src1.read();
3148
3149 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3150 if (wf->execMask(lane)) {
3151 vcc.setBit(lane, (!std::isnan(src0[lane])
3152 && !std::isnan(src1[lane])) ? 1 : 0);
3153 }
3154 }
3155
3156 wf->execMask() = vcc.rawData();
3157 vcc.write();
3158 } // execute
3159 // --- Inst_VOPC__V_CMPX_U_F64 class methods ---
3160
3161 Inst_VOPC__V_CMPX_U_F64::Inst_VOPC__V_CMPX_U_F64(InFmt_VOPC *iFmt)
3162 : Inst_VOPC(iFmt, "v_cmpx_u_f64")
3163 {
3164 setFlag(ALU);
3165 setFlag(F64);
3166 setFlag(WritesEXEC);
3167 } // Inst_VOPC__V_CMPX_U_F64
3168
3169 Inst_VOPC__V_CMPX_U_F64::~Inst_VOPC__V_CMPX_U_F64()
3170 {
3171 } // ~Inst_VOPC__V_CMPX_U_F64
3172
3173 // --- description from .arch file ---
3174 // EXEC,D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC
3175 // encoding.
3176 void
3177 Inst_VOPC__V_CMPX_U_F64::execute(GPUDynInstPtr gpuDynInst)
3178 {
3179 Wavefront *wf = gpuDynInst->wavefront();
3180 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3181 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3182 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3183
3184 src0.readSrc();
3185 src1.read();
3186
3187 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3188 if (wf->execMask(lane)) {
3189 vcc.setBit(lane, (std::isnan(src0[lane])
3190 || std::isnan(src1[lane])) ? 1 : 0);
3191 }
3192 }
3193
3194 wf->execMask() = vcc.rawData();
3195 vcc.write();
3196 } // execute
3197 // --- Inst_VOPC__V_CMPX_NGE_F64 class methods ---
3198
3199 Inst_VOPC__V_CMPX_NGE_F64::Inst_VOPC__V_CMPX_NGE_F64(InFmt_VOPC *iFmt)
3200 : Inst_VOPC(iFmt, "v_cmpx_nge_f64")
3201 {
3202 setFlag(ALU);
3203 setFlag(F64);
3204 setFlag(WritesEXEC);
3205 } // Inst_VOPC__V_CMPX_NGE_F64
3206
3207 Inst_VOPC__V_CMPX_NGE_F64::~Inst_VOPC__V_CMPX_NGE_F64()
3208 {
3209 } // ~Inst_VOPC__V_CMPX_NGE_F64
3210
3211 // --- description from .arch file ---
3212 // EXEC,D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
3213 void
3214 Inst_VOPC__V_CMPX_NGE_F64::execute(GPUDynInstPtr gpuDynInst)
3215 {
3216 Wavefront *wf = gpuDynInst->wavefront();
3217 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3218 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3219 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3220
3221 src0.readSrc();
3222 src1.read();
3223
3224 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3225 if (wf->execMask(lane)) {
3226 vcc.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
3227 }
3228 }
3229
3230 wf->execMask() = vcc.rawData();
3231 vcc.write();
3232 } // execute
3233 // --- Inst_VOPC__V_CMPX_NLG_F64 class methods ---
3234
3235 Inst_VOPC__V_CMPX_NLG_F64::Inst_VOPC__V_CMPX_NLG_F64(InFmt_VOPC *iFmt)
3236 : Inst_VOPC(iFmt, "v_cmpx_nlg_f64")
3237 {
3238 setFlag(ALU);
3239 setFlag(F64);
3240 setFlag(WritesEXEC);
3241 } // Inst_VOPC__V_CMPX_NLG_F64
3242
3243 Inst_VOPC__V_CMPX_NLG_F64::~Inst_VOPC__V_CMPX_NLG_F64()
3244 {
3245 } // ~Inst_VOPC__V_CMPX_NLG_F64
3246
3247 // --- description from .arch file ---
3248 // EXEC,D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
3249 void
3250 Inst_VOPC__V_CMPX_NLG_F64::execute(GPUDynInstPtr gpuDynInst)
3251 {
3252 Wavefront *wf = gpuDynInst->wavefront();
3253 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3254 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3255 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3256
3257 src0.readSrc();
3258 src1.read();
3259
3260 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3261 if (wf->execMask(lane)) {
3262 vcc.setBit(lane, !(src0[lane] < src1[lane]
3263 || src0[lane] > src1[lane]) ? 1 : 0);
3264 }
3265 }
3266
3267 wf->execMask() = vcc.rawData();
3268 vcc.write();
3269 } // execute
3270 // --- Inst_VOPC__V_CMPX_NGT_F64 class methods ---
3271
3272 Inst_VOPC__V_CMPX_NGT_F64::Inst_VOPC__V_CMPX_NGT_F64(InFmt_VOPC *iFmt)
3273 : Inst_VOPC(iFmt, "v_cmpx_ngt_f64")
3274 {
3275 setFlag(ALU);
3276 setFlag(F64);
3277 setFlag(WritesEXEC);
3278 } // Inst_VOPC__V_CMPX_NGT_F64
3279
3280 Inst_VOPC__V_CMPX_NGT_F64::~Inst_VOPC__V_CMPX_NGT_F64()
3281 {
3282 } // ~Inst_VOPC__V_CMPX_NGT_F64
3283
3284 // --- description from .arch file ---
3285 // EXEC,D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
3286 void
3287 Inst_VOPC__V_CMPX_NGT_F64::execute(GPUDynInstPtr gpuDynInst)
3288 {
3289 Wavefront *wf = gpuDynInst->wavefront();
3290 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3291 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3292 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3293
3294 src0.readSrc();
3295 src1.read();
3296
3297 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3298 if (wf->execMask(lane)) {
3299 vcc.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
3300 }
3301 }
3302
3303 wf->execMask() = vcc.rawData();
3304 vcc.write();
3305 } // execute
3306 // --- Inst_VOPC__V_CMPX_NLE_F64 class methods ---
3307
3308 Inst_VOPC__V_CMPX_NLE_F64::Inst_VOPC__V_CMPX_NLE_F64(InFmt_VOPC *iFmt)
3309 : Inst_VOPC(iFmt, "v_cmpx_nle_f64")
3310 {
3311 setFlag(ALU);
3312 setFlag(F64);
3313 setFlag(WritesEXEC);
3314 } // Inst_VOPC__V_CMPX_NLE_F64
3315
3316 Inst_VOPC__V_CMPX_NLE_F64::~Inst_VOPC__V_CMPX_NLE_F64()
3317 {
3318 } // ~Inst_VOPC__V_CMPX_NLE_F64
3319
3320 // --- description from .arch file ---
3321 // EXEC,D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
3322 void
3323 Inst_VOPC__V_CMPX_NLE_F64::execute(GPUDynInstPtr gpuDynInst)
3324 {
3325 Wavefront *wf = gpuDynInst->wavefront();
3326 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3327 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3328 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3329
3330 src0.readSrc();
3331 src1.read();
3332
3333 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3334 if (wf->execMask(lane)) {
3335 vcc.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
3336 }
3337 }
3338
3339 wf->execMask() = vcc.rawData();
3340 vcc.write();
3341 } // execute
3342 // --- Inst_VOPC__V_CMPX_NEQ_F64 class methods ---
3343
3344 Inst_VOPC__V_CMPX_NEQ_F64::Inst_VOPC__V_CMPX_NEQ_F64(InFmt_VOPC *iFmt)
3345 : Inst_VOPC(iFmt, "v_cmpx_neq_f64")
3346 {
3347 setFlag(ALU);
3348 setFlag(F64);
3349 setFlag(WritesEXEC);
3350 } // Inst_VOPC__V_CMPX_NEQ_F64
3351
3352 Inst_VOPC__V_CMPX_NEQ_F64::~Inst_VOPC__V_CMPX_NEQ_F64()
3353 {
3354 } // ~Inst_VOPC__V_CMPX_NEQ_F64
3355
3356 // --- description from .arch file ---
3357 // EXEC,D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
3358 void
3359 Inst_VOPC__V_CMPX_NEQ_F64::execute(GPUDynInstPtr gpuDynInst)
3360 {
3361 Wavefront *wf = gpuDynInst->wavefront();
3362 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3363 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3364 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3365
3366 src0.readSrc();
3367 src1.read();
3368
3369 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3370 if (wf->execMask(lane)) {
3371 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
3372 }
3373 }
3374
3375 wf->execMask() = vcc.rawData();
3376 vcc.write();
3377 } // execute
3378 // --- Inst_VOPC__V_CMPX_NLT_F64 class methods ---
3379
3380 Inst_VOPC__V_CMPX_NLT_F64::Inst_VOPC__V_CMPX_NLT_F64(InFmt_VOPC *iFmt)
3381 : Inst_VOPC(iFmt, "v_cmpx_nlt_f64")
3382 {
3383 setFlag(ALU);
3384 setFlag(F64);
3385 setFlag(WritesEXEC);
3386 } // Inst_VOPC__V_CMPX_NLT_F64
3387
3388 Inst_VOPC__V_CMPX_NLT_F64::~Inst_VOPC__V_CMPX_NLT_F64()
3389 {
3390 } // ~Inst_VOPC__V_CMPX_NLT_F64
3391
3392 // --- description from .arch file ---
3393 // EXEC,D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
3394 void
3395 Inst_VOPC__V_CMPX_NLT_F64::execute(GPUDynInstPtr gpuDynInst)
3396 {
3397 Wavefront *wf = gpuDynInst->wavefront();
3398 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3399 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3400 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3401
3402 src0.readSrc();
3403 src1.read();
3404
3405 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3406 if (wf->execMask(lane)) {
3407 vcc.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
3408 }
3409 }
3410
3411 wf->execMask() = vcc.rawData();
3412 vcc.write();
3413 } // execute
3414 // --- Inst_VOPC__V_CMPX_TRU_F64 class methods ---
3415
3416 Inst_VOPC__V_CMPX_TRU_F64::Inst_VOPC__V_CMPX_TRU_F64(InFmt_VOPC *iFmt)
3417 : Inst_VOPC(iFmt, "v_cmpx_tru_f64")
3418 {
3419 setFlag(ALU);
3420 setFlag(F64);
3421 setFlag(WritesEXEC);
3422 } // Inst_VOPC__V_CMPX_TRU_F64
3423
3424 Inst_VOPC__V_CMPX_TRU_F64::~Inst_VOPC__V_CMPX_TRU_F64()
3425 {
3426 } // ~Inst_VOPC__V_CMPX_TRU_F64
3427
3428 // --- description from .arch file ---
3429 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
3430 void
3431 Inst_VOPC__V_CMPX_TRU_F64::execute(GPUDynInstPtr gpuDynInst)
3432 {
3433 Wavefront *wf = gpuDynInst->wavefront();
3434 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3435
3436 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3437 if (wf->execMask(lane)) {
3438 vcc.setBit(lane, 1);
3439 }
3440 }
3441
3442 wf->execMask() = vcc.rawData();
3443 vcc.write();
3444 } // execute
3445 // --- Inst_VOPC__V_CMP_F_I16 class methods ---
3446
3447 Inst_VOPC__V_CMP_F_I16::Inst_VOPC__V_CMP_F_I16(InFmt_VOPC *iFmt)
3448 : Inst_VOPC(iFmt, "v_cmp_f_i16")
3449 {
3450 setFlag(ALU);
3451 } // Inst_VOPC__V_CMP_F_I16
3452
3453 Inst_VOPC__V_CMP_F_I16::~Inst_VOPC__V_CMP_F_I16()
3454 {
3455 } // ~Inst_VOPC__V_CMP_F_I16
3456
3457 // --- description from .arch file ---
3458 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
3459 void
3460 Inst_VOPC__V_CMP_F_I16::execute(GPUDynInstPtr gpuDynInst)
3461 {
3462 Wavefront *wf = gpuDynInst->wavefront();
3463 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3464
3465 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3466 if (wf->execMask(lane)) {
3467 vcc.setBit(lane, 0);
3468 }
3469 }
3470
3471 vcc.write();
3472 } // execute
3473 // --- Inst_VOPC__V_CMP_LT_I16 class methods ---
3474
3475 Inst_VOPC__V_CMP_LT_I16::Inst_VOPC__V_CMP_LT_I16(InFmt_VOPC *iFmt)
3476 : Inst_VOPC(iFmt, "v_cmp_lt_i16")
3477 {
3478 setFlag(ALU);
3479 } // Inst_VOPC__V_CMP_LT_I16
3480
3481 Inst_VOPC__V_CMP_LT_I16::~Inst_VOPC__V_CMP_LT_I16()
3482 {
3483 } // ~Inst_VOPC__V_CMP_LT_I16
3484
3485 // --- description from .arch file ---
3486 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
3487 void
3488 Inst_VOPC__V_CMP_LT_I16::execute(GPUDynInstPtr gpuDynInst)
3489 {
3490 Wavefront *wf = gpuDynInst->wavefront();
3491 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
3492 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
3493 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3494
3495 src0.readSrc();
3496 src1.read();
3497
3498 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3499 if (wf->execMask(lane)) {
3500 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
3501 }
3502 }
3503
3504 vcc.write();
3505 } // execute
3506 // --- Inst_VOPC__V_CMP_EQ_I16 class methods ---
3507
3508 Inst_VOPC__V_CMP_EQ_I16::Inst_VOPC__V_CMP_EQ_I16(InFmt_VOPC *iFmt)
3509 : Inst_VOPC(iFmt, "v_cmp_eq_i16")
3510 {
3511 setFlag(ALU);
3512 } // Inst_VOPC__V_CMP_EQ_I16
3513
3514 Inst_VOPC__V_CMP_EQ_I16::~Inst_VOPC__V_CMP_EQ_I16()
3515 {
3516 } // ~Inst_VOPC__V_CMP_EQ_I16
3517
3518 // --- description from .arch file ---
3519 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
3520 void
3521 Inst_VOPC__V_CMP_EQ_I16::execute(GPUDynInstPtr gpuDynInst)
3522 {
3523 Wavefront *wf = gpuDynInst->wavefront();
3524 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
3525 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
3526 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3527
3528 src0.readSrc();
3529 src1.read();
3530
3531 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3532 if (wf->execMask(lane)) {
3533 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
3534 }
3535 }
3536
3537 vcc.write();
3538 } // execute
3539 // --- Inst_VOPC__V_CMP_LE_I16 class methods ---
3540
3541 Inst_VOPC__V_CMP_LE_I16::Inst_VOPC__V_CMP_LE_I16(InFmt_VOPC *iFmt)
3542 : Inst_VOPC(iFmt, "v_cmp_le_i16")
3543 {
3544 setFlag(ALU);
3545 } // Inst_VOPC__V_CMP_LE_I16
3546
3547 Inst_VOPC__V_CMP_LE_I16::~Inst_VOPC__V_CMP_LE_I16()
3548 {
3549 } // ~Inst_VOPC__V_CMP_LE_I16
3550
3551 // --- description from .arch file ---
3552 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
3553 void
3554 Inst_VOPC__V_CMP_LE_I16::execute(GPUDynInstPtr gpuDynInst)
3555 {
3556 Wavefront *wf = gpuDynInst->wavefront();
3557 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
3558 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
3559 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3560
3561 src0.readSrc();
3562 src1.read();
3563
3564 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3565 if (wf->execMask(lane)) {
3566 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
3567 }
3568 }
3569
3570 vcc.write();
3571 } // execute
3572 // --- Inst_VOPC__V_CMP_GT_I16 class methods ---
3573
3574 Inst_VOPC__V_CMP_GT_I16::Inst_VOPC__V_CMP_GT_I16(InFmt_VOPC *iFmt)
3575 : Inst_VOPC(iFmt, "v_cmp_gt_i16")
3576 {
3577 setFlag(ALU);
3578 } // Inst_VOPC__V_CMP_GT_I16
3579
3580 Inst_VOPC__V_CMP_GT_I16::~Inst_VOPC__V_CMP_GT_I16()
3581 {
3582 } // ~Inst_VOPC__V_CMP_GT_I16
3583
3584 // --- description from .arch file ---
3585 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
3586 void
3587 Inst_VOPC__V_CMP_GT_I16::execute(GPUDynInstPtr gpuDynInst)
3588 {
3589 Wavefront *wf = gpuDynInst->wavefront();
3590 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
3591 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
3592 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3593
3594 src0.readSrc();
3595 src1.read();
3596
3597 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3598 if (wf->execMask(lane)) {
3599 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
3600 }
3601 }
3602
3603 vcc.write();
3604 } // execute
3605 // --- Inst_VOPC__V_CMP_NE_I16 class methods ---
3606
3607 Inst_VOPC__V_CMP_NE_I16::Inst_VOPC__V_CMP_NE_I16(InFmt_VOPC *iFmt)
3608 : Inst_VOPC(iFmt, "v_cmp_ne_i16")
3609 {
3610 setFlag(ALU);
3611 } // Inst_VOPC__V_CMP_NE_I16
3612
3613 Inst_VOPC__V_CMP_NE_I16::~Inst_VOPC__V_CMP_NE_I16()
3614 {
3615 } // ~Inst_VOPC__V_CMP_NE_I16
3616
3617 // --- description from .arch file ---
3618 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
3619 void
3620 Inst_VOPC__V_CMP_NE_I16::execute(GPUDynInstPtr gpuDynInst)
3621 {
3622 Wavefront *wf = gpuDynInst->wavefront();
3623 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
3624 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
3625 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3626
3627 src0.readSrc();
3628 src1.read();
3629
3630 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3631 if (wf->execMask(lane)) {
3632 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
3633 }
3634 }
3635
3636 vcc.write();
3637 } // execute
3638 // --- Inst_VOPC__V_CMP_GE_I16 class methods ---
3639
3640 Inst_VOPC__V_CMP_GE_I16::Inst_VOPC__V_CMP_GE_I16(InFmt_VOPC *iFmt)
3641 : Inst_VOPC(iFmt, "v_cmp_ge_i16")
3642 {
3643 setFlag(ALU);
3644 } // Inst_VOPC__V_CMP_GE_I16
3645
3646 Inst_VOPC__V_CMP_GE_I16::~Inst_VOPC__V_CMP_GE_I16()
3647 {
3648 } // ~Inst_VOPC__V_CMP_GE_I16
3649
3650 // --- description from .arch file ---
3651 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
3652 void
3653 Inst_VOPC__V_CMP_GE_I16::execute(GPUDynInstPtr gpuDynInst)
3654 {
3655 Wavefront *wf = gpuDynInst->wavefront();
3656 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
3657 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
3658 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3659
3660 src0.readSrc();
3661 src1.read();
3662
3663 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3664 if (wf->execMask(lane)) {
3665 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
3666 }
3667 }
3668
3669 vcc.write();
3670 } // execute
3671 // --- Inst_VOPC__V_CMP_T_I16 class methods ---
3672
3673 Inst_VOPC__V_CMP_T_I16::Inst_VOPC__V_CMP_T_I16(InFmt_VOPC *iFmt)
3674 : Inst_VOPC(iFmt, "v_cmp_t_i16")
3675 {
3676 setFlag(ALU);
3677 } // Inst_VOPC__V_CMP_T_I16
3678
3679 Inst_VOPC__V_CMP_T_I16::~Inst_VOPC__V_CMP_T_I16()
3680 {
3681 } // ~Inst_VOPC__V_CMP_T_I16
3682
3683 // --- description from .arch file ---
3684 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
3685 void
3686 Inst_VOPC__V_CMP_T_I16::execute(GPUDynInstPtr gpuDynInst)
3687 {
3688 Wavefront *wf = gpuDynInst->wavefront();
3689 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3690
3691 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3692 if (wf->execMask(lane)) {
3693 vcc.setBit(lane, 1);
3694 }
3695 }
3696
3697 vcc.write();
3698 } // execute
3699 // --- Inst_VOPC__V_CMP_F_U16 class methods ---
3700
3701 Inst_VOPC__V_CMP_F_U16::Inst_VOPC__V_CMP_F_U16(InFmt_VOPC *iFmt)
3702 : Inst_VOPC(iFmt, "v_cmp_f_u16")
3703 {
3704 setFlag(ALU);
3705 } // Inst_VOPC__V_CMP_F_U16
3706
3707 Inst_VOPC__V_CMP_F_U16::~Inst_VOPC__V_CMP_F_U16()
3708 {
3709 } // ~Inst_VOPC__V_CMP_F_U16
3710
3711 // --- description from .arch file ---
3712 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
3713 void
3714 Inst_VOPC__V_CMP_F_U16::execute(GPUDynInstPtr gpuDynInst)
3715 {
3716 Wavefront *wf = gpuDynInst->wavefront();
3717 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3718
3719 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3720 if (wf->execMask(lane)) {
3721 vcc.setBit(lane, 0);
3722 }
3723 }
3724
3725 vcc.write();
3726 } // execute
3727 // --- Inst_VOPC__V_CMP_LT_U16 class methods ---
3728
3729 Inst_VOPC__V_CMP_LT_U16::Inst_VOPC__V_CMP_LT_U16(InFmt_VOPC *iFmt)
3730 : Inst_VOPC(iFmt, "v_cmp_lt_u16")
3731 {
3732 setFlag(ALU);
3733 } // Inst_VOPC__V_CMP_LT_U16
3734
3735 Inst_VOPC__V_CMP_LT_U16::~Inst_VOPC__V_CMP_LT_U16()
3736 {
3737 } // ~Inst_VOPC__V_CMP_LT_U16
3738
3739 // --- description from .arch file ---
3740 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
3741 void
3742 Inst_VOPC__V_CMP_LT_U16::execute(GPUDynInstPtr gpuDynInst)
3743 {
3744 Wavefront *wf = gpuDynInst->wavefront();
3745 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
3746 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
3747 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3748
3749 src0.readSrc();
3750 src1.read();
3751
3752 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3753 if (wf->execMask(lane)) {
3754 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
3755 }
3756 }
3757
3758 vcc.write();
3759 } // execute
3760 // --- Inst_VOPC__V_CMP_EQ_U16 class methods ---
3761
3762 Inst_VOPC__V_CMP_EQ_U16::Inst_VOPC__V_CMP_EQ_U16(InFmt_VOPC *iFmt)
3763 : Inst_VOPC(iFmt, "v_cmp_eq_u16")
3764 {
3765 setFlag(ALU);
3766 } // Inst_VOPC__V_CMP_EQ_U16
3767
3768 Inst_VOPC__V_CMP_EQ_U16::~Inst_VOPC__V_CMP_EQ_U16()
3769 {
3770 } // ~Inst_VOPC__V_CMP_EQ_U16
3771
3772 // --- description from .arch file ---
3773 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
3774 void
3775 Inst_VOPC__V_CMP_EQ_U16::execute(GPUDynInstPtr gpuDynInst)
3776 {
3777 Wavefront *wf = gpuDynInst->wavefront();
3778 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
3779 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
3780 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3781
3782 src0.readSrc();
3783 src1.read();
3784
3785 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3786 if (wf->execMask(lane)) {
3787 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
3788 }
3789 }
3790
3791 vcc.write();
3792 } // execute
3793 // --- Inst_VOPC__V_CMP_LE_U16 class methods ---
3794
3795 Inst_VOPC__V_CMP_LE_U16::Inst_VOPC__V_CMP_LE_U16(InFmt_VOPC *iFmt)
3796 : Inst_VOPC(iFmt, "v_cmp_le_u16")
3797 {
3798 setFlag(ALU);
3799 } // Inst_VOPC__V_CMP_LE_U16
3800
3801 Inst_VOPC__V_CMP_LE_U16::~Inst_VOPC__V_CMP_LE_U16()
3802 {
3803 } // ~Inst_VOPC__V_CMP_LE_U16
3804
3805 // --- description from .arch file ---
3806 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
3807 void
3808 Inst_VOPC__V_CMP_LE_U16::execute(GPUDynInstPtr gpuDynInst)
3809 {
3810 Wavefront *wf = gpuDynInst->wavefront();
3811 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
3812 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
3813 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3814
3815 src0.readSrc();
3816 src1.read();
3817
3818 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3819 if (wf->execMask(lane)) {
3820 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
3821 }
3822 }
3823
3824 vcc.write();
3825 } // execute
3826 // --- Inst_VOPC__V_CMP_GT_U16 class methods ---
3827
3828 Inst_VOPC__V_CMP_GT_U16::Inst_VOPC__V_CMP_GT_U16(InFmt_VOPC *iFmt)
3829 : Inst_VOPC(iFmt, "v_cmp_gt_u16")
3830 {
3831 setFlag(ALU);
3832 } // Inst_VOPC__V_CMP_GT_U16
3833
3834 Inst_VOPC__V_CMP_GT_U16::~Inst_VOPC__V_CMP_GT_U16()
3835 {
3836 } // ~Inst_VOPC__V_CMP_GT_U16
3837
3838 // --- description from .arch file ---
3839 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
3840 void
3841 Inst_VOPC__V_CMP_GT_U16::execute(GPUDynInstPtr gpuDynInst)
3842 {
3843 Wavefront *wf = gpuDynInst->wavefront();
3844 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
3845 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
3846 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3847
3848 src0.readSrc();
3849 src1.read();
3850
3851 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3852 if (wf->execMask(lane)) {
3853 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
3854 }
3855 }
3856
3857 vcc.write();
3858 } // execute
3859 // --- Inst_VOPC__V_CMP_NE_U16 class methods ---
3860
3861 Inst_VOPC__V_CMP_NE_U16::Inst_VOPC__V_CMP_NE_U16(InFmt_VOPC *iFmt)
3862 : Inst_VOPC(iFmt, "v_cmp_ne_u16")
3863 {
3864 setFlag(ALU);
3865 } // Inst_VOPC__V_CMP_NE_U16
3866
3867 Inst_VOPC__V_CMP_NE_U16::~Inst_VOPC__V_CMP_NE_U16()
3868 {
3869 } // ~Inst_VOPC__V_CMP_NE_U16
3870
3871 // --- description from .arch file ---
3872 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
3873 void
3874 Inst_VOPC__V_CMP_NE_U16::execute(GPUDynInstPtr gpuDynInst)
3875 {
3876 Wavefront *wf = gpuDynInst->wavefront();
3877 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
3878 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
3879 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3880
3881 src0.readSrc();
3882 src1.read();
3883
3884 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3885 if (wf->execMask(lane)) {
3886 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
3887 }
3888 }
3889
3890 vcc.write();
3891 } // execute
3892 // --- Inst_VOPC__V_CMP_GE_U16 class methods ---
3893
3894 Inst_VOPC__V_CMP_GE_U16::Inst_VOPC__V_CMP_GE_U16(InFmt_VOPC *iFmt)
3895 : Inst_VOPC(iFmt, "v_cmp_ge_u16")
3896 {
3897 setFlag(ALU);
3898 } // Inst_VOPC__V_CMP_GE_U16
3899
3900 Inst_VOPC__V_CMP_GE_U16::~Inst_VOPC__V_CMP_GE_U16()
3901 {
3902 } // ~Inst_VOPC__V_CMP_GE_U16
3903
3904 // --- description from .arch file ---
3905 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
3906 void
3907 Inst_VOPC__V_CMP_GE_U16::execute(GPUDynInstPtr gpuDynInst)
3908 {
3909 Wavefront *wf = gpuDynInst->wavefront();
3910 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
3911 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
3912 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3913
3914 src0.readSrc();
3915 src1.read();
3916
3917 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3918 if (wf->execMask(lane)) {
3919 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
3920 }
3921 }
3922
3923 vcc.write();
3924 } // execute
3925 // --- Inst_VOPC__V_CMP_T_U16 class methods ---
3926
3927 Inst_VOPC__V_CMP_T_U16::Inst_VOPC__V_CMP_T_U16(InFmt_VOPC *iFmt)
3928 : Inst_VOPC(iFmt, "v_cmp_t_u16")
3929 {
3930 setFlag(ALU);
3931 } // Inst_VOPC__V_CMP_T_U16
3932
3933 Inst_VOPC__V_CMP_T_U16::~Inst_VOPC__V_CMP_T_U16()
3934 {
3935 } // ~Inst_VOPC__V_CMP_T_U16
3936
3937 // --- description from .arch file ---
3938 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
3939 void
3940 Inst_VOPC__V_CMP_T_U16::execute(GPUDynInstPtr gpuDynInst)
3941 {
3942 Wavefront *wf = gpuDynInst->wavefront();
3943 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3944
3945 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3946 if (wf->execMask(lane)) {
3947 vcc.setBit(lane, 1);
3948 }
3949 }
3950
3951 vcc.write();
3952 } // execute
3953 // --- Inst_VOPC__V_CMPX_F_I16 class methods ---
3954
3955 Inst_VOPC__V_CMPX_F_I16::Inst_VOPC__V_CMPX_F_I16(InFmt_VOPC *iFmt)
3956 : Inst_VOPC(iFmt, "v_cmpx_f_i16")
3957 {
3958 setFlag(ALU);
3959 setFlag(WritesEXEC);
3960 } // Inst_VOPC__V_CMPX_F_I16
3961
3962 Inst_VOPC__V_CMPX_F_I16::~Inst_VOPC__V_CMPX_F_I16()
3963 {
3964 } // ~Inst_VOPC__V_CMPX_F_I16
3965
3966 // --- description from .arch file ---
3967 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
3968 void
3969 Inst_VOPC__V_CMPX_F_I16::execute(GPUDynInstPtr gpuDynInst)
3970 {
3971 Wavefront *wf = gpuDynInst->wavefront();
3972 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3973
3974 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3975 if (wf->execMask(lane)) {
3976 vcc.setBit(lane, 0);
3977 }
3978 }
3979
3980 wf->execMask() = vcc.rawData();
3981 vcc.write();
3982 } // execute
3983 // --- Inst_VOPC__V_CMPX_LT_I16 class methods ---
3984
3985 Inst_VOPC__V_CMPX_LT_I16::Inst_VOPC__V_CMPX_LT_I16(InFmt_VOPC *iFmt)
3986 : Inst_VOPC(iFmt, "v_cmpx_lt_i16")
3987 {
3988 setFlag(ALU);
3989 setFlag(WritesEXEC);
3990 } // Inst_VOPC__V_CMPX_LT_I16
3991
3992 Inst_VOPC__V_CMPX_LT_I16::~Inst_VOPC__V_CMPX_LT_I16()
3993 {
3994 } // ~Inst_VOPC__V_CMPX_LT_I16
3995
3996 // --- description from .arch file ---
3997 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
3998 void
3999 Inst_VOPC__V_CMPX_LT_I16::execute(GPUDynInstPtr gpuDynInst)
4000 {
4001 Wavefront *wf = gpuDynInst->wavefront();
4002 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
4003 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
4004 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4005
4006 src0.readSrc();
4007 src1.read();
4008
4009 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4010 if (wf->execMask(lane)) {
4011 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
4012 }
4013 }
4014
4015 wf->execMask() = vcc.rawData();
4016 vcc.write();
4017 } // execute
4018 // --- Inst_VOPC__V_CMPX_EQ_I16 class methods ---
4019
4020 Inst_VOPC__V_CMPX_EQ_I16::Inst_VOPC__V_CMPX_EQ_I16(InFmt_VOPC *iFmt)
4021 : Inst_VOPC(iFmt, "v_cmpx_eq_i16")
4022 {
4023 setFlag(ALU);
4024 setFlag(WritesEXEC);
4025 } // Inst_VOPC__V_CMPX_EQ_I16
4026
4027 Inst_VOPC__V_CMPX_EQ_I16::~Inst_VOPC__V_CMPX_EQ_I16()
4028 {
4029 } // ~Inst_VOPC__V_CMPX_EQ_I16
4030
4031 // --- description from .arch file ---
4032 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
4033 void
4034 Inst_VOPC__V_CMPX_EQ_I16::execute(GPUDynInstPtr gpuDynInst)
4035 {
4036 Wavefront *wf = gpuDynInst->wavefront();
4037 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
4038 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
4039 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4040
4041 src0.readSrc();
4042 src1.read();
4043
4044 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4045 if (wf->execMask(lane)) {
4046 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
4047 }
4048 }
4049
4050 wf->execMask() = vcc.rawData();
4051 vcc.write();
4052 } // execute
4053 // --- Inst_VOPC__V_CMPX_LE_I16 class methods ---
4054
4055 Inst_VOPC__V_CMPX_LE_I16::Inst_VOPC__V_CMPX_LE_I16(InFmt_VOPC *iFmt)
4056 : Inst_VOPC(iFmt, "v_cmpx_le_i16")
4057 {
4058 setFlag(ALU);
4059 setFlag(WritesEXEC);
4060 } // Inst_VOPC__V_CMPX_LE_I16
4061
4062 Inst_VOPC__V_CMPX_LE_I16::~Inst_VOPC__V_CMPX_LE_I16()
4063 {
4064 } // ~Inst_VOPC__V_CMPX_LE_I16
4065
4066 // --- description from .arch file ---
4067 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
4068 void
4069 Inst_VOPC__V_CMPX_LE_I16::execute(GPUDynInstPtr gpuDynInst)
4070 {
4071 Wavefront *wf = gpuDynInst->wavefront();
4072 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
4073 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
4074 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4075
4076 src0.readSrc();
4077 src1.read();
4078
4079 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4080 if (wf->execMask(lane)) {
4081 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
4082 }
4083 }
4084
4085 wf->execMask() = vcc.rawData();
4086 vcc.write();
4087 } // execute
4088 // --- Inst_VOPC__V_CMPX_GT_I16 class methods ---
4089
4090 Inst_VOPC__V_CMPX_GT_I16::Inst_VOPC__V_CMPX_GT_I16(InFmt_VOPC *iFmt)
4091 : Inst_VOPC(iFmt, "v_cmpx_gt_i16")
4092 {
4093 setFlag(ALU);
4094 setFlag(WritesEXEC);
4095 } // Inst_VOPC__V_CMPX_GT_I16
4096
4097 Inst_VOPC__V_CMPX_GT_I16::~Inst_VOPC__V_CMPX_GT_I16()
4098 {
4099 } // ~Inst_VOPC__V_CMPX_GT_I16
4100
4101 // --- description from .arch file ---
4102 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
4103 void
4104 Inst_VOPC__V_CMPX_GT_I16::execute(GPUDynInstPtr gpuDynInst)
4105 {
4106 Wavefront *wf = gpuDynInst->wavefront();
4107 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
4108 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
4109 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4110
4111 src0.readSrc();
4112 src1.read();
4113
4114 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4115 if (wf->execMask(lane)) {
4116 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
4117 }
4118 }
4119
4120 wf->execMask() = vcc.rawData();
4121 vcc.write();
4122 } // execute
4123 // --- Inst_VOPC__V_CMPX_NE_I16 class methods ---
4124
4125 Inst_VOPC__V_CMPX_NE_I16::Inst_VOPC__V_CMPX_NE_I16(InFmt_VOPC *iFmt)
4126 : Inst_VOPC(iFmt, "v_cmpx_ne_i16")
4127 {
4128 setFlag(ALU);
4129 setFlag(WritesEXEC);
4130 } // Inst_VOPC__V_CMPX_NE_I16
4131
4132 Inst_VOPC__V_CMPX_NE_I16::~Inst_VOPC__V_CMPX_NE_I16()
4133 {
4134 } // ~Inst_VOPC__V_CMPX_NE_I16
4135
4136 // --- description from .arch file ---
4137 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
4138 void
4139 Inst_VOPC__V_CMPX_NE_I16::execute(GPUDynInstPtr gpuDynInst)
4140 {
4141 Wavefront *wf = gpuDynInst->wavefront();
4142 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
4143 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
4144 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4145
4146 src0.readSrc();
4147 src1.read();
4148
4149 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4150 if (wf->execMask(lane)) {
4151 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
4152 }
4153 }
4154
4155 wf->execMask() = vcc.rawData();
4156 vcc.write();
4157 } // execute
4158 // --- Inst_VOPC__V_CMPX_GE_I16 class methods ---
4159
4160 Inst_VOPC__V_CMPX_GE_I16::Inst_VOPC__V_CMPX_GE_I16(InFmt_VOPC *iFmt)
4161 : Inst_VOPC(iFmt, "v_cmpx_ge_i16")
4162 {
4163 setFlag(ALU);
4164 setFlag(WritesEXEC);
4165 } // Inst_VOPC__V_CMPX_GE_I16
4166
4167 Inst_VOPC__V_CMPX_GE_I16::~Inst_VOPC__V_CMPX_GE_I16()
4168 {
4169 } // ~Inst_VOPC__V_CMPX_GE_I16
4170
4171 // --- description from .arch file ---
4172 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
4173 void
4174 Inst_VOPC__V_CMPX_GE_I16::execute(GPUDynInstPtr gpuDynInst)
4175 {
4176 Wavefront *wf = gpuDynInst->wavefront();
4177 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
4178 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
4179 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4180
4181 src0.readSrc();
4182 src1.read();
4183
4184 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4185 if (wf->execMask(lane)) {
4186 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
4187 }
4188 }
4189
4190 wf->execMask() = vcc.rawData();
4191 vcc.write();
4192 } // execute
4193 // --- Inst_VOPC__V_CMPX_T_I16 class methods ---
4194
4195 Inst_VOPC__V_CMPX_T_I16::Inst_VOPC__V_CMPX_T_I16(InFmt_VOPC *iFmt)
4196 : Inst_VOPC(iFmt, "v_cmpx_t_i16")
4197 {
4198 setFlag(ALU);
4199 setFlag(WritesEXEC);
4200 } // Inst_VOPC__V_CMPX_T_I16
4201
4202 Inst_VOPC__V_CMPX_T_I16::~Inst_VOPC__V_CMPX_T_I16()
4203 {
4204 } // ~Inst_VOPC__V_CMPX_T_I16
4205
4206 // --- description from .arch file ---
4207 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
4208 void
4209 Inst_VOPC__V_CMPX_T_I16::execute(GPUDynInstPtr gpuDynInst)
4210 {
4211 Wavefront *wf = gpuDynInst->wavefront();
4212 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4213
4214 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4215 if (wf->execMask(lane)) {
4216 vcc.setBit(lane, 1);
4217 }
4218 }
4219
4220 wf->execMask() = vcc.rawData();
4221 vcc.write();
4222 } // execute
4223 // --- Inst_VOPC__V_CMPX_F_U16 class methods ---
4224
4225 Inst_VOPC__V_CMPX_F_U16::Inst_VOPC__V_CMPX_F_U16(InFmt_VOPC *iFmt)
4226 : Inst_VOPC(iFmt, "v_cmpx_f_u16")
4227 {
4228 setFlag(ALU);
4229 setFlag(WritesEXEC);
4230 } // Inst_VOPC__V_CMPX_F_U16
4231
4232 Inst_VOPC__V_CMPX_F_U16::~Inst_VOPC__V_CMPX_F_U16()
4233 {
4234 } // ~Inst_VOPC__V_CMPX_F_U16
4235
4236 // --- description from .arch file ---
4237 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
4238 void
4239 Inst_VOPC__V_CMPX_F_U16::execute(GPUDynInstPtr gpuDynInst)
4240 {
4241 Wavefront *wf = gpuDynInst->wavefront();
4242 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4243
4244 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4245 if (wf->execMask(lane)) {
4246 vcc.setBit(lane, 0);
4247 }
4248 }
4249
4250 wf->execMask() = vcc.rawData();
4251 vcc.write();
4252 } // execute
4253 // --- Inst_VOPC__V_CMPX_LT_U16 class methods ---
4254
4255 Inst_VOPC__V_CMPX_LT_U16::Inst_VOPC__V_CMPX_LT_U16(InFmt_VOPC *iFmt)
4256 : Inst_VOPC(iFmt, "v_cmpx_lt_u16")
4257 {
4258 setFlag(ALU);
4259 setFlag(WritesEXEC);
4260 } // Inst_VOPC__V_CMPX_LT_U16
4261
4262 Inst_VOPC__V_CMPX_LT_U16::~Inst_VOPC__V_CMPX_LT_U16()
4263 {
4264 } // ~Inst_VOPC__V_CMPX_LT_U16
4265
4266 // --- description from .arch file ---
4267 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
4268 void
4269 Inst_VOPC__V_CMPX_LT_U16::execute(GPUDynInstPtr gpuDynInst)
4270 {
4271 Wavefront *wf = gpuDynInst->wavefront();
4272 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
4273 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
4274 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4275
4276 src0.readSrc();
4277 src1.read();
4278
4279 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4280 if (wf->execMask(lane)) {
4281 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
4282 }
4283 }
4284
4285 wf->execMask() = vcc.rawData();
4286 vcc.write();
4287 } // execute
4288 // --- Inst_VOPC__V_CMPX_EQ_U16 class methods ---
4289
4290 Inst_VOPC__V_CMPX_EQ_U16::Inst_VOPC__V_CMPX_EQ_U16(InFmt_VOPC *iFmt)
4291 : Inst_VOPC(iFmt, "v_cmpx_eq_u16")
4292 {
4293 setFlag(ALU);
4294 setFlag(WritesEXEC);
4295 } // Inst_VOPC__V_CMPX_EQ_U16
4296
4297 Inst_VOPC__V_CMPX_EQ_U16::~Inst_VOPC__V_CMPX_EQ_U16()
4298 {
4299 } // ~Inst_VOPC__V_CMPX_EQ_U16
4300
4301 // --- description from .arch file ---
4302 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
4303 void
4304 Inst_VOPC__V_CMPX_EQ_U16::execute(GPUDynInstPtr gpuDynInst)
4305 {
4306 Wavefront *wf = gpuDynInst->wavefront();
4307 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
4308 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
4309 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4310
4311 src0.readSrc();
4312 src1.read();
4313
4314 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4315 if (wf->execMask(lane)) {
4316 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
4317 }
4318 }
4319
4320 wf->execMask() = vcc.rawData();
4321 vcc.write();
4322 } // execute
4323 // --- Inst_VOPC__V_CMPX_LE_U16 class methods ---
4324
4325 Inst_VOPC__V_CMPX_LE_U16::Inst_VOPC__V_CMPX_LE_U16(InFmt_VOPC *iFmt)
4326 : Inst_VOPC(iFmt, "v_cmpx_le_u16")
4327 {
4328 setFlag(ALU);
4329 setFlag(WritesEXEC);
4330 } // Inst_VOPC__V_CMPX_LE_U16
4331
4332 Inst_VOPC__V_CMPX_LE_U16::~Inst_VOPC__V_CMPX_LE_U16()
4333 {
4334 } // ~Inst_VOPC__V_CMPX_LE_U16
4335
4336 // --- description from .arch file ---
4337 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
4338 void
4339 Inst_VOPC__V_CMPX_LE_U16::execute(GPUDynInstPtr gpuDynInst)
4340 {
4341 Wavefront *wf = gpuDynInst->wavefront();
4342 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
4343 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
4344 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4345
4346 src0.readSrc();
4347 src1.read();
4348
4349 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4350 if (wf->execMask(lane)) {
4351 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
4352 }
4353 }
4354
4355 wf->execMask() = vcc.rawData();
4356 vcc.write();
4357 } // execute
4358 // --- Inst_VOPC__V_CMPX_GT_U16 class methods ---
4359
4360 Inst_VOPC__V_CMPX_GT_U16::Inst_VOPC__V_CMPX_GT_U16(InFmt_VOPC *iFmt)
4361 : Inst_VOPC(iFmt, "v_cmpx_gt_u16")
4362 {
4363 setFlag(ALU);
4364 setFlag(WritesEXEC);
4365 } // Inst_VOPC__V_CMPX_GT_U16
4366
4367 Inst_VOPC__V_CMPX_GT_U16::~Inst_VOPC__V_CMPX_GT_U16()
4368 {
4369 } // ~Inst_VOPC__V_CMPX_GT_U16
4370
4371 // --- description from .arch file ---
4372 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
4373 void
4374 Inst_VOPC__V_CMPX_GT_U16::execute(GPUDynInstPtr gpuDynInst)
4375 {
4376 Wavefront *wf = gpuDynInst->wavefront();
4377 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
4378 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
4379 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4380
4381 src0.readSrc();
4382 src1.read();
4383
4384 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4385 if (wf->execMask(lane)) {
4386 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
4387 }
4388 }
4389
4390 wf->execMask() = vcc.rawData();
4391 vcc.write();
4392 } // execute
4393 // --- Inst_VOPC__V_CMPX_NE_U16 class methods ---
4394
4395 Inst_VOPC__V_CMPX_NE_U16::Inst_VOPC__V_CMPX_NE_U16(InFmt_VOPC *iFmt)
4396 : Inst_VOPC(iFmt, "v_cmpx_ne_u16")
4397 {
4398 setFlag(ALU);
4399 setFlag(WritesEXEC);
4400 } // Inst_VOPC__V_CMPX_NE_U16
4401
4402 Inst_VOPC__V_CMPX_NE_U16::~Inst_VOPC__V_CMPX_NE_U16()
4403 {
4404 } // ~Inst_VOPC__V_CMPX_NE_U16
4405
4406 // --- description from .arch file ---
4407 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
4408 void
4409 Inst_VOPC__V_CMPX_NE_U16::execute(GPUDynInstPtr gpuDynInst)
4410 {
4411 Wavefront *wf = gpuDynInst->wavefront();
4412 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
4413 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
4414 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4415
4416 src0.readSrc();
4417 src1.read();
4418
4419 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4420 if (wf->execMask(lane)) {
4421 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
4422 }
4423 }
4424
4425 wf->execMask() = vcc.rawData();
4426 vcc.write();
4427 } // execute
4428 // --- Inst_VOPC__V_CMPX_GE_U16 class methods ---
4429
4430 Inst_VOPC__V_CMPX_GE_U16::Inst_VOPC__V_CMPX_GE_U16(InFmt_VOPC *iFmt)
4431 : Inst_VOPC(iFmt, "v_cmpx_ge_u16")
4432 {
4433 setFlag(ALU);
4434 setFlag(WritesEXEC);
4435 } // Inst_VOPC__V_CMPX_GE_U16
4436
4437 Inst_VOPC__V_CMPX_GE_U16::~Inst_VOPC__V_CMPX_GE_U16()
4438 {
4439 } // ~Inst_VOPC__V_CMPX_GE_U16
4440
4441 // --- description from .arch file ---
4442 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
4443 void
4444 Inst_VOPC__V_CMPX_GE_U16::execute(GPUDynInstPtr gpuDynInst)
4445 {
4446 Wavefront *wf = gpuDynInst->wavefront();
4447 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
4448 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
4449 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4450
4451 src0.readSrc();
4452 src1.read();
4453
4454 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4455 if (wf->execMask(lane)) {
4456 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
4457 }
4458 }
4459
4460 wf->execMask() = vcc.rawData();
4461 vcc.write();
4462 } // execute
4463 // --- Inst_VOPC__V_CMPX_T_U16 class methods ---
4464
4465 Inst_VOPC__V_CMPX_T_U16::Inst_VOPC__V_CMPX_T_U16(InFmt_VOPC *iFmt)
4466 : Inst_VOPC(iFmt, "v_cmpx_t_u16")
4467 {
4468 setFlag(ALU);
4469 setFlag(WritesEXEC);
4470 } // Inst_VOPC__V_CMPX_T_U16
4471
4472 Inst_VOPC__V_CMPX_T_U16::~Inst_VOPC__V_CMPX_T_U16()
4473 {
4474 } // ~Inst_VOPC__V_CMPX_T_U16
4475
4476 // --- description from .arch file ---
4477 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
4478 void
4479 Inst_VOPC__V_CMPX_T_U16::execute(GPUDynInstPtr gpuDynInst)
4480 {
4481 Wavefront *wf = gpuDynInst->wavefront();
4482 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4483
4484 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4485 if (wf->execMask(lane)) {
4486 vcc.setBit(lane, 1);
4487 }
4488 }
4489
4490 wf->execMask() = vcc.rawData();
4491 vcc.write();
4492 } // execute
4493 // --- Inst_VOPC__V_CMP_F_I32 class methods ---
4494
4495 Inst_VOPC__V_CMP_F_I32::Inst_VOPC__V_CMP_F_I32(InFmt_VOPC *iFmt)
4496 : Inst_VOPC(iFmt, "v_cmp_f_i32")
4497 {
4498 setFlag(ALU);
4499 } // Inst_VOPC__V_CMP_F_I32
4500
4501 Inst_VOPC__V_CMP_F_I32::~Inst_VOPC__V_CMP_F_I32()
4502 {
4503 } // ~Inst_VOPC__V_CMP_F_I32
4504
4505 // --- description from .arch file ---
4506 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
4507 void
4508 Inst_VOPC__V_CMP_F_I32::execute(GPUDynInstPtr gpuDynInst)
4509 {
4510 Wavefront *wf = gpuDynInst->wavefront();
4511 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4512
4513 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4514 if (wf->execMask(lane)) {
4515 vcc.setBit(lane, 0);
4516 }
4517 }
4518
4519 vcc.write();
4520 } // execute
4521 // --- Inst_VOPC__V_CMP_LT_I32 class methods ---
4522
4523 Inst_VOPC__V_CMP_LT_I32::Inst_VOPC__V_CMP_LT_I32(InFmt_VOPC *iFmt)
4524 : Inst_VOPC(iFmt, "v_cmp_lt_i32")
4525 {
4526 setFlag(ALU);
4527 } // Inst_VOPC__V_CMP_LT_I32
4528
4529 Inst_VOPC__V_CMP_LT_I32::~Inst_VOPC__V_CMP_LT_I32()
4530 {
4531 } // ~Inst_VOPC__V_CMP_LT_I32
4532
4533 // --- description from .arch file ---
4534 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
4535 void
4536 Inst_VOPC__V_CMP_LT_I32::execute(GPUDynInstPtr gpuDynInst)
4537 {
4538 Wavefront *wf = gpuDynInst->wavefront();
4539 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
4540 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
4541 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4542
4543 src0.readSrc();
4544 src1.read();
4545
4546 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4547 if (wf->execMask(lane)) {
4548 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
4549 }
4550 }
4551
4552 vcc.write();
4553 } // execute
4554 // --- Inst_VOPC__V_CMP_EQ_I32 class methods ---
4555
4556 Inst_VOPC__V_CMP_EQ_I32::Inst_VOPC__V_CMP_EQ_I32(InFmt_VOPC *iFmt)
4557 : Inst_VOPC(iFmt, "v_cmp_eq_i32")
4558 {
4559 setFlag(ALU);
4560 } // Inst_VOPC__V_CMP_EQ_I32
4561
4562 Inst_VOPC__V_CMP_EQ_I32::~Inst_VOPC__V_CMP_EQ_I32()
4563 {
4564 } // ~Inst_VOPC__V_CMP_EQ_I32
4565
4566 // --- description from .arch file ---
4567 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
4568 void
4569 Inst_VOPC__V_CMP_EQ_I32::execute(GPUDynInstPtr gpuDynInst)
4570 {
4571 Wavefront *wf = gpuDynInst->wavefront();
4572 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
4573 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
4574 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4575
4576 src0.readSrc();
4577 src1.read();
4578
4579 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4580 if (wf->execMask(lane)) {
4581 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
4582 }
4583 }
4584
4585 vcc.write();
4586 } // execute
4587 // --- Inst_VOPC__V_CMP_LE_I32 class methods ---
4588
4589 Inst_VOPC__V_CMP_LE_I32::Inst_VOPC__V_CMP_LE_I32(InFmt_VOPC *iFmt)
4590 : Inst_VOPC(iFmt, "v_cmp_le_i32")
4591 {
4592 setFlag(ALU);
4593 } // Inst_VOPC__V_CMP_LE_I32
4594
4595 Inst_VOPC__V_CMP_LE_I32::~Inst_VOPC__V_CMP_LE_I32()
4596 {
4597 } // ~Inst_VOPC__V_CMP_LE_I32
4598
4599 // --- description from .arch file ---
4600 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
4601 void
4602 Inst_VOPC__V_CMP_LE_I32::execute(GPUDynInstPtr gpuDynInst)
4603 {
4604 Wavefront *wf = gpuDynInst->wavefront();
4605 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
4606 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
4607 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4608
4609 src0.readSrc();
4610 src1.read();
4611
4612 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4613 if (wf->execMask(lane)) {
4614 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
4615 }
4616 }
4617
4618 vcc.write();
4619 } // execute
4620 // --- Inst_VOPC__V_CMP_GT_I32 class methods ---
4621
4622 Inst_VOPC__V_CMP_GT_I32::Inst_VOPC__V_CMP_GT_I32(InFmt_VOPC *iFmt)
4623 : Inst_VOPC(iFmt, "v_cmp_gt_i32")
4624 {
4625 setFlag(ALU);
4626 } // Inst_VOPC__V_CMP_GT_I32
4627
4628 Inst_VOPC__V_CMP_GT_I32::~Inst_VOPC__V_CMP_GT_I32()
4629 {
4630 } // ~Inst_VOPC__V_CMP_GT_I32
4631
4632 // --- description from .arch file ---
4633 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
4634 void
4635 Inst_VOPC__V_CMP_GT_I32::execute(GPUDynInstPtr gpuDynInst)
4636 {
4637 Wavefront *wf = gpuDynInst->wavefront();
4638 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
4639 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
4640 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4641
4642 src0.readSrc();
4643 src1.read();
4644
4645 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4646 if (wf->execMask(lane)) {
4647 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
4648 }
4649 }
4650
4651 vcc.write();
4652 } // execute
4653 // --- Inst_VOPC__V_CMP_NE_I32 class methods ---
4654
4655 Inst_VOPC__V_CMP_NE_I32::Inst_VOPC__V_CMP_NE_I32(InFmt_VOPC *iFmt)
4656 : Inst_VOPC(iFmt, "v_cmp_ne_i32")
4657 {
4658 setFlag(ALU);
4659 } // Inst_VOPC__V_CMP_NE_I32
4660
4661 Inst_VOPC__V_CMP_NE_I32::~Inst_VOPC__V_CMP_NE_I32()
4662 {
4663 } // ~Inst_VOPC__V_CMP_NE_I32
4664
4665 // --- description from .arch file ---
4666 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
4667 void
4668 Inst_VOPC__V_CMP_NE_I32::execute(GPUDynInstPtr gpuDynInst)
4669 {
4670 Wavefront *wf = gpuDynInst->wavefront();
4671 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
4672 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
4673 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4674
4675 src0.readSrc();
4676 src1.read();
4677
4678 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4679 if (wf->execMask(lane)) {
4680 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
4681 }
4682 }
4683
4684 vcc.write();
4685 } // execute
4686 // --- Inst_VOPC__V_CMP_GE_I32 class methods ---
4687
4688 Inst_VOPC__V_CMP_GE_I32::Inst_VOPC__V_CMP_GE_I32(InFmt_VOPC *iFmt)
4689 : Inst_VOPC(iFmt, "v_cmp_ge_i32")
4690 {
4691 setFlag(ALU);
4692 } // Inst_VOPC__V_CMP_GE_I32
4693
4694 Inst_VOPC__V_CMP_GE_I32::~Inst_VOPC__V_CMP_GE_I32()
4695 {
4696 } // ~Inst_VOPC__V_CMP_GE_I32
4697
4698 // --- description from .arch file ---
4699 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
4700 void
4701 Inst_VOPC__V_CMP_GE_I32::execute(GPUDynInstPtr gpuDynInst)
4702 {
4703 Wavefront *wf = gpuDynInst->wavefront();
4704 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
4705 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
4706 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4707
4708 src0.readSrc();
4709 src1.read();
4710
4711 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4712 if (wf->execMask(lane)) {
4713 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
4714 }
4715 }
4716
4717 vcc.write();
4718 } // execute
4719 // --- Inst_VOPC__V_CMP_T_I32 class methods ---
4720
4721 Inst_VOPC__V_CMP_T_I32::Inst_VOPC__V_CMP_T_I32(InFmt_VOPC *iFmt)
4722 : Inst_VOPC(iFmt, "v_cmp_t_i32")
4723 {
4724 setFlag(ALU);
4725 } // Inst_VOPC__V_CMP_T_I32
4726
4727 Inst_VOPC__V_CMP_T_I32::~Inst_VOPC__V_CMP_T_I32()
4728 {
4729 } // ~Inst_VOPC__V_CMP_T_I32
4730
4731 // --- description from .arch file ---
4732 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
4733 void
4734 Inst_VOPC__V_CMP_T_I32::execute(GPUDynInstPtr gpuDynInst)
4735 {
4736 Wavefront *wf = gpuDynInst->wavefront();
4737 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4738
4739 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4740 if (wf->execMask(lane)) {
4741 vcc.setBit(lane, 1);
4742 }
4743 }
4744
4745 vcc.write();
4746 } // execute
4747 // --- Inst_VOPC__V_CMP_F_U32 class methods ---
4748
4749 Inst_VOPC__V_CMP_F_U32::Inst_VOPC__V_CMP_F_U32(InFmt_VOPC *iFmt)
4750 : Inst_VOPC(iFmt, "v_cmp_f_u32")
4751 {
4752 setFlag(ALU);
4753 } // Inst_VOPC__V_CMP_F_U32
4754
4755 Inst_VOPC__V_CMP_F_U32::~Inst_VOPC__V_CMP_F_U32()
4756 {
4757 } // ~Inst_VOPC__V_CMP_F_U32
4758
4759 // --- description from .arch file ---
4760 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
4761 void
4762 Inst_VOPC__V_CMP_F_U32::execute(GPUDynInstPtr gpuDynInst)
4763 {
4764 Wavefront *wf = gpuDynInst->wavefront();
4765 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4766
4767 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4768 if (wf->execMask(lane)) {
4769 vcc.setBit(lane, 0);
4770 }
4771 }
4772
4773 vcc.write();
4774 } // execute
4775 // --- Inst_VOPC__V_CMP_LT_U32 class methods ---
4776
4777 Inst_VOPC__V_CMP_LT_U32::Inst_VOPC__V_CMP_LT_U32(InFmt_VOPC *iFmt)
4778 : Inst_VOPC(iFmt, "v_cmp_lt_u32")
4779 {
4780 setFlag(ALU);
4781 } // Inst_VOPC__V_CMP_LT_U32
4782
4783 Inst_VOPC__V_CMP_LT_U32::~Inst_VOPC__V_CMP_LT_U32()
4784 {
4785 } // ~Inst_VOPC__V_CMP_LT_U32
4786
4787 // --- description from .arch file ---
4788 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
4789 void
4790 Inst_VOPC__V_CMP_LT_U32::execute(GPUDynInstPtr gpuDynInst)
4791 {
4792 Wavefront *wf = gpuDynInst->wavefront();
4793 ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
4794 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
4795 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4796
4797 src0.readSrc();
4798 src1.read();
4799
4800 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4801 if (wf->execMask(lane)) {
4802 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
4803 }
4804 }
4805
4806 vcc.write();
4807 } // execute
4808 // --- Inst_VOPC__V_CMP_EQ_U32 class methods ---
4809
4810 Inst_VOPC__V_CMP_EQ_U32::Inst_VOPC__V_CMP_EQ_U32(InFmt_VOPC *iFmt)
4811 : Inst_VOPC(iFmt, "v_cmp_eq_u32")
4812 {
4813 setFlag(ALU);
4814 } // Inst_VOPC__V_CMP_EQ_U32
4815
4816 Inst_VOPC__V_CMP_EQ_U32::~Inst_VOPC__V_CMP_EQ_U32()
4817 {
4818 } // ~Inst_VOPC__V_CMP_EQ_U32
4819
4820 // --- description from .arch file ---
4821 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
4822 void
4823 Inst_VOPC__V_CMP_EQ_U32::execute(GPUDynInstPtr gpuDynInst)
4824 {
4825 Wavefront *wf = gpuDynInst->wavefront();
4826 ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
4827 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
4828 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4829
4830 src0.readSrc();
4831 src1.read();
4832
4833 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4834 if (wf->execMask(lane)) {
4835 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
4836 }
4837 }
4838
4839 vcc.write();
4840 } // execute
4841 // --- Inst_VOPC__V_CMP_LE_U32 class methods ---
4842
4843 Inst_VOPC__V_CMP_LE_U32::Inst_VOPC__V_CMP_LE_U32(InFmt_VOPC *iFmt)
4844 : Inst_VOPC(iFmt, "v_cmp_le_u32")
4845 {
4846 setFlag(ALU);
4847 } // Inst_VOPC__V_CMP_LE_U32
4848
4849 Inst_VOPC__V_CMP_LE_U32::~Inst_VOPC__V_CMP_LE_U32()
4850 {
4851 } // ~Inst_VOPC__V_CMP_LE_U32
4852
4853 // --- description from .arch file ---
4854 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
4855 void
4856 Inst_VOPC__V_CMP_LE_U32::execute(GPUDynInstPtr gpuDynInst)
4857 {
4858 Wavefront *wf = gpuDynInst->wavefront();
4859 ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);