gem5 v24.0.0.0
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write_queue_entry.cc
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1/*
2 * Copyright (c) 2012-2013, 2015-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
48
49#include <cassert>
50#include <string>
51
52#include "base/logging.hh"
53#include "base/types.hh"
54#include "mem/cache/base.hh"
55#include "mem/request.hh"
56
57namespace gem5
58{
59
60inline void
62 Counter order)
63{
64 emplace_back(pkt, readyTime, order);
65}
66
67bool
69{
70 for (auto& t : *this) {
71 if (pkt->trySatisfyFunctional(t.pkt)) {
72 return true;
73 }
74 }
75
76 return false;
77}
78
79void
80WriteQueueEntry::TargetList::print(std::ostream &os, int verbosity,
81 const std::string &prefix) const
82{
83 for (auto& t : *this) {
84 ccprintf(os, "%sFromCPU: ", prefix);
85 t.pkt->print(os, verbosity, "");
86 }
87}
88
89void
90WriteQueueEntry::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
91 Tick when_ready, Counter _order)
92{
93 blkAddr = blk_addr;
94 blkSize = blk_size;
95 isSecure = target->isSecure();
96 readyTime = when_ready;
97 order = _order;
98 assert(target);
99 _isUncacheable = target->req->isUncacheable();
100 inService = false;
101
102 // we should never have more than a single target for cacheable
103 // writes (writebacks and clean evictions)
104 panic_if(!_isUncacheable && !targets.empty(),
105 "Write queue entry %#llx should never have more than one "
106 "cacheable target", blkAddr);
107 panic_if(!((target->isWrite() && _isUncacheable) ||
108 (target->isEviction() && !_isUncacheable) ||
109 target->cmd == MemCmd::WriteClean),
110 "Write queue entry %#llx should be an uncacheable write or "
111 "a cacheable eviction or a writeclean");
112
113 targets.add(target, when_ready, _order);
114
115 // All targets must refer to the same block
116 assert(target->matchBlockAddr(targets.front().pkt, blkSize));
117}
118
119void
121{
122 assert(targets.empty());
123 inService = false;
124}
125
126bool
128{
129 // For printing, we treat the WriteQueueEntry as a whole as single
130 // entity. For other requests, we iterate over the individual
131 // targets since that's where the actual data lies.
132 if (pkt->isPrint()) {
133 pkt->trySatisfyFunctional(this, blkAddr, isSecure, blkSize, nullptr);
134 return false;
135 } else {
136 return targets.trySatisfyFunctional(pkt);
137 }
138}
139
140bool
142{
143 return cache.sendWriteQueuePacket(this);
144}
145
146bool
147WriteQueueEntry::matchBlockAddr(const Addr addr, const bool is_secure) const
148{
149 assert(hasTargets());
150 return (blkAddr == addr) && (isSecure == is_secure);
151}
152
153bool
155{
156 assert(hasTargets());
157 return pkt->matchBlockAddr(blkAddr, isSecure, blkSize);
158}
159
160bool
162{
163 assert(hasTargets());
164 return entry->matchBlockAddr(blkAddr, isSecure);
165}
166
167void
168WriteQueueEntry::print(std::ostream &os, int verbosity,
169 const std::string &prefix) const
170{
171 ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
172 prefix, blkAddr, blkAddr + blkSize - 1,
173 isSecure ? "s" : "ns",
174 _isUncacheable ? "Unc" : "",
175 inService ? "InSvc" : "");
176
177 ccprintf(os, "%s Targets:\n", prefix);
178 targets.print(os, verbosity, prefix + " ");
179}
180
181std::string
183{
184 std::ostringstream str;
185 print(str);
186 return str.str();
187}
188
189} // namespace gem5
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
A basic cache interface.
Definition base.hh:100
bool sendWriteQueuePacket(WriteQueueEntry *wq_entry)
Similar to sendMSHR, but for a write-queue entry instead.
Definition base.cc:1985
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
bool isSecure() const
Definition packet.hh:836
bool isWrite() const
Definition packet.hh:594
bool trySatisfyFunctional(PacketPtr other)
Check a functional request against a memory value stored in another packet (i.e.
Definition packet.hh:1399
RequestPtr req
A pointer to the original request.
Definition packet.hh:377
bool isPrint() const
Definition packet.hh:623
bool matchBlockAddr(const Addr addr, const bool is_secure, const int blk_size) const
Check if packet corresponds to a given block-aligned address and address space.
Definition packet.cc:389
MemCmd cmd
The command field of the packet.
Definition packet.hh:372
bool isEviction() const
Definition packet.hh:610
A queue entry base class, to be used by both the MSHRs and write-queue entries.
bool _isUncacheable
True if the entry is uncacheable.
unsigned blkSize
Block size of the cache.
virtual bool matchBlockAddr(const Addr addr, const bool is_secure) const =0
Check if entry corresponds to the one being looked for.
Addr blkAddr
Block aligned address.
Counter order
Order number assigned to disambiguate writes and misses.
bool inService
True if the entry has been sent downstream.
bool isSecure
True if the entry targets the secure memory space.
Tick readyTime
Tick when ready to issue.
void print(std::ostream &os, int verbosity, const std::string &prefix) const
void add(PacketPtr pkt, Tick readyTime, Counter order)
bool matchBlockAddr(const Addr addr, const bool is_secure) const override
Check if entry corresponds to the one being looked for.
bool trySatisfyFunctional(PacketPtr pkt)
std::string print() const
A no-args wrapper of print(std::ostream...) meant to be invoked from DPRINTFs avoiding string overhea...
bool sendPacket(BaseCache &cache) override
Send this queue entry as a downstream packet, with the exact behaviour depending on the specific entr...
bool hasTargets() const
Returns true if there are targets left.
void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, Tick when_ready, Counter _order)
Allocate a miss to this entry.
TargetList targets
List of all requests that match the address.
void deallocate()
Mark this entry as free.
bool conflictAddr(const QueueEntry *entry) const override
Check if given entry's packets conflict with this' entries packets.
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition logging.hh:214
Declares a basic cache interface BaseCache.
Bitfield< 5 > t
Definition misc_types.hh:71
Bitfield< 17 > os
Definition misc.hh:838
Bitfield< 3 > addr
Definition types.hh:84
double Counter
All counters are of 64-bit values.
Definition types.hh:46
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
uint64_t Tick
Tick count type.
Definition types.hh:58
void ccprintf(cp::Print &print)
Definition cprintf.hh:130
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
Write queue entry.

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