gem5  v21.1.0.2
write_queue_entry.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2012-2013, 2015-2017 ARM Limited
3  * All rights reserved.
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
15  * Copyright (c) 2010 Advanced Micro Devices, Inc.
16  * All rights reserved.
17  *
18  * Redistribution and use in source and binary forms, with or without
19  * modification, are permitted provided that the following conditions are
20  * met: redistributions of source code must retain the above copyright
21  * notice, this list of conditions and the following disclaimer;
22  * redistributions in binary form must reproduce the above copyright
23  * notice, this list of conditions and the following disclaimer in the
24  * documentation and/or other materials provided with the distribution;
25  * neither the name of the copyright holders nor the names of its
26  * contributors may be used to endorse or promote products derived from
27  * this software without specific prior written permission.
28  *
29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40  */
41 
48 
49 #include <cassert>
50 #include <string>
51 
52 #include "base/logging.hh"
53 #include "base/types.hh"
54 #include "mem/cache/base.hh"
55 #include "mem/request.hh"
56 
57 namespace gem5
58 {
59 
60 inline void
62  Counter order)
63 {
64  emplace_back(pkt, readyTime, order);
65 }
66 
67 bool
69 {
70  for (auto& t : *this) {
71  if (pkt->trySatisfyFunctional(t.pkt)) {
72  return true;
73  }
74  }
75 
76  return false;
77 }
78 
79 void
80 WriteQueueEntry::TargetList::print(std::ostream &os, int verbosity,
81  const std::string &prefix) const
82 {
83  for (auto& t : *this) {
84  ccprintf(os, "%sFromCPU: ", prefix);
85  t.pkt->print(os, verbosity, "");
86  }
87 }
88 
89 void
90 WriteQueueEntry::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
91  Tick when_ready, Counter _order)
92 {
93  blkAddr = blk_addr;
94  blkSize = blk_size;
95  isSecure = target->isSecure();
96  readyTime = when_ready;
97  order = _order;
98  assert(target);
99  _isUncacheable = target->req->isUncacheable();
100  inService = false;
101 
102  // we should never have more than a single target for cacheable
103  // writes (writebacks and clean evictions)
104  panic_if(!_isUncacheable && !targets.empty(),
105  "Write queue entry %#llx should never have more than one "
106  "cacheable target", blkAddr);
107  panic_if(!((target->isWrite() && _isUncacheable) ||
108  (target->isEviction() && !_isUncacheable) ||
109  target->cmd == MemCmd::WriteClean),
110  "Write queue entry %#llx should be an uncacheable write or "
111  "a cacheable eviction or a writeclean");
112 
113  targets.add(target, when_ready, _order);
114 
115  // All targets must refer to the same block
116  assert(target->matchBlockAddr(targets.front().pkt, blkSize));
117 }
118 
119 void
121 {
122  assert(targets.empty());
123  inService = false;
124 }
125 
126 bool
128 {
129  // For printing, we treat the WriteQueueEntry as a whole as single
130  // entity. For other requests, we iterate over the individual
131  // targets since that's where the actual data lies.
132  if (pkt->isPrint()) {
133  pkt->trySatisfyFunctional(this, blkAddr, isSecure, blkSize, nullptr);
134  return false;
135  } else {
136  return targets.trySatisfyFunctional(pkt);
137  }
138 }
139 
140 bool
142 {
143  return cache.sendWriteQueuePacket(this);
144 }
145 
146 bool
147 WriteQueueEntry::matchBlockAddr(const Addr addr, const bool is_secure) const
148 {
149  assert(hasTargets());
150  return (blkAddr == addr) && (isSecure == is_secure);
151 }
152 
153 bool
155 {
156  assert(hasTargets());
157  return pkt->matchBlockAddr(blkAddr, isSecure, blkSize);
158 }
159 
160 bool
162 {
163  assert(hasTargets());
164  return entry->matchBlockAddr(blkAddr, isSecure);
165 }
166 
167 void
168 WriteQueueEntry::print(std::ostream &os, int verbosity,
169  const std::string &prefix) const
170 {
171  ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
172  prefix, blkAddr, blkAddr + blkSize - 1,
173  isSecure ? "s" : "ns",
174  _isUncacheable ? "Unc" : "",
175  inService ? "InSvc" : "");
176 
177  ccprintf(os, "%s Targets:\n", prefix);
178  targets.print(os, verbosity, prefix + " ");
179 }
180 
181 std::string
183 {
184  std::ostringstream str;
185  print(str);
186  return str.str();
187 }
188 
189 } // namespace gem5
base.hh
gem5::WriteQueueEntry::matchBlockAddr
bool matchBlockAddr(const Addr addr, const bool is_secure) const override
Check if entry corresponds to the one being looked for.
Definition: write_queue_entry.cc:147
gem5::WriteQueueEntry::sendPacket
bool sendPacket(BaseCache &cache) override
Send this queue entry as a downstream packet, with the exact behaviour depending on the specific entr...
Definition: write_queue_entry.cc:141
gem5::MemCmd::WriteClean
@ WriteClean
Definition: packet.hh:94
gem5::QueueEntry::_isUncacheable
bool _isUncacheable
True if the entry is uncacheable.
Definition: queue_entry.hh:77
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:583
gem5::Packet::isSecure
bool isSecure() const
Definition: packet.hh:810
gem5::QueueEntry::blkAddr
Addr blkAddr
Block aligned address.
Definition: queue_entry.hh:116
request.hh
gem5::QueueEntry::order
Counter order
Order number assigned to disambiguate writes and misses.
Definition: queue_entry.hh:113
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::WriteQueueEntry::targets
TargetList targets
List of all requests that match the address.
Definition: write_queue_entry.hh:112
gem5::QueueEntry::readyTime
Tick readyTime
Tick when ready to issue.
Definition: queue_entry.hh:74
gem5::BaseCache::sendWriteQueuePacket
bool sendWriteQueuePacket(WriteQueueEntry *wq_entry)
Similar to sendMSHR, but for a write-queue entry instead.
Definition: base.cc:1893
gem5::WriteQueueEntry::TargetList::print
void print(std::ostream &os, int verbosity, const std::string &prefix) const
Definition: write_queue_entry.cc:80
gem5::BaseCache
A basic cache interface.
Definition: base.hh:95
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Packet::matchBlockAddr
bool matchBlockAddr(const Addr addr, const bool is_secure, const int blk_size) const
Check if packet corresponds to a given block-aligned address and address space.
Definition: packet.cc:394
gem5::QueueEntry::matchBlockAddr
virtual bool matchBlockAddr(const Addr addr, const bool is_secure) const =0
Check if entry corresponds to the one being looked for.
gem5::WriteQueueEntry::print
std::string print() const
A no-args wrapper of print(std::ostream...) meant to be invoked from DPRINTFs avoiding string overhea...
Definition: write_queue_entry.cc:182
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::WriteQueueEntry::TargetList::add
void add(PacketPtr pkt, Tick readyTime, Counter order)
Definition: write_queue_entry.cc:61
gem5::QueueEntry::isSecure
bool isSecure
True if the entry targets the secure memory space.
Definition: queue_entry.hh:122
gem5::WriteQueueEntry::TargetList::trySatisfyFunctional
bool trySatisfyFunctional(PacketPtr pkt)
Definition: write_queue_entry.cc:68
gem5::WriteQueueEntry::allocate
void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, Tick when_ready, Counter _order)
Allocate a miss to this entry.
Definition: write_queue_entry.cc:90
gem5::Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:361
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:70
gem5::Packet::isPrint
bool isPrint() const
Definition: packet.hh:611
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::QueueEntry::blkSize
unsigned blkSize
Block size of the cache.
Definition: queue_entry.hh:119
gem5::WriteQueueEntry::trySatisfyFunctional
bool trySatisfyFunctional(PacketPtr pkt)
Definition: write_queue_entry.cc:127
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::WriteQueueEntry::deallocate
void deallocate()
Mark this entry as free.
Definition: write_queue_entry.cc:120
types.hh
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
logging.hh
gem5::QueueEntry
A queue entry base class, to be used by both the MSHRs and write-queue entries.
Definition: queue_entry.hh:62
gem5::Packet::trySatisfyFunctional
bool trySatisfyFunctional(PacketPtr other)
Check a functional request against a memory value stored in another packet (i.e.
Definition: packet.hh:1358
gem5::WriteQueueEntry::hasTargets
bool hasTargets() const
Returns true if there are targets left.
Definition: write_queue_entry.hh:149
gem5::WriteQueueEntry::conflictAddr
bool conflictAddr(const QueueEntry *entry) const override
Check if given entry's packets conflict with this' entries packets.
Definition: write_queue_entry.cc:161
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::QueueEntry::inService
bool inService
True if the entry has been sent downstream.
Definition: queue_entry.hh:110
write_queue_entry.hh
gem5::Packet::isEviction
bool isEviction() const
Definition: packet.hh:599
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

Generated on Tue Sep 21 2021 12:25:30 for gem5 by doxygen 1.8.17