gem5  v21.1.0.2
decoder.hh
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28 
29 #ifndef __ARCH_X86_DECODER_HH__
30 #define __ARCH_X86_DECODER_HH__
31 
32 #include <cassert>
33 #include <unordered_map>
34 #include <vector>
35 
36 #include "arch/generic/decoder.hh"
38 #include "arch/x86/regs/misc.hh"
39 #include "arch/x86/types.hh"
40 #include "base/bitfield.hh"
41 #include "base/logging.hh"
42 #include "base/trace.hh"
43 #include "base/types.hh"
44 #include "cpu/decode_cache.hh"
45 #include "cpu/static_inst.hh"
46 #include "debug/Decoder.hh"
47 
48 namespace gem5
49 {
50 
51 namespace X86ISA
52 {
53 
54 class ISA;
55 class Decoder : public InstDecoder
56 {
57  private:
58  // These are defined and documented in decoder_tables.cc
59  static const uint8_t SizeTypeToSize[3][10];
60  typedef const uint8_t ByteTable[256];
62 
67 
73 
75 
76  protected:
77  using MachInst = uint64_t;
78 
79  struct InstBytes
80  {
85 
87  {}
88  };
89 
90  static InstBytes dummy;
91 
92  // The bytes to be predecoded.
95  int chunkIdx;
96  // The pc of the start of fetchChunk.
97  Addr basePC = 0;
98  // The pc the current instruction started at.
99  Addr origPC = 0;
100  // The offset into fetchChunk of current processing.
101  int offset = 0;
102  // The extended machine instruction being generated.
104  // Predecoding state.
105  X86Mode mode = LongMode;
107  uint8_t altOp = 0;
108  uint8_t defOp = 0;
109  uint8_t altAddr = 0;
110  uint8_t defAddr = 0;
111  uint8_t stack = 0;
112 
113  uint8_t
115  {
116  return ((uint8_t *)&fetchChunk)[offset];
117  }
118 
119  void
120  getImmediate(int &collected, uint64_t &current, int size)
121  {
122  // Figure out how many bytes we still need to get for the
123  // immediate.
124  int toGet = size - collected;
125  // Figure out how many bytes are left in our "buffer".
126  int remaining = sizeof(MachInst) - offset;
127  // Get as much as we need, up to the amount available.
128  toGet = toGet > remaining ? remaining : toGet;
129 
130  // Shift the bytes we want to be all the way to the right
131  uint64_t partialImm = fetchChunk >> (offset * 8);
132  // Mask off what we don't want.
133  partialImm &= mask(toGet * 8);
134  // Shift it over to overlay with our displacement.
135  partialImm <<= (immediateCollected * 8);
136  // Put it into our displacement.
137  current |= partialImm;
138  // Update how many bytes we've collected.
139  collected += toGet;
140  consumeBytes(toGet);
141  }
142 
143  void
145  {
146  assert(offset <= sizeof(MachInst));
147  if (offset == sizeof(MachInst)) {
148  DPRINTF(Decoder, "At the end of a chunk, idx = %d, chunks = %d.\n",
149  chunkIdx, instBytes->chunks.size());
150  chunkIdx++;
151  if (chunkIdx == instBytes->chunks.size()) {
152  outOfBytes = true;
153  } else {
154  offset = 0;
156  basePC += sizeof(MachInst);
157  }
158  }
159  }
160 
161  void
163  {
164  offset++;
166  }
167 
168  void
169  consumeBytes(int numBytes)
170  {
171  offset += numBytes;
173  }
174 
175  // State machine state.
176  protected:
177  // Whether or not we're out of bytes.
178  bool outOfBytes = true;
179  // Whether we've completed generating an ExtMachInst.
180  bool instDone = false;
181  // The size of the displacement value.
183  // The size of the immediate value.
185  // This is how much of any immediate value we've gotten. This is used
186  // for both the actual immediate and the displacement.
188 
189  enum State
190  {
206  // We should never get to this state. Getting here is an error.
208  };
209 
211 
212  // Functions to handle each of the states
215  State doPrefixState(uint8_t);
216  State doVex2Of2State(uint8_t);
217  State doVex2Of3State(uint8_t);
218  State doVex3Of3State(uint8_t);
219  State doVexOpcodeState(uint8_t);
220  State doOneByteOpcodeState(uint8_t);
221  State doTwoByteOpcodeState(uint8_t);
224  State doModRMState(uint8_t);
225  State doSIBState(uint8_t);
228 
229  // Process the actual opcode found earlier, using the supplied tables.
230  State processOpcode(ByteTable &immTable, ByteTable &modrmTable,
231  bool addrSizedImm = false);
232  // Process the opcode found with VEX / XOP prefix.
234 
235  protected:
237 
238  typedef RegVal CacheKey;
239 
242  typedef std::unordered_map<CacheKey, DecodePages *> AddrCacheMap;
244 
246  typedef std::unordered_map<
249 
251 
256 
257  public:
258  Decoder(ISA *isa=nullptr) : InstDecoder(&fetchChunk)
259  {
260  emi.reset();
261  emi.mode.mode = mode;
262  emi.mode.submode = submode;
263  }
264 
265  void
266  setM5Reg(HandyM5Reg m5Reg)
267  {
268  mode = (X86Mode)(uint64_t)m5Reg.mode;
269  submode = (X86SubMode)(uint64_t)m5Reg.submode;
270  emi.mode.mode = mode;
271  emi.mode.submode = submode;
272  altOp = m5Reg.altOp;
273  defOp = m5Reg.defOp;
274  altAddr = m5Reg.altAddr;
275  defAddr = m5Reg.defAddr;
276  stack = m5Reg.stack;
277 
278  AddrCacheMap::iterator amIter = addrCacheMap.find(m5Reg);
279  if (amIter != addrCacheMap.end()) {
280  decodePages = amIter->second;
281  } else {
282  decodePages = new DecodePages;
283  addrCacheMap[m5Reg] = decodePages;
284  }
285 
286  InstCacheMap::iterator imIter = instCacheMap.find(m5Reg);
287  if (imIter != instCacheMap.end()) {
288  instMap = imIter->second;
289  } else {
291  instCacheMap[m5Reg] = instMap;
292  }
293  }
294 
295  void
297  {
298  mode = old->mode;
299  submode = old->submode;
300  emi.mode.mode = mode;
301  emi.mode.submode = submode;
302  altOp = old->altOp;
303  defOp = old->defOp;
304  altAddr = old->altAddr;
305  defAddr = old->defAddr;
306  stack = old->stack;
307  }
308 
309  void reset() { state = ResetState; }
310 
311  void process();
312 
313  // Use this to give data to the decoder. This should be used
314  // when there is control flow.
315  void
316  moreBytes(const PCState &pc, Addr fetchPC)
317  {
318  DPRINTF(Decoder, "Getting more bytes.\n");
319  basePC = fetchPC;
320  offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
322  outOfBytes = false;
323  process();
324  }
325 
326  bool needMoreBytes() { return outOfBytes; }
327  bool instReady() { return instDone; }
328 
329  void
331  {
332  if (!nextPC.size()) {
333  int size = basePC + offset - origPC;
335  "Calculating the instruction size: "
336  "basePC: %#x offset: %#x origPC: %#x size: %d\n",
337  basePC, offset, origPC, size);
338  nextPC.size(size);
339  nextPC.npc(nextPC.pc() + size);
340  }
341  }
342 
343  public:
345 
347  MicroPC micropc, StaticInstPtr curMacroop) override;
348 };
349 
350 } // namespace X86ISA
351 } // namespace gem5
352 
353 #endif // __ARCH_X86_DECODER_HH__
gem5::X86ISA::Decoder::Vex2Of3State
@ Vex2Of3State
Definition: decoder.hh:195
gem5::X86ISA::mask
mask
Definition: misc.hh:802
gem5::X86ISA::Decoder::instReady
bool instReady()
Definition: decoder.hh:327
gem5::X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:811
gem5::X86ISA::Decoder::doImmediateState
State doImmediateState()
Definition: decoder.cc:636
gem5::X86ISA::Decoder::ImmediateTypeOneByte
static ByteTable ImmediateTypeOneByte
Definition: decoder.hh:68
gem5::X86ISA::Decoder::setM5Reg
void setM5Reg(HandyM5Reg m5Reg)
Definition: decoder.hh:266
gem5::X86ISA::Decoder::altAddr
uint8_t altAddr
Definition: decoder.hh:109
gem5::X86ISA::Decoder::reset
void reset()
Definition: decoder.hh:309
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::GenericISA::SimplePCState::npc
Addr npc() const
Definition: types.hh:154
gem5::X86ISA::Decoder::doSIBState
State doSIBState(uint8_t)
Definition: decoder.cc:568
gem5::X86ISA::Decoder::InstCacheMap
std::unordered_map< CacheKey, decode_cache::InstMap< ExtMachInst > * > InstCacheMap
Definition: decoder.hh:247
gem5::X86ISA::Decoder::VexOpcodeState
@ VexOpcodeState
Definition: decoder.hh:197
gem5::X86ISA::Decoder::Decoder
Decoder(ISA *isa=nullptr)
Definition: decoder.hh:258
gem5::X86ISA::Decoder::microcodeRom
static X86ISAInst::MicrocodeRom microcodeRom
Definition: decoder.hh:74
gem5::X86ISA::Decoder::immediateSize
int immediateSize
Definition: decoder.hh:184
gem5::X86ISA::ISA
Definition: isa.hh:50
gem5::X86ISA::Decoder::consumeByte
void consumeByte()
Definition: decoder.hh:162
gem5::decode_cache::InstMap
std::unordered_map< EMI, StaticInstPtr > InstMap
Hash for decoded instructions.
Definition: decode_cache.hh:47
gem5::X86ISA::Decoder::outOfBytes
bool outOfBytes
Definition: decoder.hh:178
gem5::X86ISA::Decoder::TwoByteOpcodeState
@ TwoByteOpcodeState
Definition: decoder.hh:199
gem5::X86ISA::Decoder::DisplacementState
@ DisplacementState
Definition: decoder.hh:204
gem5::X86ISA::Decoder::doVex3Of3State
State doVex3Of3State(uint8_t)
Definition: decoder.cc:319
gem5::X86ISA::Decoder::UsesModRMThreeByte0F38
static ByteTable UsesModRMThreeByte0F38
Definition: decoder.hh:65
gem5::X86ISA::ExtMachInst::mode
OperatingMode mode
Definition: types.hh:239
gem5::X86ISA::Decoder::DecodePages
decode_cache::AddrMap< Decoder::InstBytes > DecodePages
Definition: decoder.hh:240
gem5::X86ISA::Decoder::stack
uint8_t stack
Definition: decoder.hh:111
gem5::X86ISA::Decoder::ImmediateTypeVex
static ByteTable ImmediateTypeVex[10]
Definition: decoder.hh:72
microcode_rom.hh
gem5::X86ISA::Decoder::Prefixes
static ByteTable Prefixes
Definition: decoder.hh:61
gem5::X86ISA::Decoder::instMap
decode_cache::InstMap< ExtMachInst > * instMap
Definition: decoder.hh:245
gem5::X86ISA::Decoder::defOp
uint8_t defOp
Definition: decoder.hh:108
gem5::X86ISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:103
std::vector< MachInst >
gem5::X86ISA::SixtyFourBitMode
@ SixtyFourBitMode
Definition: types.hh:198
gem5::X86ISA::Decoder::ImmediateTypeTwoByte
static ByteTable ImmediateTypeTwoByte
Definition: decoder.hh:69
gem5::X86ISA::Decoder::decodeInst
StaticInstPtr decodeInst(ExtMachInst mach_inst)
gem5::X86ISA::Decoder::ImmediateTypeThreeByte0F3A
static ByteTable ImmediateTypeThreeByte0F3A
Definition: decoder.hh:71
gem5::X86ISA::Decoder::PrefixState
@ PrefixState
Definition: decoder.hh:193
gem5::X86ISA::Decoder::State
State
Definition: decoder.hh:189
gem5::X86ISA::Decoder::doModRMState
State doModRMState(uint8_t)
Definition: decoder.cc:513
gem5::X86ISAInst::MicrocodeRom
Definition: microcode_rom.hh:42
gem5::X86ISA::Decoder::offset
int offset
Definition: decoder.hh:101
gem5::X86ISA::Decoder::origPC
Addr origPC
Definition: decoder.hh:99
gem5::X86ISA::Decoder::fetchChunk
MachInst fetchChunk
Definition: decoder.hh:93
gem5::RefCountingPtr< StaticInst >
gem5::letoh
T letoh(T value)
Definition: byteswap.hh:173
gem5::X86ISA::Decoder::ByteTable
const typedef uint8_t ByteTable[256]
Definition: decoder.hh:60
gem5::X86ISA::Decoder::doVexOpcodeState
State doVexOpcodeState(uint8_t)
Definition: decoder.cc:356
gem5::X86ISA::X86SubMode
X86SubMode
Definition: types.hh:196
gem5::X86ISA::ExtMachInst::reset
void reset()
Definition: types.hh:208
gem5::X86ISA::Decoder::getNextByte
uint8_t getNextByte()
Definition: decoder.hh:114
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::X86ISA::Decoder::instBytes
InstBytes * instBytes
Definition: decoder.hh:94
gem5::X86ISA::Decoder::Vex2Of2State
@ Vex2Of2State
Definition: decoder.hh:194
gem5::X86ISA::Decoder::doFromCacheState
State doFromCacheState()
Definition: decoder.cc:148
gem5::X86ISA::Decoder::UsesModRMOneByte
static ByteTable UsesModRMOneByte
Definition: decoder.hh:63
decoder.hh
gem5::X86ISA::Decoder::instCacheMap
static InstCacheMap instCacheMap
Definition: decoder.hh:248
gem5::X86ISA::Decoder::ImmediateState
@ ImmediateState
Definition: decoder.hh:205
bitfield.hh
gem5::X86ISA::Decoder::basePC
Addr basePC
Definition: decoder.hh:97
gem5::X86ISA::Decoder::InstBytes::masks
std::vector< MachInst > masks
Definition: decoder.hh:83
gem5::X86ISA::Decoder::processExtendedOpcode
State processExtendedOpcode(ByteTable &immTable)
gem5::InstDecoder
Definition: decoder.hh:39
gem5::X86ISA::Decoder::chunkIdx
int chunkIdx
Definition: decoder.hh:95
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::X86ISA::Decoder::ErrorState
@ ErrorState
Definition: decoder.hh:207
gem5::X86ISA::Decoder::needMoreBytes
bool needMoreBytes()
Definition: decoder.hh:326
gem5::X86ISA::Decoder::SIBState
@ SIBState
Definition: decoder.hh:203
gem5::X86ISA::Decoder::OneByteOpcodeState
@ OneByteOpcodeState
Definition: decoder.hh:198
gem5::X86ISA::Decoder::decodePages
DecodePages * decodePages
Definition: decoder.hh:241
gem5::X86ISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.cc:679
gem5::decode_cache::AddrMap
A sparse map from an Addr to a Value, stored in page chunks.
Definition: decode_cache.hh:51
gem5::X86ISA::Decoder::updateOffsetState
void updateOffsetState()
Definition: decoder.hh:144
gem5::X86ISA::Decoder::doVex2Of2State
State doVex2Of2State(uint8_t)
Definition: decoder.cc:248
gem5::X86ISA::Decoder::altOp
uint8_t altOp
Definition: decoder.hh:107
gem5::X86ISA::Decoder::instDone
bool instDone
Definition: decoder.hh:180
gem5::X86ISA::Decoder::immediateCollected
int immediateCollected
Definition: decoder.hh:187
gem5::X86ISA::Decoder
Definition: decoder.hh:55
gem5::X86ISA::Decoder::InstBytes::si
StaticInstPtr si
Definition: decoder.hh:81
gem5::X86ISA::Decoder::doResetState
State doResetState()
Definition: decoder.cc:47
static_inst.hh
gem5::X86ISA::Decoder::doDisplacementState
State doDisplacementState()
Definition: decoder.cc:589
gem5::X86ISA::PCState::size
uint8_t size() const
Definition: pcstate.hh:75
gem5::X86ISA::Decoder::consumeBytes
void consumeBytes(int numBytes)
Definition: decoder.hh:169
gem5::X86ISA::Decoder::InstBytes::lastOffset
int lastOffset
Definition: decoder.hh:84
gem5::X86ISA::Decoder::dummy
static InstBytes dummy
Definition: decoder.hh:90
gem5::X86ISA::Decoder::Vex3Of3State
@ Vex3Of3State
Definition: decoder.hh:196
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::Decoder::doOneByteOpcodeState
State doOneByteOpcodeState(uint8_t)
Definition: decoder.cc:380
gem5::X86ISA::Decoder::processOpcode
State processOpcode(ByteTable &immTable, ByteTable &modrmTable, bool addrSizedImm=false)
Definition: decoder.cc:453
gem5::X86ISA::Decoder::CacheKey
RegVal CacheKey
Caching for decoded instruction objects.
Definition: decoder.hh:238
gem5::X86ISA::Decoder::submode
X86SubMode submode
Definition: decoder.hh:106
gem5::X86ISA::Decoder::fetchRomMicroop
StaticInstPtr fetchRomMicroop(MicroPC micropc, StaticInstPtr curMacroop) override
Definition: decoder.cc:741
gem5::X86ISA::Decoder::AddrCacheMap
std::unordered_map< CacheKey, DecodePages * > AddrCacheMap
Definition: decoder.hh:242
gem5::X86ISA::Decoder::doThreeByte0F3AOpcodeState
State doThreeByte0F3AOpcodeState(uint8_t)
Definition: decoder.cc:439
gem5::X86ISA::Decoder::MachInst
uint64_t MachInst
Definition: decoder.hh:77
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::X86ISA::Decoder::FromCacheState
@ FromCacheState
Definition: decoder.hh:192
gem5::X86ISA::Decoder::doVex2Of3State
State doVex2Of3State(uint8_t)
Definition: decoder.cc:278
types.hh
gem5::X86ISA::Decoder::process
void process()
Definition: decoder.cc:78
gem5::X86ISA::Decoder::updateNPC
void updateNPC(X86ISA::PCState &nextPC)
Definition: decoder.hh:330
gem5::X86ISA::Decoder::defAddr
uint8_t defAddr
Definition: decoder.hh:110
gem5::X86ISA::PCState
Definition: pcstate.hh:50
decode_cache.hh
gem5::X86ISA::Decoder::addrCacheMap
AddrCacheMap addrCacheMap
Definition: decoder.hh:243
gem5::X86ISA::Decoder::doThreeByte0F38OpcodeState
State doThreeByte0F38OpcodeState(uint8_t)
Definition: decoder.cc:425
logging.hh
gem5::X86ISA::Decoder::SizeTypeToSize
static const uint8_t SizeTypeToSize[3][10]
Definition: decoder.hh:59
gem5::X86ISA::Decoder::doTwoByteOpcodeState
State doTwoByteOpcodeState(uint8_t)
Definition: decoder.cc:402
trace.hh
gem5::X86ISA::Decoder::state
State state
Definition: decoder.hh:210
gem5::X86ISA::Decoder::InstBytes::InstBytes
InstBytes()
Definition: decoder.hh:86
gem5::X86ISA::Decoder::takeOverFrom
void takeOverFrom(Decoder *old)
Definition: decoder.hh:296
gem5::X86ISA::Decoder::displacementSize
int displacementSize
Definition: decoder.hh:182
gem5::X86ISA::Decoder::moreBytes
void moreBytes(const PCState &pc, Addr fetchPC)
Definition: decoder.hh:316
gem5::X86ISA::Decoder::ThreeByte0F3AOpcodeState
@ ThreeByte0F3AOpcodeState
Definition: decoder.hh:201
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
misc.hh
gem5::X86ISA::Decoder::InstBytes::chunks
std::vector< MachInst > chunks
Definition: decoder.hh:82
gem5::X86ISA::Decoder::getImmediate
void getImmediate(int &collected, uint64_t &current, int size)
Definition: decoder.hh:120
types.hh
gem5::GenericISA::SimplePCState::pc
Addr pc() const
Definition: types.hh:151
gem5::X86ISA::Decoder::ThreeByte0F38OpcodeState
@ ThreeByte0F38OpcodeState
Definition: decoder.hh:200
gem5::X86ISA::Decoder::InstBytes
Definition: decoder.hh:79
gem5::X86ISA::Decoder::ImmediateTypeThreeByte0F38
static ByteTable ImmediateTypeThreeByte0F38
Definition: decoder.hh:70
gem5::X86ISA::Decoder::UsesModRMTwoByte
static ByteTable UsesModRMTwoByte
Definition: decoder.hh:64
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::X86ISA::Decoder::UsesModRMThreeByte0F3A
static ByteTable UsesModRMThreeByte0F3A
Definition: decoder.hh:66
gem5::X86ISA::Decoder::mode
X86Mode mode
Definition: decoder.hh:105
gem5::X86ISA::Decoder::doPrefixState
State doPrefixState(uint8_t)
Definition: decoder.cc:182
gem5::X86ISA::Decoder::ModRMState
@ ModRMState
Definition: decoder.hh:202
gem5::X86ISA::Decoder::ResetState
@ ResetState
Definition: decoder.hh:191

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