gem5 v24.0.0.0
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types.hh File Reference
#include <cstdint>
#include <functional>
#include <iostream>
#include "arch/x86/pcstate.hh"
#include "base/bitunion.hh"
#include "base/cprintf.hh"

Go to the source code of this file.

Classes

struct  gem5::X86ISA::ExtMachInst
 
struct  std::hash< gem5::X86ISA::ExtMachInst >
 

Namespaces

namespace  gem5
 Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
 
namespace  gem5::X86ISA
 This is exposed globally, independent of the ISA.
 
namespace  std
 Overload hash function for BasicBlockRange type.
 

Typedefs

typedef uint64_t gem5::X86ISA::MachInst
 

Enumerations

enum  gem5::X86ISA::Prefixes {
  gem5::X86ISA::NoOverride , gem5::X86ISA::ESOverride , gem5::X86ISA::CSOverride , gem5::X86ISA::SSOverride ,
  gem5::X86ISA::DSOverride , gem5::X86ISA::FSOverride , gem5::X86ISA::GSOverride , gem5::X86ISA::RexPrefix ,
  gem5::X86ISA::OperandSizeOverride , gem5::X86ISA::AddressSizeOverride , gem5::X86ISA::Lock , gem5::X86ISA::Rep ,
  gem5::X86ISA::Repne , gem5::X86ISA::Vex2Prefix , gem5::X86ISA::Vex3Prefix , gem5::X86ISA::XopPrefix
}
 
enum  gem5::X86ISA::X86SubMode {
  gem5::X86ISA::SixtyFourBitMode , gem5::X86ISA::CompatabilityMode , gem5::X86ISA::ProtectedMode , gem5::X86ISA::Virtual8086Mode ,
  gem5::X86ISA::RealMode
}
 

Functions

 gem5::X86ISA::BitUnion8 (LegacyPrefixVector) Bitfield< 7
 
 gem5::X86ISA::EndBitUnion (LegacyPrefixVector) BitUnion8(ModRM) Bitfield< 7
 
 gem5::X86ISA::EndBitUnion (ModRM) BitUnion8(Sib) Bitfield< 7
 
 gem5::X86ISA::EndBitUnion (Sib) BitUnion8(Rex) Bitfield< 6 > present
 
 gem5::X86ISA::EndBitUnion (Rex) BitUnion8(Vex2Of3) Bitfield< 7 > r
 
 gem5::X86ISA::EndBitUnion (Vex2Of3) BitUnion8(Vex3Of3) Bitfield< 7 > w
 
 gem5::X86ISA::EndBitUnion (Vex3Of3) BitUnion8(Vex2Of2) Bitfield< 7 > r
 
 gem5::X86ISA::EndBitUnion (Vex2Of2) BitUnion8(VexInfo) Bitfield< 6
 
 gem5::X86ISA::EndBitUnion (VexInfo) enum OpcodeType
 
static const char * gem5::X86ISA::opcodeTypeToStr (OpcodeType type)
 
 gem5::X86ISA::BitUnion8 (Opcode) Bitfield< 7
 
 gem5::X86ISA::EndBitUnion (Opcode) BitUnion8(OperatingMode) Bitfield< 3 > mode
 
 gem5::X86ISA::EndBitUnion (OperatingMode) BitUnion8(OperatingModeAndCPL) Bitfield< 5
 
 gem5::X86ISA::EndBitUnion (OperatingModeAndCPL) enum X86Mode
 
static std::ostream & gem5::X86ISA::operator<< (std::ostream &os, const ExtMachInst &emi)
 
static bool gem5::X86ISA::operator== (const ExtMachInst &emi1, const ExtMachInst &emi2)
 
template<>
void gem5::paramOut (CheckpointOut &cp, const std::string &name, const X86ISA::ExtMachInst &machInst)
 
template<>
void gem5::paramIn (CheckpointIn &cp, const std::string &name, X86ISA::ExtMachInst &machInst)
 

Variables

 gem5::X86ISA::decodeVal
 
Bitfield< 7 > gem5::X86ISA::repne
 
Bitfield< 6 > gem5::X86ISA::rep
 
Bitfield< 5 > gem5::X86ISA::lock
 
Bitfield< 4 > gem5::X86ISA::op
 
Bitfield< 3 > gem5::X86ISA::addr
 
Bitfield< 2, 0 > gem5::X86ISA::seg
 
 gem5::X86ISA::mod
 
Bitfield< 5, 3 > gem5::X86ISA::reg
 
Bitfield< 2, 0 > gem5::X86ISA::rm
 
 gem5::X86ISA::scale
 
Bitfield< 5, 3 > gem5::X86ISA::index
 
Bitfield< 1 > gem5::X86ISA::x
 
Bitfield< 4, 0 > gem5::X86ISA::m
 
Bitfield< 6, 3 > gem5::X86ISA::v
 
 gem5::X86ISA::top5
 
Bitfield< 2, 0 > gem5::X86ISA::bottom3
 
Bitfield< 3 > gem5::X86ISA::mode
 

Generated on Tue Jun 18 2024 16:24:08 for gem5 by doxygen 1.11.0