gem5  v21.1.0.2
decoder.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2011 Google
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include "arch/x86/decoder.hh"
30 
31 #include "arch/x86/regs/misc.hh"
32 #include "base/logging.hh"
33 #include "base/trace.hh"
34 #include "base/types.hh"
35 #include "debug/Decode.hh"
36 #include "debug/Decoder.hh"
37 
38 namespace gem5
39 {
40 
41 namespace X86ISA
42 {
43 
44 X86ISAInst::MicrocodeRom Decoder::microcodeRom;
45 
48 {
49  origPC = basePC + offset;
50  DPRINTF(Decoder, "Setting origPC to %#x\n", origPC);
52  chunkIdx = 0;
53 
54  emi.rex = 0;
55  emi.legacy = 0;
56  emi.vex = 0;
57 
58  emi.opcode.type = BadOpcode;
59  emi.opcode.op = 0;
60 
62  emi.immediate = 0;
63  emi.displacement = 0;
64  emi.dispSize = 0;
65 
66  emi.modRM = 0;
67  emi.sib = 0;
68 
69  if (instBytes->si) {
70  return FromCacheState;
71  } else {
72  instBytes->chunks.clear();
73  return PrefixState;
74  }
75 }
76 
77 void
79 {
80  // This function drives the decoder state machine.
81 
82  // Some sanity checks. You shouldn't try to process more bytes if
83  // there aren't any, and you shouldn't overwrite an already decoded
84  // ExtMachInst.
85  assert(!outOfBytes);
86  assert(!instDone);
87 
88  if (state == ResetState)
89  state = doResetState();
90  if (state == FromCacheState) {
92  } else {
93  instBytes->chunks.push_back(fetchChunk);
94  }
95 
96  // While there's still something to do...
97  while (!instDone && !outOfBytes) {
98  uint8_t nextByte = getNextByte();
99  switch (state) {
100  case PrefixState:
101  state = doPrefixState(nextByte);
102  break;
103  case Vex2Of2State:
104  state = doVex2Of2State(nextByte);
105  break;
106  case Vex2Of3State:
107  state = doVex2Of3State(nextByte);
108  break;
109  case Vex3Of3State:
110  state = doVex3Of3State(nextByte);
111  break;
112  case VexOpcodeState:
113  state = doVexOpcodeState(nextByte);
114  break;
115  case OneByteOpcodeState:
116  state = doOneByteOpcodeState(nextByte);
117  break;
118  case TwoByteOpcodeState:
119  state = doTwoByteOpcodeState(nextByte);
120  break;
122  state = doThreeByte0F38OpcodeState(nextByte);
123  break;
125  state = doThreeByte0F3AOpcodeState(nextByte);
126  break;
127  case ModRMState:
128  state = doModRMState(nextByte);
129  break;
130  case SIBState:
131  state = doSIBState(nextByte);
132  break;
133  case DisplacementState:
135  break;
136  case ImmediateState:
138  break;
139  case ErrorState:
140  panic("Went to the error state in the decoder.\n");
141  default:
142  panic("Unrecognized state! %d\n", state);
143  }
144  }
145 }
146 
149 {
150  DPRINTF(Decoder, "Looking at cache state.\n");
151  if ((fetchChunk & instBytes->masks[chunkIdx]) !=
153  DPRINTF(Decoder, "Decode cache miss.\n");
154  // The chached chunks didn't match what was fetched. Fall back to the
155  // predecoder.
157  instBytes->chunks.resize(chunkIdx + 1);
158  instBytes->si = NULL;
159  chunkIdx = 0;
161  offset = origPC % sizeof(MachInst);
162  basePC = origPC - offset;
163  return PrefixState;
164  } else if (chunkIdx == instBytes->chunks.size() - 1) {
165  // We matched the cache, so use its value.
166  instDone = true;
168  if (offset == sizeof(MachInst))
169  outOfBytes = true;
170  return ResetState;
171  } else {
172  // We matched so far, but need to check more chunks.
173  chunkIdx++;
174  outOfBytes = true;
175  return FromCacheState;
176  }
177 }
178 
179 // Either get a prefix and record it in the ExtMachInst, or send the
180 // state machine on to get the opcode(s).
182 Decoder::doPrefixState(uint8_t nextByte)
183 {
184  uint8_t prefix = Prefixes[nextByte];
185  State nextState = PrefixState;
186  // REX prefixes are only recognized in 64 bit mode.
187  if (prefix == RexPrefix && emi.mode.submode != SixtyFourBitMode)
188  prefix = 0;
189  if (prefix)
190  consumeByte();
191  switch(prefix) {
192  // Operand size override prefixes
193  case OperandSizeOverride:
194  DPRINTF(Decoder, "Found operand size override prefix.\n");
195  emi.legacy.op = true;
196  break;
197  case AddressSizeOverride:
198  DPRINTF(Decoder, "Found address size override prefix.\n");
199  emi.legacy.addr = true;
200  break;
201  // Segment override prefixes
202  case CSOverride:
203  case DSOverride:
204  case ESOverride:
205  case FSOverride:
206  case GSOverride:
207  case SSOverride:
208  DPRINTF(Decoder, "Found segment override.\n");
209  emi.legacy.seg = prefix;
210  break;
211  case Lock:
212  DPRINTF(Decoder, "Found lock prefix.\n");
213  emi.legacy.lock = true;
214  break;
215  case Rep:
216  DPRINTF(Decoder, "Found rep prefix.\n");
217  emi.legacy.rep = true;
218  break;
219  case Repne:
220  DPRINTF(Decoder, "Found repne prefix.\n");
221  emi.legacy.repne = true;
222  break;
223  case RexPrefix:
224  DPRINTF(Decoder, "Found Rex prefix %#x.\n", nextByte);
225  emi.rex = nextByte;
226  break;
227  case Vex2Prefix:
228  DPRINTF(Decoder, "Found VEX two-byte prefix %#x.\n", nextByte);
229  emi.vex.present = 1;
230  nextState = Vex2Of2State;
231  break;
232  case Vex3Prefix:
233  DPRINTF(Decoder, "Found VEX three-byte prefix %#x.\n", nextByte);
234  emi.vex.present = 1;
235  nextState = Vex2Of3State;
236  break;
237  case 0:
238  nextState = OneByteOpcodeState;
239  break;
240 
241  default:
242  panic("Unrecognized prefix %#x\n", nextByte);
243  }
244  return nextState;
245 }
246 
248 Decoder::doVex2Of2State(uint8_t nextByte)
249 {
250  consumeByte();
251  Vex2Of2 vex = nextByte;
252 
253  emi.rex.r = !vex.r;
254 
255  emi.vex.l = vex.l;
256  emi.vex.v = ~vex.v;
257 
258  switch (vex.p) {
259  case 0:
260  break;
261  case 1:
262  emi.legacy.op = 1;
263  break;
264  case 2:
265  emi.legacy.rep = 1;
266  break;
267  case 3:
268  emi.legacy.repne = 1;
269  break;
270  }
271 
272  emi.opcode.type = TwoByteOpcode;
273 
274  return VexOpcodeState;
275 }
276 
278 Decoder::doVex2Of3State(uint8_t nextByte)
279 {
280  if (emi.mode.submode != SixtyFourBitMode && bits(nextByte, 7, 6) == 0x3) {
281  // This was actually an LDS instruction. Reroute to that path.
282  emi.vex.present = 0;
283  emi.opcode.type = OneByteOpcode;
284  emi.opcode.op = 0xC4;
286  nextByte >= 0xA0 && nextByte <= 0xA3);
287  }
288 
289  consumeByte();
290  Vex2Of3 vex = nextByte;
291 
292  emi.rex.r = !vex.r;
293  emi.rex.x = !vex.x;
294  emi.rex.b = !vex.b;
295 
296  switch (vex.m) {
297  case 1:
298  emi.opcode.type = TwoByteOpcode;
299  break;
300  case 2:
301  emi.opcode.type = ThreeByte0F38Opcode;
302  break;
303  case 3:
304  emi.opcode.type = ThreeByte0F3AOpcode;
305  break;
306  default:
307  // These encodings are reserved. Pretend this was an undefined
308  // instruction so the main decoder will behave correctly, and stop
309  // trying to interpret bytes.
310  emi.opcode.type = TwoByteOpcode;
311  emi.opcode.op = 0x0B;
312  instDone = true;
313  return ResetState;
314  }
315  return Vex3Of3State;
316 }
317 
319 Decoder::doVex3Of3State(uint8_t nextByte)
320 {
321  if (emi.mode.submode != SixtyFourBitMode && bits(nextByte, 7, 6) == 0x3) {
322  // This was actually an LES instruction. Reroute to that path.
323  emi.vex.present = 0;
324  emi.opcode.type = OneByteOpcode;
325  emi.opcode.op = 0xC5;
327  nextByte >= 0xA0 && nextByte <= 0xA3);
328  }
329 
330  consumeByte();
331  Vex3Of3 vex = nextByte;
332 
333  emi.rex.w = vex.w;
334 
335  emi.vex.l = vex.l;
336  emi.vex.v = ~vex.v;
337 
338  switch (vex.p) {
339  case 0:
340  break;
341  case 1:
342  emi.legacy.op = 1;
343  break;
344  case 2:
345  emi.legacy.rep = 1;
346  break;
347  case 3:
348  emi.legacy.repne = 1;
349  break;
350  }
351 
352  return VexOpcodeState;
353 }
354 
356 Decoder::doVexOpcodeState(uint8_t nextByte)
357 {
358  DPRINTF(Decoder, "Found VEX opcode %#x.\n", nextByte);
359 
360  emi.opcode.op = nextByte;
361  consumeByte();
362 
363  switch (emi.opcode.type) {
364  case TwoByteOpcode:
366  case ThreeByte0F38Opcode:
369  case ThreeByte0F3AOpcode:
372  default:
373  panic("Unrecognized opcode type %d.\n", emi.opcode.type);
374  }
375 }
376 
377 // Load the first opcode byte. Determine if there are more opcode bytes, and
378 // if not, what immediate and/or ModRM is needed.
381 {
382  State nextState = ErrorState;
383  consumeByte();
384 
385  if (nextByte == 0x0f) {
386  DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
387  nextState = TwoByteOpcodeState;
388  } else {
389  DPRINTF(Decoder, "Found one byte opcode %#x.\n", nextByte);
390  emi.opcode.type = OneByteOpcode;
391  emi.opcode.op = nextByte;
392 
394  nextByte >= 0xA0 && nextByte <= 0xA3);
395  }
396  return nextState;
397 }
398 
399 // Load the second opcode byte. Determine if there are more opcode bytes, and
400 // if not, what immediate and/or ModRM is needed.
403 {
404  State nextState = ErrorState;
405  consumeByte();
406  if (nextByte == 0x38) {
407  nextState = ThreeByte0F38OpcodeState;
408  DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
409  } else if (nextByte == 0x3a) {
410  nextState = ThreeByte0F3AOpcodeState;
411  DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
412  } else {
413  DPRINTF(Decoder, "Found two byte opcode %#x.\n", nextByte);
414  emi.opcode.type = TwoByteOpcode;
415  emi.opcode.op = nextByte;
416 
418  }
419  return nextState;
420 }
421 
422 // Load the third opcode byte and determine what immediate and/or ModRM is
423 // needed.
426 {
427  consumeByte();
428 
429  DPRINTF(Decoder, "Found three byte 0F38 opcode %#x.\n", nextByte);
430  emi.opcode.type = ThreeByte0F38Opcode;
431  emi.opcode.op = nextByte;
432 
434 }
435 
436 // Load the third opcode byte and determine what immediate and/or ModRM is
437 // needed.
440 {
441  consumeByte();
442 
443  DPRINTF(Decoder, "Found three byte 0F3A opcode %#x.\n", nextByte);
444  emi.opcode.type = ThreeByte0F3AOpcode;
445  emi.opcode.op = nextByte;
446 
448 }
449 
450 // Generic opcode processing which determines the immediate size, and whether
451 // or not there's a modrm byte.
453 Decoder::processOpcode(ByteTable &immTable, ByteTable &modrmTable,
454  bool addrSizedImm)
455 {
456  State nextState = ErrorState;
457  const uint8_t opcode = emi.opcode.op;
458 
459  // Figure out the effective operand size. This can be overriden to
460  // a fixed value at the decoder level.
461  int logOpSize;
462  if (emi.rex.w)
463  logOpSize = 3; // 64 bit operand size
464  else if (emi.legacy.op)
465  logOpSize = altOp;
466  else
467  logOpSize = defOp;
468 
469  // Set the actual op size.
470  emi.opSize = 1 << logOpSize;
471 
472  // Figure out the effective address size. This can be overriden to
473  // a fixed value at the decoder level.
474  int logAddrSize;
475  if (emi.legacy.addr)
476  logAddrSize = altAddr;
477  else
478  logAddrSize = defAddr;
479 
480  // Set the actual address size.
481  emi.addrSize = 1 << logAddrSize;
482 
483  // Figure out the effective stack width. This can be overriden to
484  // a fixed value at the decoder level.
485  emi.stackSize = 1 << stack;
486 
487  // Figure out how big of an immediate we'll retreive based
488  // on the opcode.
489  int immType = immTable[opcode];
490  if (addrSizedImm)
491  immediateSize = SizeTypeToSize[logAddrSize - 1][immType];
492  else
493  immediateSize = SizeTypeToSize[logOpSize - 1][immType];
494 
495  // Determine what to expect next.
496  if (modrmTable[opcode]) {
497  nextState = ModRMState;
498  } else {
499  if (immediateSize) {
500  nextState = ImmediateState;
501  } else {
502  instDone = true;
503  nextState = ResetState;
504  }
505  }
506  return nextState;
507 }
508 
509 // Get the ModRM byte and determine what displacement, if any, there is.
510 // Also determine whether or not to get the SIB byte, displacement, or
511 // immediate next.
513 Decoder::doModRMState(uint8_t nextByte)
514 {
515  State nextState = ErrorState;
516  ModRM modRM = nextByte;
517  DPRINTF(Decoder, "Found modrm byte %#x.\n", nextByte);
518  if (defOp == 1) {
519  // Figure out 16 bit displacement size.
520  if ((modRM.mod == 0 && modRM.rm == 6) || modRM.mod == 2)
521  displacementSize = 2;
522  else if (modRM.mod == 1)
523  displacementSize = 1;
524  else
525  displacementSize = 0;
526  } else {
527  // Figure out 32/64 bit displacement size.
528  if ((modRM.mod == 0 && modRM.rm == 5) || modRM.mod == 2)
529  displacementSize = 4;
530  else if (modRM.mod == 1)
531  displacementSize = 1;
532  else
533  displacementSize = 0;
534  }
535 
536  // The "test" instruction in group 3 needs an immediate, even though
537  // the other instructions with the same actual opcode don't.
538  if (emi.opcode.type == OneByteOpcode && (modRM.reg & 0x6) == 0) {
539  if (emi.opcode.op == 0xF6)
540  immediateSize = 1;
541  else if (emi.opcode.op == 0xF7)
542  immediateSize = (emi.opSize == 8) ? 4 : emi.opSize;
543  }
544 
545  // If there's an SIB, get that next.
546  // There is no SIB in 16 bit mode.
547  if (modRM.rm == 4 && modRM.mod != 3) {
548  // && in 32/64 bit mode)
549  nextState = SIBState;
550  } else if (displacementSize) {
551  nextState = DisplacementState;
552  } else if (immediateSize) {
553  nextState = ImmediateState;
554  } else {
555  instDone = true;
556  nextState = ResetState;
557  }
558  // The ModRM byte is consumed no matter what.
559  consumeByte();
560  emi.modRM = modRM;
561  return nextState;
562 }
563 
564 // Get the SIB byte. We don't do anything with it at this point, other
565 // than storing it in the ExtMachInst. Determine if we need to get a
566 // displacement or immediate next.
568 Decoder::doSIBState(uint8_t nextByte)
569 {
570  State nextState = ErrorState;
571  emi.sib = nextByte;
572  DPRINTF(Decoder, "Found SIB byte %#x.\n", nextByte);
573  consumeByte();
574  if (emi.modRM.mod == 0 && emi.sib.base == 5)
575  displacementSize = 4;
576  if (displacementSize) {
577  nextState = DisplacementState;
578  } else if (immediateSize) {
579  nextState = ImmediateState;
580  } else {
581  instDone = true;
582  nextState = ResetState;
583  }
584  return nextState;
585 }
586 
587 // Gather up the displacement, or at least as much of it as we can get.
590 {
591  State nextState = ErrorState;
592 
596 
597  DPRINTF(Decoder, "Collecting %d byte displacement, got %d bytes.\n",
599 
601  // Reset this for other immediates.
602  immediateCollected = 0;
603  // Sign extend the displacement.
604  switch(displacementSize)
605  {
606  case 1:
607  emi.displacement = sext<8>(emi.displacement);
608  break;
609  case 2:
610  emi.displacement = sext<16>(emi.displacement);
611  break;
612  case 4:
613  emi.displacement = sext<32>(emi.displacement);
614  break;
615  default:
616  panic("Undefined displacement size!\n");
617  }
618  DPRINTF(Decoder, "Collected displacement %#x.\n",
619  emi.displacement);
620  if (immediateSize) {
621  nextState = ImmediateState;
622  } else {
623  instDone = true;
624  nextState = ResetState;
625  }
626 
628  }
629  else
630  nextState = DisplacementState;
631  return nextState;
632 }
633 
634 // Gather up the immediate, or at least as much of it as we can get.
637 {
638  State nextState = ErrorState;
639 
641 
642  DPRINTF(Decoder, "Collecting %d byte immediate, got %d bytes.\n",
644 
646  // Reset this for other immediates.
647  immediateCollected = 0;
648 
649  //XXX Warning! The following is an observed pattern and might
650  // not always be true!
651 
652  // Instructions which use 64 bit operands but 32 bit immediates
653  // need to have the immediate sign extended to 64 bits.
654  // Instructions which use true 64 bit immediates won't be
655  // affected, and instructions that use true 32 bit immediates
656  // won't notice.
657  switch(immediateSize) {
658  case 4:
659  emi.immediate = sext<32>(emi.immediate);
660  break;
661  case 1:
662  emi.immediate = sext<8>(emi.immediate);
663  }
664 
665  DPRINTF(Decoder, "Collected immediate %#x.\n",
666  emi.immediate);
667  instDone = true;
668  nextState = ResetState;
669  } else {
670  nextState = ImmediateState;
671  }
672  return nextState;
673 }
674 
677 
680 {
682 
683  auto iter = instMap->find(mach_inst);
684  if (iter != instMap->end()) {
685  si = iter->second;
686  } else {
687  si = decodeInst(mach_inst);
688  (*instMap)[mach_inst] = si;
689  }
690 
691  DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
692  si->getName(), mach_inst);
693  return si;
694 }
695 
698 {
699  if (!instDone)
700  return NULL;
701  instDone = false;
702  updateNPC(nextPC);
703 
705  if (si)
706  return si;
707 
708  // We didn't match in the AddrMap, but we still populated an entry. Fix
709  // up its byte masks.
710  const int chunkSize = sizeof(MachInst);
711 
713 
714  Addr firstBasePC = basePC - (instBytes->chunks.size() - 1) * chunkSize;
715  Addr firstOffset = origPC - firstBasePC;
716  Addr totalSize = instBytes->lastOffset - firstOffset +
717  (instBytes->chunks.size() - 1) * chunkSize;
718  int start = firstOffset;
719  instBytes->masks.clear();
720 
721  while (totalSize) {
722  int end = start + totalSize;
723  end = (chunkSize < end) ? chunkSize : end;
724  int size = end - start;
725  int idx = instBytes->masks.size();
726 
727  MachInst maskVal = mask(size * 8) << (start * 8);
728  assert(maskVal);
729 
730  instBytes->masks.push_back(maskVal);
731  instBytes->chunks[idx] &= instBytes->masks[idx];
732  totalSize -= size;
733  start = 0;
734  }
735 
736  si = decode(emi, origPC);
737  return si;
738 }
739 
742 {
743  return microcodeRom.fetchMicroop(micropc, curMacroop);
744 }
745 
746 } // namespace X86ISA
747 } // namespace gem5
gem5::X86ISA::Decoder::Vex2Of3State
@ Vex2Of3State
Definition: decoder.hh:195
gem5::X86ISA::mask
mask
Definition: misc.hh:802
gem5::X86ISA::Repne
@ Repne
Definition: types.hh:72
gem5::X86ISA::Decoder::doImmediateState
State doImmediateState()
Definition: decoder.cc:636
gem5::X86ISA::FSOverride
@ FSOverride
Definition: types.hh:65
gem5::X86ISA::Decoder::ImmediateTypeOneByte
static ByteTable ImmediateTypeOneByte
Definition: decoder.hh:68
gem5::X86ISA::ExtMachInst::op
Opcode op
Definition: types.hh:220
gem5::X86ISA::Rep
@ Rep
Definition: types.hh:71
gem5::X86ISA::Decoder::altAddr
uint8_t altAddr
Definition: decoder.hh:109
gem5::X86ISA::Decoder::doSIBState
State doSIBState(uint8_t)
Definition: decoder.cc:568
gem5::X86ISA::Decoder::InstCacheMap
std::unordered_map< CacheKey, decode_cache::InstMap< ExtMachInst > * > InstCacheMap
Definition: decoder.hh:247
gem5::X86ISA::ESOverride
@ ESOverride
Definition: types.hh:61
gem5::X86ISA::Vex2Prefix
@ Vex2Prefix
Definition: types.hh:73
gem5::X86ISA::Decoder::VexOpcodeState
@ VexOpcodeState
Definition: decoder.hh:197
gem5::X86ISA::Decoder::microcodeRom
static X86ISAInst::MicrocodeRom microcodeRom
Definition: decoder.hh:74
gem5::X86ISA::Decoder::immediateSize
int immediateSize
Definition: decoder.hh:184
gem5::X86ISAInst::MicrocodeRom::fetchMicroop
StaticInstPtr fetchMicroop(MicroPC microPC, StaticInstPtr curMacroop)
Definition: microcode_rom.hh:63
gem5::X86ISA::CSOverride
@ CSOverride
Definition: types.hh:62
gem5::X86ISA::Decoder::consumeByte
void consumeByte()
Definition: decoder.hh:162
gem5::X86ISA::ExtMachInst::modRM
ModRM modRM
Definition: types.hh:223
gem5::X86ISA::Decoder::outOfBytes
bool outOfBytes
Definition: decoder.hh:178
gem5::X86ISA::Decoder::TwoByteOpcodeState
@ TwoByteOpcodeState
Definition: decoder.hh:199
gem5::X86ISA::SSOverride
@ SSOverride
Definition: types.hh:63
gem5::X86ISA::Decoder::DisplacementState
@ DisplacementState
Definition: decoder.hh:204
gem5::X86ISA::Decoder::doVex3Of3State
State doVex3Of3State(uint8_t)
Definition: decoder.cc:319
gem5::X86ISA::Decoder::UsesModRMThreeByte0F38
static ByteTable UsesModRMThreeByte0F38
Definition: decoder.hh:65
gem5::X86ISA::ExtMachInst::opSize
uint8_t opSize
Definition: types.hh:230
gem5::X86ISA::ExtMachInst::mode
OperatingMode mode
Definition: types.hh:239
gem5::X86ISA::Decoder::stack
uint8_t stack
Definition: decoder.hh:111
gem5::X86ISA::Decoder::instMap
decode_cache::InstMap< ExtMachInst > * instMap
Definition: decoder.hh:245
gem5::X86ISA::Decoder::defOp
uint8_t defOp
Definition: decoder.hh:108
gem5::X86ISA::AddressSizeOverride
@ AddressSizeOverride
Definition: types.hh:69
gem5::X86ISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:103
gem5::X86ISA::ExtMachInst::opcode
struct gem5::X86ISA::ExtMachInst::@19 opcode
gem5::X86ISA::ExtMachInst::stackSize
uint8_t stackSize
Definition: types.hh:234
gem5::X86ISA::GSOverride
@ GSOverride
Definition: types.hh:66
gem5::X86ISA::SixtyFourBitMode
@ SixtyFourBitMode
Definition: types.hh:198
gem5::X86ISA::Decoder::ImmediateTypeTwoByte
static ByteTable ImmediateTypeTwoByte
Definition: decoder.hh:69
gem5::X86ISA::Decoder::decodeInst
StaticInstPtr decodeInst(ExtMachInst mach_inst)
gem5::X86ISA::Decoder::ImmediateTypeThreeByte0F3A
static ByteTable ImmediateTypeThreeByte0F3A
Definition: decoder.hh:71
gem5::X86ISA::Decoder::PrefixState
@ PrefixState
Definition: decoder.hh:193
gem5::X86ISA::Decoder::State
State
Definition: decoder.hh:189
gem5::X86ISA::Decoder::doModRMState
State doModRMState(uint8_t)
Definition: decoder.cc:513
gem5::X86ISA::OperandSizeOverride
@ OperandSizeOverride
Definition: types.hh:68
decoder.hh
gem5::X86ISA::Decoder::offset
int offset
Definition: decoder.hh:101
gem5::X86ISA::Decoder::origPC
Addr origPC
Definition: decoder.hh:99
gem5::X86ISA::Decoder::fetchChunk
MachInst fetchChunk
Definition: decoder.hh:93
gem5::RefCountingPtr
If you want a reference counting pointer to a mutable object, create it like this:
Definition: refcnt.hh:126
gem5::X86ISA::Decoder::doVexOpcodeState
State doVexOpcodeState(uint8_t)
Definition: decoder.cc:356
gem5::X86ISA::Decoder::getNextByte
uint8_t getNextByte()
Definition: decoder.hh:114
gem5::X86ISA::ExtMachInst::rex
Rex rex
Definition: types.hh:212
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::X86ISA::Decoder::instBytes
InstBytes * instBytes
Definition: decoder.hh:94
gem5::X86ISA::Decoder::Vex2Of2State
@ Vex2Of2State
Definition: decoder.hh:194
gem5::X86ISA::Decoder::doFromCacheState
State doFromCacheState()
Definition: decoder.cc:148
gem5::X86ISA::ExtMachInst::type
OpcodeType type
Definition: types.hh:218
gem5::X86ISA::Decoder::UsesModRMOneByte
static ByteTable UsesModRMOneByte
Definition: decoder.hh:63
gem5::ArmISA::opcode
Bitfield< 24, 21 > opcode
Definition: types.hh:92
gem5::X86ISA::Decoder::instCacheMap
static InstCacheMap instCacheMap
Definition: decoder.hh:248
gem5::X86ISA::DSOverride
@ DSOverride
Definition: types.hh:64
gem5::X86ISA::Decoder::ImmediateState
@ ImmediateState
Definition: decoder.hh:205
gem5::X86ISA::ExtMachInst::legacy
LegacyPrefixVector legacy
Definition: types.hh:211
gem5::X86ISA::Decoder::basePC
Addr basePC
Definition: decoder.hh:97
gem5::X86ISA::Decoder::InstBytes::masks
std::vector< MachInst > masks
Definition: decoder.hh:83
gem5::X86ISA::Prefixes
Prefixes
Definition: types.hh:58
gem5::X86ISA::Decoder::chunkIdx
int chunkIdx
Definition: decoder.hh:95
gem5::X86ISA::ExtMachInst::vex
VexInfo vex
Definition: types.hh:213
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::X86ISA::Decoder::ErrorState
@ ErrorState
Definition: decoder.hh:207
gem5::X86ISA::Decoder::SIBState
@ SIBState
Definition: decoder.hh:203
gem5::X86ISA::Decoder::OneByteOpcodeState
@ OneByteOpcodeState
Definition: decoder.hh:198
gem5::X86ISA::Decoder::decodePages
DecodePages * decodePages
Definition: decoder.hh:241
gem5::X86ISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.cc:679
gem5::X86ISA::ExtMachInst::addrSize
uint8_t addrSize
Definition: types.hh:232
gem5::X86ISA::Decoder::doVex2Of2State
State doVex2Of2State(uint8_t)
Definition: decoder.cc:248
gem5::X86ISA::Decoder::altOp
uint8_t altOp
Definition: decoder.hh:107
gem5::X86ISA::Decoder::instDone
bool instDone
Definition: decoder.hh:180
gem5::X86ISA::Decoder::immediateCollected
int immediateCollected
Definition: decoder.hh:187
gem5::X86ISA::Decoder
Definition: decoder.hh:55
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::X86ISA::Decoder::InstBytes::si
StaticInstPtr si
Definition: decoder.hh:81
gem5::X86ISA::Decoder::doResetState
State doResetState()
Definition: decoder.cc:47
gem5::X86ISA::Decoder::doDisplacementState
State doDisplacementState()
Definition: decoder.cc:589
gem5::X86ISA::Decoder::InstBytes::lastOffset
int lastOffset
Definition: decoder.hh:84
gem5::X86ISA::Decoder::dummy
static InstBytes dummy
Definition: decoder.hh:90
gem5::X86ISA::Decoder::Vex3Of3State
@ Vex3Of3State
Definition: decoder.hh:196
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::RexPrefix
@ RexPrefix
Definition: types.hh:67
gem5::X86ISA::Decoder::doOneByteOpcodeState
State doOneByteOpcodeState(uint8_t)
Definition: decoder.cc:380
gem5::X86ISA::Decoder::processOpcode
State processOpcode(ByteTable &immTable, ByteTable &modrmTable, bool addrSizedImm=false)
Definition: decoder.cc:453
gem5::X86ISA::si
Bitfield< 15, 3 > si
Definition: misc.hh:866
gem5::X86ISA::ExtMachInst::dispSize
uint8_t dispSize
Definition: types.hh:236
gem5::X86ISA::Decoder::fetchRomMicroop
StaticInstPtr fetchRomMicroop(MicroPC micropc, StaticInstPtr curMacroop) override
Definition: decoder.cc:741
gem5::X86ISA::Decoder::doThreeByte0F3AOpcodeState
State doThreeByte0F3AOpcodeState(uint8_t)
Definition: decoder.cc:439
gem5::X86ISA::ExtMachInst::sib
Sib sib
Definition: types.hh:224
gem5::X86ISA::Decoder::MachInst
uint64_t MachInst
Definition: decoder.hh:77
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::X86ISA::ExtMachInst::displacement
uint64_t displacement
Definition: types.hh:227
gem5::X86ISA::ExtMachInst::immediate
uint64_t immediate
Definition: types.hh:226
gem5::X86ISA::Decoder::FromCacheState
@ FromCacheState
Definition: decoder.hh:192
gem5::X86ISA::Decoder::doVex2Of3State
State doVex2Of3State(uint8_t)
Definition: decoder.cc:278
gem5::X86ISA::Vex3Prefix
@ Vex3Prefix
Definition: types.hh:74
types.hh
gem5::X86ISA::Decoder::process
void process()
Definition: decoder.cc:78
gem5::X86ISA::Decoder::updateNPC
void updateNPC(X86ISA::PCState &nextPC)
Definition: decoder.hh:330
gem5::X86ISA::Decoder::defAddr
uint8_t defAddr
Definition: decoder.hh:110
gem5::X86ISA::PCState
Definition: pcstate.hh:50
gem5::X86ISA::Decoder::doThreeByte0F38OpcodeState
State doThreeByte0F38OpcodeState(uint8_t)
Definition: decoder.cc:425
logging.hh
gem5::X86ISA::Decoder::SizeTypeToSize
static const uint8_t SizeTypeToSize[3][10]
Definition: decoder.hh:59
gem5::X86ISA::Decoder::doTwoByteOpcodeState
State doTwoByteOpcodeState(uint8_t)
Definition: decoder.cc:402
trace.hh
gem5::X86ISA::Lock
@ Lock
Definition: types.hh:70
gem5::X86ISA::Decoder::state
State state
Definition: decoder.hh:210
gem5::X86ISA::Decoder::displacementSize
int displacementSize
Definition: decoder.hh:182
gem5::decode_cache::AddrMap::lookup
Value & lookup(Addr addr)
Definition: decode_cache.hh:132
gem5::X86ISA::Decoder::ThreeByte0F3AOpcodeState
@ ThreeByte0F3AOpcodeState
Definition: decoder.hh:201
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
misc.hh
gem5::X86ISA::Decoder::InstBytes::chunks
std::vector< MachInst > chunks
Definition: decoder.hh:82
gem5::X86ISA::Decoder::getImmediate
void getImmediate(int &collected, uint64_t &current, int size)
Definition: decoder.hh:120
gem5::X86ISA::Decoder::ThreeByte0F38OpcodeState
@ ThreeByte0F38OpcodeState
Definition: decoder.hh:200
gem5::X86ISA::Decoder::InstBytes
Definition: decoder.hh:79
gem5::X86ISA::Decoder::ImmediateTypeThreeByte0F38
static ByteTable ImmediateTypeThreeByte0F38
Definition: decoder.hh:70
gem5::X86ISA::Decoder::UsesModRMTwoByte
static ByteTable UsesModRMTwoByte
Definition: decoder.hh:64
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::X86ISA::Decoder::UsesModRMThreeByte0F3A
static ByteTable UsesModRMThreeByte0F3A
Definition: decoder.hh:66
gem5::X86ISA::Decoder::doPrefixState
State doPrefixState(uint8_t)
Definition: decoder.cc:182
gem5::X86ISA::Decoder::ModRMState
@ ModRMState
Definition: decoder.hh:202
gem5::X86ISA::Decoder::ResetState
@ ResetState
Definition: decoder.hh:191

Generated on Tue Sep 21 2021 12:23:59 for gem5 by doxygen 1.8.17