gem5 v24.1.0.1
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decoder.cc
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1/*
2 * Copyright (c) 2011 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/x86/decoder.hh"
30
31#include "arch/x86/regs/misc.hh"
32#include "base/logging.hh"
33#include "base/trace.hh"
34#include "base/types.hh"
35#include "debug/Decode.hh"
36#include "debug/Decoder.hh"
37
38namespace gem5
39{
40
41namespace X86ISA
42{
43
46{
48 DPRINTF(Decoder, "Setting origPC to %#x\n", origPC);
50 chunkIdx = 0;
51
52 emi.rex = 0;
53 emi.legacy = 0;
54 emi.vex = 0;
55
56 emi.opcode.type = BadOpcode;
57 emi.opcode.op = 0;
58
60 emi.immediate = 0;
61 emi.displacement = 0;
62 emi.dispSize = 0;
63
64 emi.modRM = 0;
65 emi.sib = 0;
66
67 if (instBytes->si) {
68 return FromCacheState;
69 } else {
70 instBytes->chunks.clear();
71 return PrefixState;
72 }
73}
74
75void
77{
78 // This function drives the decoder state machine.
79
80 // Some sanity checks. You shouldn't try to process more bytes if
81 // there aren't any, and you shouldn't overwrite an already decoded
82 // ExtMachInst.
83 assert(!outOfBytes);
84 assert(!instDone);
85
86 if (state == ResetState)
88 if (state == FromCacheState) {
90 } else {
91 instBytes->chunks.push_back(fetchChunk);
92 }
93
94 // While there's still something to do...
95 while (!instDone && !outOfBytes) {
96 uint8_t nextByte = getNextByte();
97 switch (state) {
98 case PrefixState:
99 state = doPrefixState(nextByte);
100 break;
101 case Vex2Of2State:
102 state = doVex2Of2State(nextByte);
103 break;
104 case Vex2Of3State:
105 state = doVex2Of3State(nextByte);
106 break;
107 case Vex3Of3State:
108 state = doVex3Of3State(nextByte);
109 break;
110 case VexOpcodeState:
111 state = doVexOpcodeState(nextByte);
112 break;
114 state = doOneByteOpcodeState(nextByte);
115 break;
117 state = doTwoByteOpcodeState(nextByte);
118 break;
121 break;
124 break;
125 case ModRMState:
126 state = doModRMState(nextByte);
127 break;
128 case SIBState:
129 state = doSIBState(nextByte);
130 break;
133 break;
134 case ImmediateState:
136 break;
137 case ErrorState:
138 panic("Went to the error state in the decoder.\n");
139 default:
140 panic("Unrecognized state! %d\n", state);
141 }
142 }
143}
144
147{
148 DPRINTF(Decoder, "Looking at cache state.\n");
151 DPRINTF(Decoder, "Decode cache miss.\n");
152 // The chached chunks didn't match what was fetched. Fall back to the
153 // predecoder.
155 instBytes->chunks.resize(chunkIdx + 1);
156 instBytes->si = NULL;
157 chunkIdx = 0;
159 offset = origPC % sizeof(MachInst);
160 basePC = origPC - offset;
161 return PrefixState;
162 } else if (chunkIdx == instBytes->chunks.size() - 1) {
163 // We matched the cache, so use its value.
164 instDone = true;
166 if (offset == sizeof(MachInst))
167 outOfBytes = true;
168 return ResetState;
169 } else {
170 // We matched so far, but need to check more chunks.
171 chunkIdx++;
172 outOfBytes = true;
173 return FromCacheState;
174 }
175}
176
177// Either get a prefix and record it in the ExtMachInst, or send the
178// state machine on to get the opcode(s).
180Decoder::doPrefixState(uint8_t nextByte)
181{
182 // The REX and VEX prefixes only exist in 64 bit mode, so we use a
183 // different table for that.
184 const int table_idx = emi.mode.submode == SixtyFourBitMode ? 1 : 0;
185 const uint8_t prefix = Prefixes[table_idx][nextByte];
186 State nextState = PrefixState;
187 if (prefix)
188 consumeByte();
189 switch(prefix) {
190 // Operand size override prefixes
192 DPRINTF(Decoder, "Found operand size override prefix.\n");
193 emi.legacy.op = true;
194 break;
196 DPRINTF(Decoder, "Found address size override prefix.\n");
197 emi.legacy.addr = true;
198 break;
199 // Segment override prefixes
200 case CSOverride:
201 case DSOverride:
202 case ESOverride:
203 case FSOverride:
204 case GSOverride:
205 case SSOverride:
206 DPRINTF(Decoder, "Found segment override.\n");
207 emi.legacy.seg = prefix;
208 break;
209 case Lock:
210 DPRINTF(Decoder, "Found lock prefix.\n");
211 emi.legacy.lock = true;
212 break;
213 case Rep:
214 DPRINTF(Decoder, "Found rep prefix.\n");
215 emi.legacy.rep = true;
216 break;
217 case Repne:
218 DPRINTF(Decoder, "Found repne prefix.\n");
219 emi.legacy.repne = true;
220 break;
221 case RexPrefix:
222 DPRINTF(Decoder, "Found Rex prefix %#x.\n", nextByte);
223 emi.rex = nextByte;
224 break;
225 case Vex2Prefix:
226 DPRINTF(Decoder, "Found VEX two-byte prefix %#x.\n", nextByte);
227 emi.vex.present = 1;
228 nextState = Vex2Of2State;
229 break;
230 case Vex3Prefix:
231 DPRINTF(Decoder, "Found VEX three-byte prefix %#x.\n", nextByte);
232 emi.vex.present = 1;
233 nextState = Vex2Of3State;
234 break;
235 case 0:
236 nextState = OneByteOpcodeState;
237 break;
238
239 default:
240 panic("Unrecognized prefix %#x\n", nextByte);
241 }
242 return nextState;
243}
244
246Decoder::doVex2Of2State(uint8_t nextByte)
247{
248 consumeByte();
249 Vex2Of2 vex = nextByte;
250
251 emi.rex.r = !vex.r;
252
253 emi.vex.l = vex.l;
254 emi.vex.v = ~vex.v;
255
256 switch (vex.p) {
257 case 0:
258 break;
259 case 1:
260 emi.legacy.op = 1;
261 break;
262 case 2:
263 emi.legacy.rep = 1;
264 break;
265 case 3:
266 emi.legacy.repne = 1;
267 break;
268 }
269
270 emi.opcode.type = TwoByteOpcode;
271
272 return VexOpcodeState;
273}
274
276Decoder::doVex2Of3State(uint8_t nextByte)
277{
278 if (emi.mode.submode != SixtyFourBitMode && bits(nextByte, 7, 6) == 0x3) {
279 // This was actually an LDS instruction. Reroute to that path.
280 emi.vex.present = 0;
281 emi.opcode.type = OneByteOpcode;
282 emi.opcode.op = 0xC4;
284 nextByte >= 0xA0 && nextByte <= 0xA3);
285 }
286
287 consumeByte();
288 Vex2Of3 vex = nextByte;
289
290 emi.rex.r = !vex.r;
291 emi.rex.x = !vex.x;
292 emi.rex.b = !vex.b;
293
294 switch (vex.m) {
295 case 1:
296 emi.opcode.type = TwoByteOpcode;
297 break;
298 case 2:
299 emi.opcode.type = ThreeByte0F38Opcode;
300 break;
301 case 3:
302 emi.opcode.type = ThreeByte0F3AOpcode;
303 break;
304 default:
305 // These encodings are reserved. Pretend this was an undefined
306 // instruction so the main decoder will behave correctly, and stop
307 // trying to interpret bytes.
308 emi.opcode.type = TwoByteOpcode;
309 emi.opcode.op = 0x0B;
310 instDone = true;
311 return ResetState;
312 }
313 return Vex3Of3State;
314}
315
317Decoder::doVex3Of3State(uint8_t nextByte)
318{
319 if (emi.mode.submode != SixtyFourBitMode && bits(nextByte, 7, 6) == 0x3) {
320 // This was actually an LES instruction. Reroute to that path.
321 emi.vex.present = 0;
322 emi.opcode.type = OneByteOpcode;
323 emi.opcode.op = 0xC5;
325 nextByte >= 0xA0 && nextByte <= 0xA3);
326 }
327
328 consumeByte();
329 Vex3Of3 vex = nextByte;
330
331 emi.rex.w = vex.w;
332
333 emi.vex.l = vex.l;
334 emi.vex.v = ~vex.v;
335
336 switch (vex.p) {
337 case 0:
338 break;
339 case 1:
340 emi.legacy.op = 1;
341 break;
342 case 2:
343 emi.legacy.rep = 1;
344 break;
345 case 3:
346 emi.legacy.repne = 1;
347 break;
348 }
349
350 return VexOpcodeState;
351}
352
355{
356 DPRINTF(Decoder, "Found VEX opcode %#x.\n", nextByte);
357
358 emi.opcode.op = nextByte;
359 consumeByte();
360
361 switch (emi.opcode.type) {
362 case TwoByteOpcode:
364 case ThreeByte0F38Opcode:
367 case ThreeByte0F3AOpcode:
370 default:
371 panic("Unrecognized opcode type %d.\n", emi.opcode.type);
372 }
373}
374
375// Load the first opcode byte. Determine if there are more opcode bytes, and
376// if not, what immediate and/or ModRM is needed.
379{
380 State nextState = ErrorState;
381 consumeByte();
382
383 if (nextByte == 0x0f) {
384 DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
385 nextState = TwoByteOpcodeState;
386 } else {
387 DPRINTF(Decoder, "Found one byte opcode %#x.\n", nextByte);
388 emi.opcode.type = OneByteOpcode;
389 emi.opcode.op = nextByte;
390
392 nextByte >= 0xA0 && nextByte <= 0xA3);
393 }
394 return nextState;
395}
396
397// Load the second opcode byte. Determine if there are more opcode bytes, and
398// if not, what immediate and/or ModRM is needed.
401{
402 State nextState = ErrorState;
403 consumeByte();
404 if (nextByte == 0x38) {
405 nextState = ThreeByte0F38OpcodeState;
406 DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
407 } else if (nextByte == 0x3a) {
408 nextState = ThreeByte0F3AOpcodeState;
409 DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
410 } else {
411 DPRINTF(Decoder, "Found two byte opcode %#x.\n", nextByte);
412 emi.opcode.type = TwoByteOpcode;
413 emi.opcode.op = nextByte;
414
416 }
417 return nextState;
418}
419
420// Load the third opcode byte and determine what immediate and/or ModRM is
421// needed.
424{
425 consumeByte();
426
427 DPRINTF(Decoder, "Found three byte 0F38 opcode %#x.\n", nextByte);
428 emi.opcode.type = ThreeByte0F38Opcode;
429 emi.opcode.op = nextByte;
430
432}
433
434// Load the third opcode byte and determine what immediate and/or ModRM is
435// needed.
438{
439 consumeByte();
440
441 DPRINTF(Decoder, "Found three byte 0F3A opcode %#x.\n", nextByte);
442 emi.opcode.type = ThreeByte0F3AOpcode;
443 emi.opcode.op = nextByte;
444
446}
447
448// Generic opcode processing which determines the immediate size, and whether
449// or not there's a modrm byte.
451Decoder::processOpcode(ByteTable &immTable, ByteTable &modrmTable,
452 bool addrSizedImm)
453{
454 State nextState = ErrorState;
455 const uint8_t opcode = emi.opcode.op;
456
457 // Figure out the effective operand size. This can be overriden to
458 // a fixed value at the decoder level.
459 int logOpSize;
460 if (emi.rex.w)
461 logOpSize = 3; // 64 bit operand size
462 else if (emi.legacy.op)
463 logOpSize = altOp;
464 else
465 logOpSize = defOp;
466
467 // Set the actual op size.
468 emi.opSize = 1 << logOpSize;
469
470 // Figure out the effective address size. This can be overriden to
471 // a fixed value at the decoder level.
472 int logAddrSize;
473 if (emi.legacy.addr)
474 logAddrSize = altAddr;
475 else
476 logAddrSize = defAddr;
477
478 // Set the actual address size.
479 emi.addrSize = 1 << logAddrSize;
480
481 // Figure out the effective stack width. This can be overriden to
482 // a fixed value at the decoder level.
483 emi.stackSize = 1 << stack;
484
485 // Figure out how big of an immediate we'll retreive based
486 // on the opcode.
487 int immType = immTable[opcode];
488 if (addrSizedImm)
489 immediateSize = SizeTypeToSize[logAddrSize - 1][immType];
490 else
491 immediateSize = SizeTypeToSize[logOpSize - 1][immType];
492
493 // Determine what to expect next.
494 if (modrmTable[opcode]) {
495 nextState = ModRMState;
496 } else {
497 if (immediateSize) {
498 nextState = ImmediateState;
499 } else {
500 instDone = true;
501 nextState = ResetState;
502 }
503 }
504 return nextState;
505}
506
507// Get the ModRM byte and determine what displacement, if any, there is.
508// Also determine whether or not to get the SIB byte, displacement, or
509// immediate next.
511Decoder::doModRMState(uint8_t nextByte)
512{
513 State nextState = ErrorState;
514 ModRM modRM = nextByte;
515 DPRINTF(Decoder, "Found modrm byte %#x.\n", nextByte);
516 if (emi.addrSize == 2) {
517 // Figure out 16 bit displacement size.
518 if ((modRM.mod == 0 && modRM.rm == 6) || modRM.mod == 2)
520 else if (modRM.mod == 1)
522 else
524 } else {
525 // Figure out 32/64 bit displacement size.
526 if ((modRM.mod == 0 && modRM.rm == 5) || modRM.mod == 2)
528 else if (modRM.mod == 1)
530 else
532 }
533
534 // The "test" instruction in group 3 needs an immediate, even though
535 // the other instructions with the same actual opcode don't.
536 if (emi.opcode.type == OneByteOpcode && (modRM.reg & 0x6) == 0) {
537 if (emi.opcode.op == 0xF6)
538 immediateSize = 1;
539 else if (emi.opcode.op == 0xF7)
540 immediateSize = (emi.opSize == 8) ? 4 : emi.opSize;
541 }
542
543 // If there's an SIB, get that next.
544 // There is no SIB in 16 bit mode.
545 if (modRM.rm == 4 && modRM.mod != 3 && emi.addrSize != 2) {
546 nextState = SIBState;
547 } else if (displacementSize) {
548 nextState = DisplacementState;
549 } else if (immediateSize) {
550 nextState = ImmediateState;
551 } else {
552 instDone = true;
553 nextState = ResetState;
554 }
555 // The ModRM byte is consumed no matter what.
556 consumeByte();
557 emi.modRM = modRM;
558 return nextState;
559}
560
561// Get the SIB byte. We don't do anything with it at this point, other
562// than storing it in the ExtMachInst. Determine if we need to get a
563// displacement or immediate next.
565Decoder::doSIBState(uint8_t nextByte)
566{
567 State nextState = ErrorState;
568 emi.sib = nextByte;
569 DPRINTF(Decoder, "Found SIB byte %#x.\n", nextByte);
570 consumeByte();
571 if (emi.modRM.mod == 0 && emi.sib.base == 5)
573 if (displacementSize) {
574 nextState = DisplacementState;
575 } else if (immediateSize) {
576 nextState = ImmediateState;
577 } else {
578 instDone = true;
579 nextState = ResetState;
580 }
581 return nextState;
582}
583
584// Gather up the displacement, or at least as much of it as we can get.
587{
588 State nextState = ErrorState;
589
593
594 DPRINTF(Decoder, "Collecting %d byte displacement, got %d bytes.\n",
596
598 // Reset this for other immediates.
600 // Sign extend the displacement.
601 switch(displacementSize)
602 {
603 case 1:
604 emi.displacement = sext<8>(emi.displacement);
605 break;
606 case 2:
607 emi.displacement = sext<16>(emi.displacement);
608 break;
609 case 4:
610 emi.displacement = sext<32>(emi.displacement);
611 break;
612 default:
613 panic("Undefined displacement size!\n");
614 }
615 DPRINTF(Decoder, "Collected displacement %#x.\n",
617 if (immediateSize) {
618 nextState = ImmediateState;
619 } else {
620 instDone = true;
621 nextState = ResetState;
622 }
623
625 }
626 else
627 nextState = DisplacementState;
628 return nextState;
629}
630
631// Gather up the immediate, or at least as much of it as we can get.
634{
635 State nextState = ErrorState;
636
638
639 DPRINTF(Decoder, "Collecting %d byte immediate, got %d bytes.\n",
641
643 // Reset this for other immediates.
645
646 //XXX Warning! The following is an observed pattern and might
647 // not always be true!
648
649 // Instructions which use 64 bit operands but 32 bit immediates
650 // need to have the immediate sign extended to 64 bits.
651 // Instructions which use true 64 bit immediates won't be
652 // affected, and instructions that use true 32 bit immediates
653 // won't notice.
654 switch(immediateSize) {
655 case 4:
656 emi.immediate = sext<32>(emi.immediate);
657 break;
658 case 1:
659 emi.immediate = sext<8>(emi.immediate);
660 }
661
662 DPRINTF(Decoder, "Collected immediate %#x.\n",
663 emi.immediate);
664 instDone = true;
665 nextState = ResetState;
666 } else {
667 nextState = ImmediateState;
668 }
669 return nextState;
670}
671
674{
676
677 auto iter = instMap->find(mach_inst);
678 if (iter != instMap->end()) {
679 si = iter->second;
680 } else {
681 si = decodeInst(mach_inst);
682 (*instMap)[mach_inst] = si;
683 }
684
685 si->size(basePC + offset - origPC);
686
687 DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
688 si->getName(), mach_inst);
689 return si;
690}
691
694{
695 if (!instDone)
696 return NULL;
697 instDone = false;
698 updateNPC(next_pc.as<PCState>());
699
701 if (si)
702 return si;
703
704 // We didn't match in the AddrMap, but we still populated an entry. Fix
705 // up its byte masks.
706 const int chunkSize = sizeof(MachInst);
707
709
710 Addr firstBasePC = basePC - (instBytes->chunks.size() - 1) * chunkSize;
711 Addr firstOffset = origPC - firstBasePC;
712 Addr totalSize = instBytes->lastOffset - firstOffset +
713 (instBytes->chunks.size() - 1) * chunkSize;
714 int start = firstOffset;
715 instBytes->masks.clear();
716
717 while (totalSize) {
718 int end = start + totalSize;
719 end = (chunkSize < end) ? chunkSize : end;
720 int size = end - start;
721 int idx = instBytes->masks.size();
722
723 MachInst maskVal = mask(size * 8) << (start * 8);
724 assert(maskVal);
725
726 instBytes->masks.push_back(maskVal);
727 instBytes->chunks[idx] &= instBytes->masks[idx];
728 totalSize -= size;
729 start = 0;
730 }
731
732 return decode(emi, origPC);
733}
734
737{
738 return microcodeRom.fetchMicroop(micropc, curMacroop);
739}
740
741} // namespace X86ISA
742} // namespace gem5
#define DPRINTF(x,...)
Definition trace.hh:209
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
Target & as()
Definition pcstate.hh:73
StaticInstPtr fetchMicroop(MicroPC microPC, StaticInstPtr curMacroop)
State doPrefixState(uint8_t)
Definition decoder.cc:180
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition decoder.cc:673
static const ByteTable ImmediateTypeTwoByte
Definition decoder.hh:71
DecodePages * decodePages
Definition decoder.hh:240
StaticInstPtr fetchRomMicroop(MicroPC micropc, StaticInstPtr curMacroop) override
Definition decoder.cc:736
InstBytes * instBytes
Definition decoder.hh:95
State doThreeByte0F3AOpcodeState(uint8_t)
Definition decoder.cc:437
static const ByteTable UsesModRMTwoByte
Definition decoder.hh:66
uint8_t getNextByte()
Definition decoder.hh:117
void updateNPC(X86ISA::PCState &nextPC)
Definition decoder.hh:341
State doVex3Of3State(uint8_t)
Definition decoder.cc:317
decode_cache::InstMap< ExtMachInst > * instMap
Definition decoder.hh:244
static const ByteTable UsesModRMThreeByte0F3A
Definition decoder.hh:68
State doVexOpcodeState(uint8_t)
Definition decoder.cc:354
State doDisplacementState()
Definition decoder.cc:586
State doVex2Of2State(uint8_t)
Definition decoder.cc:246
static const ByteTable ImmediateTypeThreeByte0F38
Definition decoder.hh:72
State doVex2Of3State(uint8_t)
Definition decoder.cc:276
void getImmediate(int &collected, uint64_t &current, int size)
Definition decoder.hh:123
State processOpcode(ByteTable &immTable, ByteTable &modrmTable, bool addrSizedImm=false)
Definition decoder.cc:451
static const ByteTable UsesModRMThreeByte0F38
Definition decoder.hh:67
StaticInstPtr decodeInst(ExtMachInst mach_inst)
State doOneByteOpcodeState(uint8_t)
Definition decoder.cc:378
static const uint8_t SizeTypeToSize[3][10]
Definition decoder.hh:61
State doTwoByteOpcodeState(uint8_t)
Definition decoder.cc:400
X86ISAInst::MicrocodeRom microcodeRom
Definition decoder.hh:75
static const ByteTable ImmediateTypeThreeByte0F3A
Definition decoder.hh:73
State doThreeByte0F38OpcodeState(uint8_t)
Definition decoder.cc:423
static const ByteTable ImmediateTypeOneByte
Definition decoder.hh:70
State doSIBState(uint8_t)
Definition decoder.cc:565
State doModRMState(uint8_t)
Definition decoder.cc:511
static const ByteTable UsesModRMOneByte
Definition decoder.hh:65
Value & lookup(Addr addr)
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition bitfield.hh:79
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
Bitfield< 24, 21 > opcode
Definition types.hh:92
Bitfield< 3 > addr
Definition types.hh:84
Bitfield< 15, 3 > si
Definition misc.hh:895
@ SixtyFourBitMode
Definition types.hh:204
@ OperandSizeOverride
Definition types.hh:68
@ AddressSizeOverride
Definition types.hh:69
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
uint16_t MicroPC
Definition types.hh:149
std::vector< MachInst > chunks
Definition decoder.hh:83
std::vector< MachInst > masks
Definition decoder.hh:84
OperatingModeAndCPL mode
Definition types.hh:245
struct gem5::X86ISA::ExtMachInst::@42 opcode
LegacyPrefixVector legacy
Definition types.hh:217

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