gem5  v22.1.0.0
decoder.cc
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28 
29 #include "arch/x86/decoder.hh"
30 
31 #include "arch/x86/regs/misc.hh"
32 #include "base/logging.hh"
33 #include "base/trace.hh"
34 #include "base/types.hh"
35 #include "debug/Decode.hh"
36 #include "debug/Decoder.hh"
37 
38 namespace gem5
39 {
40 
41 namespace X86ISA
42 {
43 
44 X86ISAInst::MicrocodeRom Decoder::microcodeRom;
45 
48 {
49  origPC = basePC + offset;
50  DPRINTF(Decoder, "Setting origPC to %#x\n", origPC);
52  chunkIdx = 0;
53 
54  emi.rex = 0;
55  emi.legacy = 0;
56  emi.vex = 0;
57 
58  emi.opcode.type = BadOpcode;
59  emi.opcode.op = 0;
60 
62  emi.immediate = 0;
63  emi.displacement = 0;
64  emi.dispSize = 0;
65 
66  emi.modRM = 0;
67  emi.sib = 0;
68 
69  if (instBytes->si) {
70  return FromCacheState;
71  } else {
72  instBytes->chunks.clear();
73  return PrefixState;
74  }
75 }
76 
77 void
79 {
80  // This function drives the decoder state machine.
81 
82  // Some sanity checks. You shouldn't try to process more bytes if
83  // there aren't any, and you shouldn't overwrite an already decoded
84  // ExtMachInst.
85  assert(!outOfBytes);
86  assert(!instDone);
87 
88  if (state == ResetState)
89  state = doResetState();
90  if (state == FromCacheState) {
92  } else {
93  instBytes->chunks.push_back(fetchChunk);
94  }
95 
96  // While there's still something to do...
97  while (!instDone && !outOfBytes) {
98  uint8_t nextByte = getNextByte();
99  switch (state) {
100  case PrefixState:
101  state = doPrefixState(nextByte);
102  break;
103  case Vex2Of2State:
104  state = doVex2Of2State(nextByte);
105  break;
106  case Vex2Of3State:
107  state = doVex2Of3State(nextByte);
108  break;
109  case Vex3Of3State:
110  state = doVex3Of3State(nextByte);
111  break;
112  case VexOpcodeState:
113  state = doVexOpcodeState(nextByte);
114  break;
115  case OneByteOpcodeState:
116  state = doOneByteOpcodeState(nextByte);
117  break;
118  case TwoByteOpcodeState:
119  state = doTwoByteOpcodeState(nextByte);
120  break;
122  state = doThreeByte0F38OpcodeState(nextByte);
123  break;
125  state = doThreeByte0F3AOpcodeState(nextByte);
126  break;
127  case ModRMState:
128  state = doModRMState(nextByte);
129  break;
130  case SIBState:
131  state = doSIBState(nextByte);
132  break;
133  case DisplacementState:
135  break;
136  case ImmediateState:
138  break;
139  case ErrorState:
140  panic("Went to the error state in the decoder.\n");
141  default:
142  panic("Unrecognized state! %d\n", state);
143  }
144  }
145 }
146 
149 {
150  DPRINTF(Decoder, "Looking at cache state.\n");
151  if ((fetchChunk & instBytes->masks[chunkIdx]) !=
153  DPRINTF(Decoder, "Decode cache miss.\n");
154  // The chached chunks didn't match what was fetched. Fall back to the
155  // predecoder.
157  instBytes->chunks.resize(chunkIdx + 1);
158  instBytes->si = NULL;
159  chunkIdx = 0;
161  offset = origPC % sizeof(MachInst);
162  basePC = origPC - offset;
163  return PrefixState;
164  } else if (chunkIdx == instBytes->chunks.size() - 1) {
165  // We matched the cache, so use its value.
166  instDone = true;
168  if (offset == sizeof(MachInst))
169  outOfBytes = true;
170  return ResetState;
171  } else {
172  // We matched so far, but need to check more chunks.
173  chunkIdx++;
174  outOfBytes = true;
175  return FromCacheState;
176  }
177 }
178 
179 // Either get a prefix and record it in the ExtMachInst, or send the
180 // state machine on to get the opcode(s).
182 Decoder::doPrefixState(uint8_t nextByte)
183 {
184  // The REX and VEX prefixes only exist in 64 bit mode, so we use a
185  // different table for that.
186  const int table_idx = emi.mode.submode == SixtyFourBitMode ? 1 : 0;
187  const uint8_t prefix = Prefixes[table_idx][nextByte];
188  State nextState = PrefixState;
189  if (prefix)
190  consumeByte();
191  switch(prefix) {
192  // Operand size override prefixes
193  case OperandSizeOverride:
194  DPRINTF(Decoder, "Found operand size override prefix.\n");
195  emi.legacy.op = true;
196  break;
197  case AddressSizeOverride:
198  DPRINTF(Decoder, "Found address size override prefix.\n");
199  emi.legacy.addr = true;
200  break;
201  // Segment override prefixes
202  case CSOverride:
203  case DSOverride:
204  case ESOverride:
205  case FSOverride:
206  case GSOverride:
207  case SSOverride:
208  DPRINTF(Decoder, "Found segment override.\n");
209  emi.legacy.seg = prefix;
210  break;
211  case Lock:
212  DPRINTF(Decoder, "Found lock prefix.\n");
213  emi.legacy.lock = true;
214  break;
215  case Rep:
216  DPRINTF(Decoder, "Found rep prefix.\n");
217  emi.legacy.rep = true;
218  break;
219  case Repne:
220  DPRINTF(Decoder, "Found repne prefix.\n");
221  emi.legacy.repne = true;
222  break;
223  case RexPrefix:
224  DPRINTF(Decoder, "Found Rex prefix %#x.\n", nextByte);
225  emi.rex = nextByte;
226  break;
227  case Vex2Prefix:
228  DPRINTF(Decoder, "Found VEX two-byte prefix %#x.\n", nextByte);
229  emi.vex.present = 1;
230  nextState = Vex2Of2State;
231  break;
232  case Vex3Prefix:
233  DPRINTF(Decoder, "Found VEX three-byte prefix %#x.\n", nextByte);
234  emi.vex.present = 1;
235  nextState = Vex2Of3State;
236  break;
237  case 0:
238  nextState = OneByteOpcodeState;
239  break;
240 
241  default:
242  panic("Unrecognized prefix %#x\n", nextByte);
243  }
244  return nextState;
245 }
246 
248 Decoder::doVex2Of2State(uint8_t nextByte)
249 {
250  consumeByte();
251  Vex2Of2 vex = nextByte;
252 
253  emi.rex.r = !vex.r;
254 
255  emi.vex.l = vex.l;
256  emi.vex.v = ~vex.v;
257 
258  switch (vex.p) {
259  case 0:
260  break;
261  case 1:
262  emi.legacy.op = 1;
263  break;
264  case 2:
265  emi.legacy.rep = 1;
266  break;
267  case 3:
268  emi.legacy.repne = 1;
269  break;
270  }
271 
272  emi.opcode.type = TwoByteOpcode;
273 
274  return VexOpcodeState;
275 }
276 
278 Decoder::doVex2Of3State(uint8_t nextByte)
279 {
280  if (emi.mode.submode != SixtyFourBitMode && bits(nextByte, 7, 6) == 0x3) {
281  // This was actually an LDS instruction. Reroute to that path.
282  emi.vex.present = 0;
283  emi.opcode.type = OneByteOpcode;
284  emi.opcode.op = 0xC4;
286  nextByte >= 0xA0 && nextByte <= 0xA3);
287  }
288 
289  consumeByte();
290  Vex2Of3 vex = nextByte;
291 
292  emi.rex.r = !vex.r;
293  emi.rex.x = !vex.x;
294  emi.rex.b = !vex.b;
295 
296  switch (vex.m) {
297  case 1:
298  emi.opcode.type = TwoByteOpcode;
299  break;
300  case 2:
301  emi.opcode.type = ThreeByte0F38Opcode;
302  break;
303  case 3:
304  emi.opcode.type = ThreeByte0F3AOpcode;
305  break;
306  default:
307  // These encodings are reserved. Pretend this was an undefined
308  // instruction so the main decoder will behave correctly, and stop
309  // trying to interpret bytes.
310  emi.opcode.type = TwoByteOpcode;
311  emi.opcode.op = 0x0B;
312  instDone = true;
313  return ResetState;
314  }
315  return Vex3Of3State;
316 }
317 
319 Decoder::doVex3Of3State(uint8_t nextByte)
320 {
321  if (emi.mode.submode != SixtyFourBitMode && bits(nextByte, 7, 6) == 0x3) {
322  // This was actually an LES instruction. Reroute to that path.
323  emi.vex.present = 0;
324  emi.opcode.type = OneByteOpcode;
325  emi.opcode.op = 0xC5;
327  nextByte >= 0xA0 && nextByte <= 0xA3);
328  }
329 
330  consumeByte();
331  Vex3Of3 vex = nextByte;
332 
333  emi.rex.w = vex.w;
334 
335  emi.vex.l = vex.l;
336  emi.vex.v = ~vex.v;
337 
338  switch (vex.p) {
339  case 0:
340  break;
341  case 1:
342  emi.legacy.op = 1;
343  break;
344  case 2:
345  emi.legacy.rep = 1;
346  break;
347  case 3:
348  emi.legacy.repne = 1;
349  break;
350  }
351 
352  return VexOpcodeState;
353 }
354 
356 Decoder::doVexOpcodeState(uint8_t nextByte)
357 {
358  DPRINTF(Decoder, "Found VEX opcode %#x.\n", nextByte);
359 
360  emi.opcode.op = nextByte;
361  consumeByte();
362 
363  switch (emi.opcode.type) {
364  case TwoByteOpcode:
366  case ThreeByte0F38Opcode:
369  case ThreeByte0F3AOpcode:
372  default:
373  panic("Unrecognized opcode type %d.\n", emi.opcode.type);
374  }
375 }
376 
377 // Load the first opcode byte. Determine if there are more opcode bytes, and
378 // if not, what immediate and/or ModRM is needed.
381 {
382  State nextState = ErrorState;
383  consumeByte();
384 
385  if (nextByte == 0x0f) {
386  DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
387  nextState = TwoByteOpcodeState;
388  } else {
389  DPRINTF(Decoder, "Found one byte opcode %#x.\n", nextByte);
390  emi.opcode.type = OneByteOpcode;
391  emi.opcode.op = nextByte;
392 
394  nextByte >= 0xA0 && nextByte <= 0xA3);
395  }
396  return nextState;
397 }
398 
399 // Load the second opcode byte. Determine if there are more opcode bytes, and
400 // if not, what immediate and/or ModRM is needed.
403 {
404  State nextState = ErrorState;
405  consumeByte();
406  if (nextByte == 0x38) {
407  nextState = ThreeByte0F38OpcodeState;
408  DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
409  } else if (nextByte == 0x3a) {
410  nextState = ThreeByte0F3AOpcodeState;
411  DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
412  } else {
413  DPRINTF(Decoder, "Found two byte opcode %#x.\n", nextByte);
414  emi.opcode.type = TwoByteOpcode;
415  emi.opcode.op = nextByte;
416 
418  }
419  return nextState;
420 }
421 
422 // Load the third opcode byte and determine what immediate and/or ModRM is
423 // needed.
426 {
427  consumeByte();
428 
429  DPRINTF(Decoder, "Found three byte 0F38 opcode %#x.\n", nextByte);
430  emi.opcode.type = ThreeByte0F38Opcode;
431  emi.opcode.op = nextByte;
432 
434 }
435 
436 // Load the third opcode byte and determine what immediate and/or ModRM is
437 // needed.
440 {
441  consumeByte();
442 
443  DPRINTF(Decoder, "Found three byte 0F3A opcode %#x.\n", nextByte);
444  emi.opcode.type = ThreeByte0F3AOpcode;
445  emi.opcode.op = nextByte;
446 
448 }
449 
450 // Generic opcode processing which determines the immediate size, and whether
451 // or not there's a modrm byte.
453 Decoder::processOpcode(ByteTable &immTable, ByteTable &modrmTable,
454  bool addrSizedImm)
455 {
456  State nextState = ErrorState;
457  const uint8_t opcode = emi.opcode.op;
458 
459  // Figure out the effective operand size. This can be overriden to
460  // a fixed value at the decoder level.
461  int logOpSize;
462  if (emi.rex.w)
463  logOpSize = 3; // 64 bit operand size
464  else if (emi.legacy.op)
465  logOpSize = altOp;
466  else
467  logOpSize = defOp;
468 
469  // Set the actual op size.
470  emi.opSize = 1 << logOpSize;
471 
472  // Figure out the effective address size. This can be overriden to
473  // a fixed value at the decoder level.
474  int logAddrSize;
475  if (emi.legacy.addr)
476  logAddrSize = altAddr;
477  else
478  logAddrSize = defAddr;
479 
480  // Set the actual address size.
481  emi.addrSize = 1 << logAddrSize;
482 
483  // Figure out the effective stack width. This can be overriden to
484  // a fixed value at the decoder level.
485  emi.stackSize = 1 << stack;
486 
487  // Figure out how big of an immediate we'll retreive based
488  // on the opcode.
489  int immType = immTable[opcode];
490  if (addrSizedImm)
491  immediateSize = SizeTypeToSize[logAddrSize - 1][immType];
492  else
493  immediateSize = SizeTypeToSize[logOpSize - 1][immType];
494 
495  // Determine what to expect next.
496  if (modrmTable[opcode]) {
497  nextState = ModRMState;
498  } else {
499  if (immediateSize) {
500  nextState = ImmediateState;
501  } else {
502  instDone = true;
503  nextState = ResetState;
504  }
505  }
506  return nextState;
507 }
508 
509 // Get the ModRM byte and determine what displacement, if any, there is.
510 // Also determine whether or not to get the SIB byte, displacement, or
511 // immediate next.
513 Decoder::doModRMState(uint8_t nextByte)
514 {
515  State nextState = ErrorState;
516  ModRM modRM = nextByte;
517  DPRINTF(Decoder, "Found modrm byte %#x.\n", nextByte);
518  if (emi.addrSize == 2) {
519  // Figure out 16 bit displacement size.
520  if ((modRM.mod == 0 && modRM.rm == 6) || modRM.mod == 2)
521  displacementSize = 2;
522  else if (modRM.mod == 1)
523  displacementSize = 1;
524  else
525  displacementSize = 0;
526  } else {
527  // Figure out 32/64 bit displacement size.
528  if ((modRM.mod == 0 && modRM.rm == 5) || modRM.mod == 2)
529  displacementSize = 4;
530  else if (modRM.mod == 1)
531  displacementSize = 1;
532  else
533  displacementSize = 0;
534  }
535 
536  // The "test" instruction in group 3 needs an immediate, even though
537  // the other instructions with the same actual opcode don't.
538  if (emi.opcode.type == OneByteOpcode && (modRM.reg & 0x6) == 0) {
539  if (emi.opcode.op == 0xF6)
540  immediateSize = 1;
541  else if (emi.opcode.op == 0xF7)
542  immediateSize = (emi.opSize == 8) ? 4 : emi.opSize;
543  }
544 
545  // If there's an SIB, get that next.
546  // There is no SIB in 16 bit mode.
547  if (modRM.rm == 4 && modRM.mod != 3 && emi.addrSize != 2) {
548  nextState = SIBState;
549  } else if (displacementSize) {
550  nextState = DisplacementState;
551  } else if (immediateSize) {
552  nextState = ImmediateState;
553  } else {
554  instDone = true;
555  nextState = ResetState;
556  }
557  // The ModRM byte is consumed no matter what.
558  consumeByte();
559  emi.modRM = modRM;
560  return nextState;
561 }
562 
563 // Get the SIB byte. We don't do anything with it at this point, other
564 // than storing it in the ExtMachInst. Determine if we need to get a
565 // displacement or immediate next.
567 Decoder::doSIBState(uint8_t nextByte)
568 {
569  State nextState = ErrorState;
570  emi.sib = nextByte;
571  DPRINTF(Decoder, "Found SIB byte %#x.\n", nextByte);
572  consumeByte();
573  if (emi.modRM.mod == 0 && emi.sib.base == 5)
574  displacementSize = 4;
575  if (displacementSize) {
576  nextState = DisplacementState;
577  } else if (immediateSize) {
578  nextState = ImmediateState;
579  } else {
580  instDone = true;
581  nextState = ResetState;
582  }
583  return nextState;
584 }
585 
586 // Gather up the displacement, or at least as much of it as we can get.
589 {
590  State nextState = ErrorState;
591 
595 
596  DPRINTF(Decoder, "Collecting %d byte displacement, got %d bytes.\n",
598 
600  // Reset this for other immediates.
601  immediateCollected = 0;
602  // Sign extend the displacement.
603  switch(displacementSize)
604  {
605  case 1:
606  emi.displacement = sext<8>(emi.displacement);
607  break;
608  case 2:
609  emi.displacement = sext<16>(emi.displacement);
610  break;
611  case 4:
612  emi.displacement = sext<32>(emi.displacement);
613  break;
614  default:
615  panic("Undefined displacement size!\n");
616  }
617  DPRINTF(Decoder, "Collected displacement %#x.\n",
618  emi.displacement);
619  if (immediateSize) {
620  nextState = ImmediateState;
621  } else {
622  instDone = true;
623  nextState = ResetState;
624  }
625 
627  }
628  else
629  nextState = DisplacementState;
630  return nextState;
631 }
632 
633 // Gather up the immediate, or at least as much of it as we can get.
636 {
637  State nextState = ErrorState;
638 
640 
641  DPRINTF(Decoder, "Collecting %d byte immediate, got %d bytes.\n",
643 
645  // Reset this for other immediates.
646  immediateCollected = 0;
647 
648  //XXX Warning! The following is an observed pattern and might
649  // not always be true!
650 
651  // Instructions which use 64 bit operands but 32 bit immediates
652  // need to have the immediate sign extended to 64 bits.
653  // Instructions which use true 64 bit immediates won't be
654  // affected, and instructions that use true 32 bit immediates
655  // won't notice.
656  switch(immediateSize) {
657  case 4:
658  emi.immediate = sext<32>(emi.immediate);
659  break;
660  case 1:
661  emi.immediate = sext<8>(emi.immediate);
662  }
663 
664  DPRINTF(Decoder, "Collected immediate %#x.\n",
665  emi.immediate);
666  instDone = true;
667  nextState = ResetState;
668  } else {
669  nextState = ImmediateState;
670  }
671  return nextState;
672 }
673 
676 
679 {
681 
682  auto iter = instMap->find(mach_inst);
683  if (iter != instMap->end()) {
684  si = iter->second;
685  } else {
686  si = decodeInst(mach_inst);
687  (*instMap)[mach_inst] = si;
688  }
689 
690  DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
691  si->getName(), mach_inst);
692  return si;
693 }
694 
697 {
698  if (!instDone)
699  return NULL;
700  instDone = false;
701  updateNPC(next_pc.as<PCState>());
702 
704  if (si)
705  return si;
706 
707  // We didn't match in the AddrMap, but we still populated an entry. Fix
708  // up its byte masks.
709  const int chunkSize = sizeof(MachInst);
710 
712 
713  Addr firstBasePC = basePC - (instBytes->chunks.size() - 1) * chunkSize;
714  Addr firstOffset = origPC - firstBasePC;
715  Addr totalSize = instBytes->lastOffset - firstOffset +
716  (instBytes->chunks.size() - 1) * chunkSize;
717  int start = firstOffset;
718  instBytes->masks.clear();
719 
720  while (totalSize) {
721  int end = start + totalSize;
722  end = (chunkSize < end) ? chunkSize : end;
723  int size = end - start;
724  int idx = instBytes->masks.size();
725 
726  MachInst maskVal = mask(size * 8) << (start * 8);
727  assert(maskVal);
728 
729  instBytes->masks.push_back(maskVal);
730  instBytes->chunks[idx] &= instBytes->masks[idx];
731  totalSize -= size;
732  start = 0;
733  }
734 
735  si = decode(emi, origPC);
736  return si;
737 }
738 
741 {
742  return microcodeRom.fetchMicroop(micropc, curMacroop);
743 }
744 
745 } // namespace X86ISA
746 } // namespace gem5
#define DPRINTF(x,...)
Definition: trace.hh:186
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
Target & as()
Definition: pcstate.hh:72
StaticInstPtr fetchMicroop(MicroPC microPC, StaticInstPtr curMacroop)
State doPrefixState(uint8_t)
Definition: decoder.cc:182
std::unordered_map< CacheKey, decode_cache::InstMap< ExtMachInst > * > InstCacheMap
Definition: decoder.hh:246
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.cc:678
ExtMachInst emi
Definition: decoder.hh:104
static ByteTable ImmediateTypeTwoByte
Definition: decoder.hh:71
State doFromCacheState()
Definition: decoder.cc:148
DecodePages * decodePages
Definition: decoder.hh:240
StaticInstPtr fetchRomMicroop(MicroPC micropc, StaticInstPtr curMacroop) override
Definition: decoder.cc:740
InstBytes * instBytes
Definition: decoder.hh:95
State doThreeByte0F3AOpcodeState(uint8_t)
Definition: decoder.cc:439
static ByteTable UsesModRMTwoByte
Definition: decoder.hh:66
uint8_t getNextByte()
Definition: decoder.hh:117
void updateNPC(X86ISA::PCState &nextPC)
Definition: decoder.hh:341
State doVex3Of3State(uint8_t)
Definition: decoder.cc:319
decode_cache::InstMap< ExtMachInst > * instMap
Definition: decoder.hh:244
static InstBytes dummy
Definition: decoder.hh:91
static ByteTable UsesModRMThreeByte0F3A
Definition: decoder.hh:68
State doVexOpcodeState(uint8_t)
Definition: decoder.cc:356
State doDisplacementState()
Definition: decoder.cc:588
State doVex2Of2State(uint8_t)
Definition: decoder.cc:248
static ByteTable ImmediateTypeThreeByte0F38
Definition: decoder.hh:72
State doVex2Of3State(uint8_t)
Definition: decoder.cc:278
void getImmediate(int &collected, uint64_t &current, int size)
Definition: decoder.hh:123
State processOpcode(ByteTable &immTable, ByteTable &modrmTable, bool addrSizedImm=false)
Definition: decoder.cc:453
static ByteTable UsesModRMThreeByte0F38
Definition: decoder.hh:67
StaticInstPtr decodeInst(ExtMachInst mach_inst)
State doImmediateState()
Definition: decoder.cc:635
static InstCacheMap instCacheMap
Definition: decoder.hh:247
State doOneByteOpcodeState(uint8_t)
Definition: decoder.cc:380
MachInst fetchChunk
Definition: decoder.hh:94
static const uint8_t SizeTypeToSize[3][10]
Definition: decoder.hh:61
State doResetState()
Definition: decoder.cc:47
State doTwoByteOpcodeState(uint8_t)
Definition: decoder.cc:402
static X86ISAInst::MicrocodeRom microcodeRom
Definition: decoder.hh:75
static ByteTable ImmediateTypeThreeByte0F3A
Definition: decoder.hh:73
State doThreeByte0F38OpcodeState(uint8_t)
Definition: decoder.cc:425
static ByteTable ImmediateTypeOneByte
Definition: decoder.hh:70
State doSIBState(uint8_t)
Definition: decoder.cc:567
State doModRMState(uint8_t)
Definition: decoder.cc:513
static ByteTable UsesModRMOneByte
Definition: decoder.hh:65
Value & lookup(Addr addr)
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
Bitfield< 24, 21 > opcode
Definition: types.hh:92
Bitfield< 3 > addr
Definition: types.hh:84
Bitfield< 15, 3 > si
Definition: misc.hh:867
@ SixtyFourBitMode
Definition: types.hh:204
@ GSOverride
Definition: types.hh:66
@ FSOverride
Definition: types.hh:65
@ Vex3Prefix
Definition: types.hh:74
@ OperandSizeOverride
Definition: types.hh:68
@ AddressSizeOverride
Definition: types.hh:69
@ RexPrefix
Definition: types.hh:67
@ Vex2Prefix
Definition: types.hh:73
@ DSOverride
Definition: types.hh:64
@ CSOverride
Definition: types.hh:62
@ ESOverride
Definition: types.hh:61
@ SSOverride
Definition: types.hh:63
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
uint16_t MicroPC
Definition: types.hh:149
std::vector< MachInst > chunks
Definition: decoder.hh:83
std::vector< MachInst > masks
Definition: decoder.hh:84
OperatingModeAndCPL mode
Definition: types.hh:245
LegacyPrefixVector legacy
Definition: types.hh:217
struct gem5::X86ISA::ExtMachInst::@33 opcode

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