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133 #include <sys/signal.h>
149 #include "blobs/gdb_xml_aarch64_core.hh"
150 #include "blobs/gdb_xml_aarch64_fpu.hh"
151 #include "blobs/gdb_xml_aarch64_target.hh"
152 #include "blobs/gdb_xml_arm_core.hh"
153 #include "blobs/gdb_xml_arm_target.hh"
154 #include "blobs/gdb_xml_arm_vfpv3.hh"
158 #include "debug/GDBAcc.hh"
159 #include "debug/GDBMisc.hh"
174 auto req = std::make_shared<Request>(
addr, 64, 0x40, -1, 0, 0);
190 :
BaseRemoteGDB(_system, tc, _port), regCache32(this), regCache64(this)
203 DPRINTF(GDBAcc,
"acc: %#x mapping is invalid\n",
va);
208 DPRINTF(GDBAcc,
"acc: %#x mapping is valid\n",
va);
220 DPRINTF(GDBAcc,
"getRegs in remotegdb \n");
222 for (
int i = 0;
i < 31; ++
i)
243 DPRINTF(GDBAcc,
"setRegs in remotegdb \n");
245 for (
int i = 0;
i < 31; ++
i)
272 DPRINTF(GDBAcc,
"getRegs in remotegdb \n");
293 for (
int i = 0;
i < 32;
i++)
302 DPRINTF(GDBAcc,
"setRegs in remotegdb \n");
320 pc_state.set(
r.gpr[15]);
332 #define GDB_XML(x, s) \
333 { x, std::string(reinterpret_cast<const char *>(Blobs::s), \
335 static const std::map<std::string, std::string> annexMap32{
336 GDB_XML(
"target.xml", gdb_xml_arm_target),
337 GDB_XML(
"arm-core.xml", gdb_xml_arm_core),
338 GDB_XML(
"arm-vfpv3.xml", gdb_xml_arm_vfpv3),
340 static const std::map<std::string, std::string> annexMap64{
341 GDB_XML(
"target.xml", gdb_xml_aarch64_target),
342 GDB_XML(
"aarch64-core.xml", gdb_xml_aarch64_core),
343 GDB_XML(
"aarch64-fpu.xml", gdb_xml_aarch64_fpu),
347 auto it = annexMap.find(annex);
348 if (it == annexMap.end())
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
static void output(const char *filename)
virtual VecRegContainer & getWritableVecReg(const RegId ®)=0
VecElem v[NumVecV8ArchRegs *NumVecElemPerNeonVecReg]
void getRegs(ThreadContext *)
Fill the raw buffer from the registers in the ThreadContext.
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
AArch64GdbRegCache regCache64
EmulationPageTable * pTable
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
virtual Process * getProcessPtr()=0
const int NumVecV8ArchRegs
const Entry * lookup(Addr vaddr)
Lookup function.
Register ID: describe an architectural register with its class and index.
void getRegs(ThreadContext *)
Fill the raw buffer from the registers in the ThreadContext.
ThreadContext * context()
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
void setRegs(ThreadContext *) const
Set the ThreadContext's registers from the values in the raw buffer.
virtual const VecRegContainer & readVecReg(const RegId ®) const =0
void setRegs(ThreadContext *) const
Set the ThreadContext's registers from the values in the raw buffer.
constexpr decltype(nullptr) NoFault
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
bool done() const
Are we done? That is, did the last call to next() advance past the end of the region?
Concrete subclasses of this abstract class represent how the register values are transmitted on the w...
virtual BaseTLB * getITBPtr()=0
bool getXferFeaturesRead(const std::string &annex, std::string &output)
Get an XML target description.
virtual TheISA::PCState pcState() const =0
static bool tryTranslate(ThreadContext *tc, Addr addr)
@ VecRegClass
Vector Register.
BaseGdbRegCache * gdbRegs()
struct ArmISA::RemoteGDB::AArch64GdbRegCache::@4 r
bool acc(Addr addr, size_t len)
Overload hash function for BasicBlockRange type.
constexpr unsigned NumVecElemPerNeonVecReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
This class takes an arbitrary memory region (address/length pair) and generates a series of appropria...
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
AArch32GdbRegCache regCache32
bool inAArch64(ThreadContext *tc)
virtual RegVal readIntReg(RegIndex reg_idx) const =0
virtual BaseTLB * getDTBPtr()=0
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