gem5  v20.1.0.0
remote_gdb.cc
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1 /*
2  * Copyright 2015 LabWare
3  * Copyright 2014 Google Inc.
4  * Copyright (c) 2010, 2013, 2016, 2018-2019 ARM Limited
5  * All rights reserved
6  *
7  * The license below extends only to copyright in the software and shall
8  * not be construed as granting a license to any other intellectual
9  * property including but not limited to intellectual property relating
10  * to a hardware implementation of the functionality of the software
11  * licensed hereunder. You may use the software subject to the license
12  * terms below provided that you ensure that this notice is replicated
13  * unmodified and in its entirety in all distributions of the software,
14  * modified or unmodified, in source code or in binary form.
15  *
16  * Copyright (c) 2002-2005 The Regents of The University of Michigan
17  * All rights reserved.
18  *
19  * Redistribution and use in source and binary forms, with or without
20  * modification, are permitted provided that the following conditions are
21  * met: redistributions of source code must retain the above copyright
22  * notice, this list of conditions and the following disclaimer;
23  * redistributions in binary form must reproduce the above copyright
24  * notice, this list of conditions and the following disclaimer in the
25  * documentation and/or other materials provided with the distribution;
26  * neither the name of the copyright holders nor the names of its
27  * contributors may be used to endorse or promote products derived from
28  * this software without specific prior written permission.
29  *
30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41  */
42 
43 /*
44  * Copyright (c) 1990, 1993 The Regents of the University of California
45  * All rights reserved
46  *
47  * This software was developed by the Computer Systems Engineering group
48  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
49  * contributed to Berkeley.
50  *
51  * All advertising materials mentioning features or use of this software
52  * must display the following acknowledgement:
53  * This product includes software developed by the University of
54  * California, Lawrence Berkeley Laboratories.
55  *
56  * Redistribution and use in source and binary forms, with or without
57  * modification, are permitted provided that the following conditions
58  * are met:
59  * 1. Redistributions of source code must retain the above copyright
60  * notice, this list of conditions and the following disclaimer.
61  * 2. Redistributions in binary form must reproduce the above copyright
62  * notice, this list of conditions and the following disclaimer in the
63  * documentation and/or other materials provided with the distribution.
64  * 3. All advertising materials mentioning features or use of this software
65  * must display the following acknowledgement:
66  * This product includes software developed by the University of
67  * California, Berkeley and its contributors.
68  * 4. Neither the name of the University nor the names of its contributors
69  * may be used to endorse or promote products derived from this software
70  * without specific prior written permission.
71  *
72  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
73  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75  * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
76  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
82  * SUCH DAMAGE.
83  *
84  * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
85  */
86 
87 /*-
88  * Copyright (c) 2001 The NetBSD Foundation, Inc.
89  * All rights reserved.
90  *
91  * This code is derived from software contributed to The NetBSD Foundation
92  * by Jason R. Thorpe.
93  *
94  * Redistribution and use in source and binary forms, with or without
95  * modification, are permitted provided that the following conditions
96  * are met:
97  * 1. Redistributions of source code must retain the above copyright
98  * notice, this list of conditions and the following disclaimer.
99  * 2. Redistributions in binary form must reproduce the above copyright
100  * notice, this list of conditions and the following disclaimer in the
101  * documentation and/or other materials provided with the distribution.
102  * 3. All advertising materials mentioning features or use of this software
103  * must display the following acknowledgement:
104  * This product includes software developed by the NetBSD
105  * Foundation, Inc. and its contributors.
106  * 4. Neither the name of The NetBSD Foundation nor the names of its
107  * contributors may be used to endorse or promote products derived
108  * from this software without specific prior written permission.
109  *
110  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
111  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
112  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
113  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
114  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
115  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
116  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
117  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
118  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
119  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
120  * POSSIBILITY OF SUCH DAMAGE.
121  */
122 
123 /*
124  * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
125  *
126  * Taken from NetBSD
127  *
128  * "Stub" to allow remote cpu to debug over a serial line using gdb.
129  */
130 
131 #include "arch/arm/remote_gdb.hh"
132 
133 #include <sys/signal.h>
134 #include <unistd.h>
135 
136 #include <string>
137 
138 #include "arch/arm/decoder.hh"
139 #include "arch/arm/pagetable.hh"
140 #include "arch/arm/registers.hh"
141 #include "arch/arm/system.hh"
142 #include "arch/arm/utility.hh"
143 #include "arch/generic/tlb.hh"
144 #include "base/chunk_generator.hh"
145 #include "base/intmath.hh"
146 #include "base/remote_gdb.hh"
147 #include "base/socket.hh"
148 #include "base/trace.hh"
149 #include "blobs/gdb_xml_aarch64_core.hh"
150 #include "blobs/gdb_xml_aarch64_fpu.hh"
151 #include "blobs/gdb_xml_aarch64_target.hh"
152 #include "blobs/gdb_xml_arm_core.hh"
153 #include "blobs/gdb_xml_arm_target.hh"
154 #include "blobs/gdb_xml_arm_vfpv3.hh"
155 #include "cpu/static_inst.hh"
156 #include "cpu/thread_context.hh"
157 #include "cpu/thread_state.hh"
158 #include "debug/GDBAcc.hh"
159 #include "debug/GDBMisc.hh"
160 #include "mem/page_table.hh"
161 #include "mem/physical.hh"
162 #include "mem/port.hh"
163 #include "sim/full_system.hh"
164 #include "sim/system.hh"
165 
166 using namespace std;
167 using namespace ArmISA;
168 
169 static bool
171 {
172  // Set up a functional memory Request to pass to the TLB
173  // to get it to translate the vaddr to a paddr
174  auto req = std::make_shared<Request>(addr, 64, 0x40, -1, 0, 0);
175 
176  // Check the TLBs for a translation
177  // It's possible that there is a valid translation in the tlb
178  // that is no loger valid in the page table in memory
179  // so we need to check here first
180  //
181  // Calling translateFunctional invokes a table-walk if required
182  // so we should always succeed
183  auto *dtb = tc->getDTBPtr();
184  auto *itb = tc->getITBPtr();
185  return dtb->translateFunctional(req, tc, BaseTLB::Read) == NoFault ||
186  itb->translateFunctional(req, tc, BaseTLB::Read) == NoFault;
187 }
188 
189 RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc, int _port)
190  : BaseRemoteGDB(_system, tc, _port), regCache32(this), regCache64(this)
191 {
192 }
193 
194 /*
195  * Determine if the mapping at va..(va+len) is valid.
196  */
197 bool
199 {
200  if (FullSystem) {
201  for (ChunkGenerator gen(va, len, PageBytes); !gen.done(); gen.next()) {
202  if (!tryTranslate(context(), gen.addr())) {
203  DPRINTF(GDBAcc, "acc: %#x mapping is invalid\n", va);
204  return false;
205  }
206  }
207 
208  DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
209  return true;
210  } else {
211  // Check to make sure the first byte is mapped into the processes
212  // address space.
213  return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
214  }
215 }
216 
217 void
219 {
220  DPRINTF(GDBAcc, "getRegs in remotegdb \n");
221 
222  for (int i = 0; i < 31; ++i)
223  r.x[i] = context->readIntReg(INTREG_X0 + i);
224  r.spx = context->readIntReg(INTREG_SPX);
225  r.pc = context->pcState().pc();
227 
228  size_t base = 0;
229  for (int i = 0; i < NumVecV8ArchRegs; i++) {
230  auto v = (context->readVecReg(RegId(VecRegClass, i))).as<VecElem>();
231  for (size_t j = 0; j < NumVecElemPerNeonVecReg; j++) {
232  r.v[base] = v[j];
233  base++;
234  }
235  }
238 }
239 
240 void
242 {
243  DPRINTF(GDBAcc, "setRegs in remotegdb \n");
244 
245  for (int i = 0; i < 31; ++i)
246  context->setIntReg(INTREG_X0 + i, r.x[i]);
247  auto pc_state = context->pcState();
248  pc_state.set(r.pc);
249  context->pcState(pc_state);
251  // Update the stack pointer. This should be done after
252  // updating CPSR/PSTATE since that might affect how SPX gets
253  // mapped.
254  context->setIntReg(INTREG_SPX, r.spx);
255 
256  size_t base = 0;
257  for (int i = 0; i < NumVecV8ArchRegs; i++) {
258  auto v = (context->getWritableVecReg(
259  RegId(VecRegClass, i))).as<VecElem>();
260  for (size_t j = 0; j < NumVecElemPerNeonVecReg; j++) {
261  v[j] = r.v[base];
262  base++;
263  }
264  }
267 }
268 
269 void
271 {
272  DPRINTF(GDBAcc, "getRegs in remotegdb \n");
273 
274  r.gpr[0] = context->readIntReg(INTREG_R0);
275  r.gpr[1] = context->readIntReg(INTREG_R1);
276  r.gpr[2] = context->readIntReg(INTREG_R2);
277  r.gpr[3] = context->readIntReg(INTREG_R3);
278  r.gpr[4] = context->readIntReg(INTREG_R4);
279  r.gpr[5] = context->readIntReg(INTREG_R5);
280  r.gpr[6] = context->readIntReg(INTREG_R6);
281  r.gpr[7] = context->readIntReg(INTREG_R7);
282  r.gpr[8] = context->readIntReg(INTREG_R8);
283  r.gpr[9] = context->readIntReg(INTREG_R9);
284  r.gpr[10] = context->readIntReg(INTREG_R10);
285  r.gpr[11] = context->readIntReg(INTREG_R11);
286  r.gpr[12] = context->readIntReg(INTREG_R12);
287  r.gpr[13] = context->readIntReg(INTREG_SP);
288  r.gpr[14] = context->readIntReg(INTREG_LR);
289  r.gpr[15] = context->pcState().pc();
291 
292  // One day somebody will implement transfer of FPRs correctly.
293  for (int i = 0; i < 32; i++)
294  r.fpr[i] = 0;
295 
297 }
298 
299 void
301 {
302  DPRINTF(GDBAcc, "setRegs in remotegdb \n");
303 
304  context->setIntReg(INTREG_R0, r.gpr[0]);
305  context->setIntReg(INTREG_R1, r.gpr[1]);
306  context->setIntReg(INTREG_R2, r.gpr[2]);
307  context->setIntReg(INTREG_R3, r.gpr[3]);
308  context->setIntReg(INTREG_R4, r.gpr[4]);
309  context->setIntReg(INTREG_R5, r.gpr[5]);
310  context->setIntReg(INTREG_R6, r.gpr[6]);
311  context->setIntReg(INTREG_R7, r.gpr[7]);
312  context->setIntReg(INTREG_R8, r.gpr[8]);
313  context->setIntReg(INTREG_R9, r.gpr[9]);
314  context->setIntReg(INTREG_R10, r.gpr[10]);
315  context->setIntReg(INTREG_R11, r.gpr[11]);
316  context->setIntReg(INTREG_R12, r.gpr[12]);
317  context->setIntReg(INTREG_SP, r.gpr[13]);
318  context->setIntReg(INTREG_LR, r.gpr[14]);
319  auto pc_state = context->pcState();
320  pc_state.set(r.gpr[15]);
321  context->pcState(pc_state);
322 
323  // One day somebody will implement transfer of FPRs correctly.
324 
327 }
328 
329 bool
330 RemoteGDB::getXferFeaturesRead(const std::string &annex, std::string &output)
331 {
332 #define GDB_XML(x, s) \
333  { x, std::string(reinterpret_cast<const char *>(Blobs::s), \
334  Blobs::s ## _len) }
335  static const std::map<std::string, std::string> annexMap32{
336  GDB_XML("target.xml", gdb_xml_arm_target),
337  GDB_XML("arm-core.xml", gdb_xml_arm_core),
338  GDB_XML("arm-vfpv3.xml", gdb_xml_arm_vfpv3),
339  };
340  static const std::map<std::string, std::string> annexMap64{
341  GDB_XML("target.xml", gdb_xml_aarch64_target),
342  GDB_XML("aarch64-core.xml", gdb_xml_aarch64_core),
343  GDB_XML("aarch64-fpu.xml", gdb_xml_aarch64_fpu),
344  };
345 #undef GDB_XML
346  auto& annexMap = inAArch64(context()) ? annexMap64 : annexMap32;
347  auto it = annexMap.find(annex);
348  if (it == annexMap.end())
349  return false;
350  output = it->second;
351  return true;
352 }
353 
356 {
357  if (inAArch64(context()))
358  return &regCache64;
359  else
360  return &regCache32;
361 }
ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
ArmISA::INTREG_R4
@ INTREG_R4
Definition: intregs.hh:58
output
static void output(const char *filename)
Definition: debug.cc:60
socket.hh
thread_state.hh
system.hh
remote_gdb.hh
BaseTLB::Read
@ Read
Definition: tlb.hh:57
ArmISA::INTREG_R2
@ INTREG_R2
Definition: intregs.hh:56
ArmISA::INTREG_R8
@ INTREG_R8
Definition: intregs.hh:62
ThreadContext::getWritableVecReg
virtual VecRegContainer & getWritableVecReg(const RegId &reg)=0
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
ArmISA::INTREG_R9
@ INTREG_R9
Definition: intregs.hh:63
ArmISA::RemoteGDB::AArch64GdbRegCache::v
VecElem v[NumVecV8ArchRegs *NumVecElemPerNeonVecReg]
Definition: remote_gdb.hh:96
remote_gdb.hh
pagetable.hh
ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs
void getRegs(ThreadContext *)
Fill the raw buffer from the registers in the ThreadContext.
Definition: remote_gdb.cc:218
ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: miscregs.hh:614
ArmISA::INTREG_LR
@ INTREG_LR
Definition: intregs.hh:70
tlb.hh
ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
ArmISA::RemoteGDB::regCache64
AArch64GdbRegCache regCache64
Definition: remote_gdb.hh:113
Process::pTable
EmulationPageTable * pTable
Definition: process.hh:174
X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:132
ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
system.hh
ArmISA::NumVecV8ArchRegs
const int NumVecV8ArchRegs
Definition: registers.hh:94
ArmISA
Definition: ccregs.hh:41
ArmISA::INTREG_SP
@ INTREG_SP
Definition: intregs.hh:68
EmulationPageTable::lookup
const Entry * lookup(Addr vaddr)
Lookup function.
Definition: page_table.cc:130
RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:75
ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs
void getRegs(ThreadContext *)
Fill the raw buffer from the registers in the ThreadContext.
Definition: remote_gdb.cc:270
ArmISA::INTREG_SPX
@ INTREG_SPX
Definition: intregs.hh:160
ArmISA::INTREG_R10
@ INTREG_R10
Definition: intregs.hh:64
BaseRemoteGDB::context
ThreadContext * context()
Definition: remote_gdb.hh:304
ArmISA::j
Bitfield< 24 > j
Definition: miscregs_types.hh:54
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
ArmISA::INTREG_R0
@ INTREG_R0
Definition: intregs.hh:54
ArmISA::INTREG_R6
@ INTREG_R6
Definition: intregs.hh:60
System
Definition: system.hh:73
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
ArmISA::INTREG_R1
@ INTREG_R1
Definition: intregs.hh:55
ArmISA::INTREG_R12
@ INTREG_R12
Definition: intregs.hh:66
MipsISA::r
r
Definition: pra_constants.hh:95
BaseTLB::translateFunctional
virtual Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
Definition: tlb.hh:96
ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs
void setRegs(ThreadContext *) const
Set the ThreadContext's registers from the values in the raw buffer.
Definition: remote_gdb.cc:300
port.hh
ThreadContext::readVecReg
virtual const VecRegContainer & readVecReg(const RegId &reg) const =0
GDB_XML
#define GDB_XML(x, s)
ArmISA::INTREG_R7
@ INTREG_R7
Definition: intregs.hh:61
static_inst.hh
ArmISA::INTREG_X0
@ INTREG_X0
Definition: intregs.hh:127
ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs
void setRegs(ThreadContext *) const
Set the ThreadContext's registers from the values in the raw buffer.
Definition: remote_gdb.cc:241
NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:245
BaseRemoteGDB
Definition: remote_gdb.hh:43
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ChunkGenerator::done
bool done() const
Are we done? That is, did the last call to next() advance past the end of the region?
Definition: chunk_generator.hh:137
BaseGdbRegCache
Concrete subclasses of this abstract class represent how the register values are transmitted on the w...
Definition: remote_gdb.hh:70
utility.hh
ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: miscregs.hh:68
ThreadContext::getITBPtr
virtual BaseTLB * getITBPtr()=0
full_system.hh
ArmISA::RemoteGDB::getXferFeaturesRead
bool getXferFeaturesRead(const std::string &annex, std::string &output)
Get an XML target description.
Definition: remote_gdb.cc:330
ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
tryTranslate
static bool tryTranslate(ThreadContext *tc, Addr addr)
Definition: remote_gdb.cc:170
VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:56
ArmISA::PageBytes
const Addr PageBytes
Definition: isa_traits.hh:52
ArmISA::RemoteGDB::gdbRegs
BaseGdbRegCache * gdbRegs()
Definition: remote_gdb.cc:355
ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: miscregs.hh:57
ArmISA::RemoteGDB::AArch64GdbRegCache::r
struct ArmISA::RemoteGDB::AArch64GdbRegCache::@4 r
ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: miscregs.hh:613
ArmISA::INTREG_R3
@ INTREG_R3
Definition: intregs.hh:57
ArmISA::RemoteGDB::acc
bool acc(Addr addr, size_t len)
Definition: remote_gdb.cc:198
std
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:587
registers.hh
ArmISA::NumVecElemPerNeonVecReg
constexpr unsigned NumVecElemPerNeonVecReg
Definition: registers.hh:64
ArmISA::len
Bitfield< 18, 16 > len
Definition: miscregs_types.hh:439
physical.hh
ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
addr
ip6_addr_t addr
Definition: inet.hh:423
chunk_generator.hh
ChunkGenerator
This class takes an arbitrary memory region (address/length pair) and generates a series of appropria...
Definition: chunk_generator.hh:55
trace.hh
ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
intmath.hh
ArmISA::RemoteGDB::regCache32
AArch32GdbRegCache regCache32
Definition: remote_gdb.hh:112
ArmISA::INTREG_R11
@ INTREG_R11
Definition: intregs.hh:65
ArmISA::inAArch64
bool inAArch64(ThreadContext *tc)
Definition: utility.cc:222
ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
decoder.hh
page_table.hh
ArmISA::v
Bitfield< 28 > v
Definition: miscregs_types.hh:51
ArmISA::INTREG_R5
@ INTREG_R5
Definition: intregs.hh:59
thread_context.hh
ThreadContext::getDTBPtr
virtual BaseTLB * getDTBPtr()=0
ArmISA::va
Bitfield< 8 > va
Definition: miscregs_types.hh:272

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