gem5  v20.1.0.0
Public Member Functions | Public Attributes | Protected Types | List of all members
SimpleExecContext Class Reference

#include <exec_context.hh>

Inheritance diagram for SimpleExecContext:
ExecContext

Public Member Functions

 SimpleExecContext (BaseSimpleCPU *_cpu, SimpleThread *_thread)
 Constructor. More...
 
RegVal readIntRegOperand (const StaticInst *si, int idx) override
 Reads an integer register. More...
 
void setIntRegOperand (const StaticInst *si, int idx, RegVal val) override
 Sets an integer register to a value. More...
 
RegVal readFloatRegOperandBits (const StaticInst *si, int idx) override
 Reads a floating point register in its binary format, instead of by value. More...
 
void setFloatRegOperandBits (const StaticInst *si, int idx, RegVal val) override
 Sets the bits of a floating point register of single width to a binary value. More...
 
const VecRegContainerreadVecRegOperand (const StaticInst *si, int idx) const override
 Reads a vector register. More...
 
VecRegContainergetWritableVecRegOperand (const StaticInst *si, int idx) override
 Reads a vector register for modification. More...
 
void setVecRegOperand (const StaticInst *si, int idx, const VecRegContainer &val) override
 Sets a vector register to a value. More...
 
VecElem readVecElemOperand (const StaticInst *si, int idx) const override
 Reads an element of a vector register. More...
 
void setVecElemOperand (const StaticInst *si, int idx, const VecElem val) override
 Sets an element of a vector register to a value. More...
 
const VecPredRegContainerreadVecPredRegOperand (const StaticInst *si, int idx) const override
 Predicate registers interface. More...
 
VecPredRegContainergetWritableVecPredRegOperand (const StaticInst *si, int idx) override
 Gets destination predicate register operand for modification. More...
 
void setVecPredRegOperand (const StaticInst *si, int idx, const VecPredRegContainer &val) override
 Sets a destination predicate register operand to a value. More...
 
RegVal readCCRegOperand (const StaticInst *si, int idx) override
 
void setCCRegOperand (const StaticInst *si, int idx, RegVal val) override
 
RegVal readMiscRegOperand (const StaticInst *si, int idx) override
 
void setMiscRegOperand (const StaticInst *si, int idx, RegVal val) override
 
RegVal readMiscReg (int misc_reg) override
 Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...
 
void setMiscReg (int misc_reg, RegVal val) override
 Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...
 
PCState pcState () const override
 
void pcState (const PCState &val) override
 
Fault readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override
 Perform an atomic memory read operation. More...
 
Fault initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override
 Initiate a timing memory read operation. More...
 
Fault writeMem (uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >()) override
 For atomic-mode contexts, perform an atomic memory write operation. More...
 
Fault amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
 For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More...
 
Fault initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
 For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More...
 
Fault initiateHtmCmd (Request::Flags flags) override
 Initiate an HTM command, e.g. More...
 
void setStCondFailures (unsigned int sc_failures) override
 Sets the number of consecutive store conditional failures. More...
 
unsigned int readStCondFailures () const override
 Returns the number of consecutive store conditional failures. More...
 
void syscall () override
 Executes a syscall specified by the callnum. More...
 
ThreadContexttcBase () const override
 Returns a pointer to the ThreadContext. More...
 
bool readPredicate () const override
 
void setPredicate (bool val) override
 
bool readMemAccPredicate () const override
 
void setMemAccPredicate (bool val) override
 
uint64_t getHtmTransactionUid () const override
 
uint64_t newHtmTransactionUid () const override
 
bool inHtmTransactionalState () const override
 
uint64_t getHtmTransactionalDepth () const override
 
void demapPage (Addr vaddr, uint64_t asn) override
 Invalidate a page in the DTLB and ITLB. More...
 
void armMonitor (Addr address) override
 
bool mwait (PacketPtr pkt) override
 
void mwaitAtomic (ThreadContext *tc) override
 
AddressMonitorgetAddrMonitor () override
 
template<typename VecElem >
VecLaneT< VecElem, true > readVecLaneOperand (const StaticInst *si, int idx) const
 Vector Register Lane Interfaces. More...
 
virtual ConstVecLane8 readVec8BitLaneOperand (const StaticInst *si, int idx) const override
 Reads source vector 8bit operand. More...
 
virtual ConstVecLane16 readVec16BitLaneOperand (const StaticInst *si, int idx) const override
 Reads source vector 16bit operand. More...
 
virtual ConstVecLane32 readVec32BitLaneOperand (const StaticInst *si, int idx) const override
 Reads source vector 32bit operand. More...
 
virtual ConstVecLane64 readVec64BitLaneOperand (const StaticInst *si, int idx) const override
 Reads source vector 64bit operand. More...
 
template<typename LD >
void setVecLaneOperandT (const StaticInst *si, int idx, const LD &val)
 Write a lane of the destination vector operand. More...
 
virtual void setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::Byte > &val) override
 Write a lane of the destination vector operand. More...
 
virtual void setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::TwoByte > &val) override
 Write a lane of the destination vector operand. More...
 
virtual void setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::FourByte > &val) override
 Write a lane of the destination vector operand. More...
 
virtual void setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::EightByte > &val) override
 Write a lane of the destination vector operand. More...
 
Integer Register Interfaces
Floating Point Register Interfaces
Condition Code Registers
Misc Register Interfaces
PC Control
Memory Interface
SysCall Emulation Interfaces
ARM-Specific Interfaces
X86-Specific Interfaces

Public Attributes

BaseSimpleCPUcpu
 
SimpleThreadthread
 
Addr fetchOffset
 
bool stayAtPC
 
TheISA::PCState predPC
 
Counter numInst
 PER-THREAD STATS. More...
 
Stats::Scalar numInsts
 
Counter numOp
 
Stats::Scalar numOps
 
Stats::Scalar numIntAluAccesses
 
Stats::Scalar numFpAluAccesses
 
Stats::Scalar numVecAluAccesses
 
Stats::Scalar numCallsReturns
 
Stats::Scalar numCondCtrlInsts
 
Stats::Scalar numIntInsts
 
Stats::Scalar numFpInsts
 
Stats::Scalar numVecInsts
 
Stats::Scalar numIntRegReads
 
Stats::Scalar numIntRegWrites
 
Stats::Scalar numFpRegReads
 
Stats::Scalar numFpRegWrites
 
Stats::Scalar numVecRegReads
 
Stats::Scalar numVecRegWrites
 
Stats::Scalar numVecPredRegReads
 
Stats::Scalar numVecPredRegWrites
 
Stats::Scalar numCCRegReads
 
Stats::Scalar numCCRegWrites
 
Stats::Scalar numMemRefs
 
Stats::Scalar numLoadInsts
 
Stats::Scalar numStoreInsts
 
Stats::Formula numIdleCycles
 
Stats::Formula numBusyCycles
 
Counter numLoad
 
Stats::Average notIdleFraction
 
Stats::Formula idleFraction
 
Stats::Scalar icacheStallCycles
 
Counter lastIcacheStall
 
Stats::Scalar dcacheStallCycles
 
Counter lastDcacheStall
 
Stats::Vector statExecutedInstType
 
Stats::Scalar numBranches
 
Stats::Scalar numPredictedBranches
 Number of branches predicted as taken. More...
 
Stats::Scalar numBranchMispred
 Number of misprediced branches. More...
 

Protected Types

using VecRegContainer = TheISA::VecRegContainer
 
using VecElem = TheISA::VecElem
 

Additional Inherited Members

- Public Types inherited from ExecContext
typedef TheISA::PCState PCState
 
using VecRegContainer = TheISA::VecRegContainer
 
using VecElem = TheISA::VecElem
 
using VecPredRegContainer = TheISA::VecPredRegContainer
 

Detailed Description

Definition at line 57 of file exec_context.hh.

Member Typedef Documentation

◆ VecElem

using SimpleExecContext::VecElem = TheISA::VecElem
protected

Definition at line 60 of file exec_context.hh.

◆ VecRegContainer

using SimpleExecContext::VecRegContainer = TheISA::VecRegContainer
protected

Definition at line 59 of file exec_context.hh.

Constructor & Destructor Documentation

◆ SimpleExecContext()

SimpleExecContext::SimpleExecContext ( BaseSimpleCPU _cpu,
SimpleThread _thread 
)
inline

Constructor.

Definition at line 167 of file exec_context.hh.

Member Function Documentation

◆ amoMem()

Fault SimpleExecContext::amoMem ( Addr  addr,
uint8_t *  data,
unsigned int  size,
Request::Flags  flags,
AtomicOpFunctorPtr  amo_op 
)
inlineoverridevirtual

For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)

Reimplemented from ExecContext.

Definition at line 463 of file exec_context.hh.

References addr, BaseSimpleCPU::amoMem(), cpu, and data.

◆ armMonitor()

void SimpleExecContext::armMonitor ( Addr  address)
inlineoverridevirtual

Implements ExecContext.

Definition at line 570 of file exec_context.hh.

References BaseCPU::armMonitor(), cpu, thread, and SimpleThread::threadId().

◆ demapPage()

void SimpleExecContext::demapPage ( Addr  vaddr,
uint64_t  asn 
)
inlineoverridevirtual

Invalidate a page in the DTLB and ITLB.

Implements ExecContext.

Definition at line 564 of file exec_context.hh.

References SimpleThread::demapPage(), thread, and MipsISA::vaddr.

◆ getAddrMonitor()

AddressMonitor* SimpleExecContext::getAddrMonitor ( )
inlineoverridevirtual

Implements ExecContext.

Definition at line 588 of file exec_context.hh.

References cpu, BaseCPU::getCpuAddrMonitor(), thread, and SimpleThread::threadId().

◆ getHtmTransactionalDepth()

uint64_t SimpleExecContext::getHtmTransactionalDepth ( ) const
inlineoverridevirtual

◆ getHtmTransactionUid()

uint64_t SimpleExecContext::getHtmTransactionUid ( ) const
inlineoverridevirtual

◆ getWritableVecPredRegOperand()

VecPredRegContainer& SimpleExecContext::getWritableVecPredRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Gets destination predicate register operand for modification.

Implements ExecContext.

Definition at line 345 of file exec_context.hh.

References SimpleThread::getWritableVecPredReg(), numVecPredRegWrites, X86ISA::reg, ArmISA::si, and thread.

◆ getWritableVecRegOperand()

VecRegContainer& SimpleExecContext::getWritableVecRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Reads a vector register for modification.

Implements ExecContext.

Definition at line 226 of file exec_context.hh.

References SimpleThread::getWritableVecReg(), numVecRegWrites, X86ISA::reg, ArmISA::si, and thread.

◆ inHtmTransactionalState()

bool SimpleExecContext::inHtmTransactionalState ( ) const
inlineoverridevirtual

◆ initiateHtmCmd()

Fault SimpleExecContext::initiateHtmCmd ( Request::Flags  flags)
inlineoverridevirtual

Initiate an HTM command, e.g.

tell Ruby we're starting/stopping a transaction

Implements ExecContext.

Definition at line 476 of file exec_context.hh.

References cpu, and BaseSimpleCPU::initiateHtmCmd().

◆ initiateMemAMO()

Fault SimpleExecContext::initiateMemAMO ( Addr  addr,
unsigned int  size,
Request::Flags  flags,
AtomicOpFunctorPtr  amo_op 
)
inlineoverridevirtual

For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)

Reimplemented from ExecContext.

Definition at line 469 of file exec_context.hh.

References addr, cpu, and BaseSimpleCPU::initiateMemAMO().

◆ initiateMemRead()

Fault SimpleExecContext::initiateMemRead ( Addr  addr,
unsigned int  size,
Request::Flags  flags,
const std::vector< bool > &  byte_enable = std::vector<bool>() 
)
inlineoverridevirtual

Initiate a timing memory read operation.

Must be overridden for exec contexts that support timing memory mode. Not pure virtual since exec contexts that only support atomic memory mode need not override (though in that case this function should never be called).

Reimplemented from ExecContext.

Definition at line 444 of file exec_context.hh.

References addr, cpu, and BaseSimpleCPU::initiateMemRead().

◆ mwait()

bool SimpleExecContext::mwait ( PacketPtr  pkt)
inlineoverridevirtual

Implements ExecContext.

Definition at line 576 of file exec_context.hh.

References cpu, BaseCPU::mwait(), thread, and SimpleThread::threadId().

◆ mwaitAtomic()

void SimpleExecContext::mwaitAtomic ( ThreadContext tc)
inlineoverridevirtual

Implements ExecContext.

Definition at line 582 of file exec_context.hh.

References cpu, SimpleThread::dtb, BaseCPU::mwaitAtomic(), thread, and SimpleThread::threadId().

◆ newHtmTransactionUid()

uint64_t SimpleExecContext::newHtmTransactionUid ( ) const
inlineoverridevirtual

Implements ExecContext.

Definition at line 542 of file exec_context.hh.

References ThreadContext::getHtmCheckpointPtr(), and tcBase().

Referenced by TimingSimpleCPU::completeIfetch().

◆ pcState() [1/2]

PCState SimpleExecContext::pcState ( ) const
inlineoverridevirtual

Implements ExecContext.

Definition at line 422 of file exec_context.hh.

References SimpleThread::pcState(), and thread.

◆ pcState() [2/2]

void SimpleExecContext::pcState ( const PCState val)
inlineoverridevirtual

Implements ExecContext.

Definition at line 428 of file exec_context.hh.

References SimpleThread::pcState(), thread, and X86ISA::val.

◆ readCCRegOperand()

RegVal SimpleExecContext::readCCRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Implements ExecContext.

Definition at line 364 of file exec_context.hh.

References numCCRegReads, SimpleThread::readCCReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readFloatRegOperandBits()

RegVal SimpleExecContext::readFloatRegOperandBits ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Reads a floating point register in its binary format, instead of by value.

Implements ExecContext.

Definition at line 195 of file exec_context.hh.

References numFpRegReads, SimpleThread::readFloatReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readIntRegOperand()

RegVal SimpleExecContext::readIntRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Reads an integer register.

Implements ExecContext.

Definition at line 174 of file exec_context.hh.

References numIntRegReads, SimpleThread::readIntReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readMem()

Fault SimpleExecContext::readMem ( Addr  addr,
uint8_t *  data,
unsigned int  size,
Request::Flags  flags,
const std::vector< bool > &  byte_enable = std::vector<bool>() 
)
inlineoverridevirtual

Perform an atomic memory read operation.

Must be overridden for exec contexts that support atomic memory mode. Not pure virtual since exec contexts that only support timing memory mode need not override (though in that case this function should never be called).

Reimplemented from ExecContext.

Definition at line 434 of file exec_context.hh.

References addr, cpu, data, and BaseSimpleCPU::readMem().

◆ readMemAccPredicate()

bool SimpleExecContext::readMemAccPredicate ( ) const
inlineoverridevirtual

Implements ExecContext.

Definition at line 524 of file exec_context.hh.

References SimpleThread::readMemAccPredicate(), and thread.

◆ readMiscReg()

RegVal SimpleExecContext::readMiscReg ( int  misc_reg)
inlineoverridevirtual

Reads a miscellaneous register, handling any architectural side effects due to reading that register.

Implements ExecContext.

Definition at line 404 of file exec_context.hh.

References numIntRegReads, SimpleThread::readMiscReg(), and thread.

◆ readMiscRegOperand()

RegVal SimpleExecContext::readMiscRegOperand ( const StaticInst si,
int  idx 
)
inlineoverridevirtual

Implements ExecContext.

Definition at line 382 of file exec_context.hh.

References numIntRegReads, SimpleThread::readMiscReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readPredicate()

bool SimpleExecContext::readPredicate ( ) const
inlineoverridevirtual

Implements ExecContext.

Definition at line 508 of file exec_context.hh.

References SimpleThread::readPredicate(), and thread.

◆ readStCondFailures()

unsigned int SimpleExecContext::readStCondFailures ( ) const
inlineoverridevirtual

Returns the number of consecutive store conditional failures.

Implements ExecContext.

Definition at line 494 of file exec_context.hh.

References SimpleThread::readStCondFailures(), and thread.

◆ readVec16BitLaneOperand()

virtual ConstVecLane16 SimpleExecContext::readVec16BitLaneOperand ( const StaticInst si,
int  idx 
) const
inlineoverridevirtual

Reads source vector 16bit operand.

Implements ExecContext.

Definition at line 265 of file exec_context.hh.

References ArmISA::si.

◆ readVec32BitLaneOperand()

virtual ConstVecLane32 SimpleExecContext::readVec32BitLaneOperand ( const StaticInst si,
int  idx 
) const
inlineoverridevirtual

Reads source vector 32bit operand.

Implements ExecContext.

Definition at line 271 of file exec_context.hh.

References ArmISA::si.

◆ readVec64BitLaneOperand()

virtual ConstVecLane64 SimpleExecContext::readVec64BitLaneOperand ( const StaticInst si,
int  idx 
) const
inlineoverridevirtual

Reads source vector 64bit operand.

Implements ExecContext.

Definition at line 277 of file exec_context.hh.

References ArmISA::si.

◆ readVec8BitLaneOperand()

virtual ConstVecLane8 SimpleExecContext::readVec8BitLaneOperand ( const StaticInst si,
int  idx 
) const
inlineoverridevirtual

Reads source vector 8bit operand.

Implements ExecContext.

Definition at line 259 of file exec_context.hh.

References ArmISA::si.

◆ readVecElemOperand()

VecElem SimpleExecContext::readVecElemOperand ( const StaticInst si,
int  idx 
) const
inlineoverridevirtual

Reads an element of a vector register.

Implements ExecContext.

Definition at line 316 of file exec_context.hh.

References numVecRegReads, SimpleThread::readVecElem(), X86ISA::reg, ArmISA::si, and thread.

◆ readVecLaneOperand()

template<typename VecElem >
VecLaneT<VecElem, true> SimpleExecContext::readVecLaneOperand ( const StaticInst si,
int  idx 
) const
inline

Vector Register Lane Interfaces.

Reads source vector lane.

Definition at line 250 of file exec_context.hh.

References numVecRegReads, SimpleThread::readVecLane(), X86ISA::reg, ArmISA::si, and thread.

◆ readVecPredRegOperand()

const VecPredRegContainer& SimpleExecContext::readVecPredRegOperand ( const StaticInst si,
int  idx 
) const
inlineoverridevirtual

Predicate registers interface.

Reads source predicate register operand.

Implements ExecContext.

Definition at line 336 of file exec_context.hh.

References numVecPredRegReads, SimpleThread::readVecPredReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readVecRegOperand()

const VecRegContainer& SimpleExecContext::readVecRegOperand ( const StaticInst si,
int  idx 
) const
inlineoverridevirtual

Reads a vector register.

Implements ExecContext.

Definition at line 216 of file exec_context.hh.

References numVecRegReads, SimpleThread::readVecReg(), X86ISA::reg, ArmISA::si, and thread.

◆ setCCRegOperand()

void SimpleExecContext::setCCRegOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

Implements ExecContext.

Definition at line 373 of file exec_context.hh.

References numCCRegWrites, X86ISA::reg, SimpleThread::setCCReg(), ArmISA::si, thread, and X86ISA::val.

◆ setFloatRegOperandBits()

void SimpleExecContext::setFloatRegOperandBits ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

Sets the bits of a floating point register of single width to a binary value.

Implements ExecContext.

Definition at line 206 of file exec_context.hh.

References numFpRegWrites, X86ISA::reg, SimpleThread::setFloatReg(), ArmISA::si, thread, and X86ISA::val.

◆ setIntRegOperand()

void SimpleExecContext::setIntRegOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

Sets an integer register to a value.

Implements ExecContext.

Definition at line 184 of file exec_context.hh.

References numIntRegWrites, X86ISA::reg, SimpleThread::setIntReg(), ArmISA::si, thread, and X86ISA::val.

◆ setMemAccPredicate()

void SimpleExecContext::setMemAccPredicate ( bool  val)
inlineoverridevirtual

Implements ExecContext.

Definition at line 530 of file exec_context.hh.

References SimpleThread::setMemAccPredicate(), thread, and X86ISA::val.

Referenced by BaseSimpleCPU::preExecute().

◆ setMiscReg()

void SimpleExecContext::setMiscReg ( int  misc_reg,
RegVal  val 
)
inlineoverridevirtual

Sets a miscellaneous register, handling any architectural side effects due to writing that register.

Implements ExecContext.

Definition at line 415 of file exec_context.hh.

References numIntRegWrites, SimpleThread::setMiscReg(), thread, and X86ISA::val.

◆ setMiscRegOperand()

void SimpleExecContext::setMiscRegOperand ( const StaticInst si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

◆ setPredicate()

void SimpleExecContext::setPredicate ( bool  val)
inlineoverridevirtual

◆ setStCondFailures()

void SimpleExecContext::setStCondFailures ( unsigned int  sc_failures)
inlineoverridevirtual

Sets the number of consecutive store conditional failures.

Implements ExecContext.

Definition at line 485 of file exec_context.hh.

References SimpleThread::setStCondFailures(), and thread.

◆ setVecElemOperand()

void SimpleExecContext::setVecElemOperand ( const StaticInst si,
int  idx,
const VecElem  val 
)
inlineoverridevirtual

Sets an element of a vector register to a value.

Implements ExecContext.

Definition at line 326 of file exec_context.hh.

References numVecRegWrites, X86ISA::reg, SimpleThread::setVecElem(), ArmISA::si, thread, and X86ISA::val.

◆ setVecLaneOperand() [1/4]

virtual void SimpleExecContext::setVecLaneOperand ( const StaticInst si,
int  idx,
const LaneData< LaneSize::Byte > &  val 
)
inlineoverridevirtual

Write a lane of the destination vector operand.

Implements ExecContext.

Definition at line 294 of file exec_context.hh.

References setVecLaneOperandT(), ArmISA::si, and X86ISA::val.

◆ setVecLaneOperand() [2/4]

virtual void SimpleExecContext::setVecLaneOperand ( const StaticInst si,
int  idx,
const LaneData< LaneSize::EightByte > &  val 
)
inlineoverridevirtual

Write a lane of the destination vector operand.

Implements ExecContext.

Definition at line 309 of file exec_context.hh.

References setVecLaneOperandT(), ArmISA::si, and X86ISA::val.

◆ setVecLaneOperand() [3/4]

virtual void SimpleExecContext::setVecLaneOperand ( const StaticInst si,
int  idx,
const LaneData< LaneSize::FourByte > &  val 
)
inlineoverridevirtual

Write a lane of the destination vector operand.

Implements ExecContext.

Definition at line 304 of file exec_context.hh.

References setVecLaneOperandT(), ArmISA::si, and X86ISA::val.

◆ setVecLaneOperand() [4/4]

virtual void SimpleExecContext::setVecLaneOperand ( const StaticInst si,
int  idx,
const LaneData< LaneSize::TwoByte > &  val 
)
inlineoverridevirtual

Write a lane of the destination vector operand.

Implements ExecContext.

Definition at line 299 of file exec_context.hh.

References setVecLaneOperandT(), ArmISA::si, and X86ISA::val.

◆ setVecLaneOperandT()

template<typename LD >
void SimpleExecContext::setVecLaneOperandT ( const StaticInst si,
int  idx,
const LD &  val 
)
inline

Write a lane of the destination vector operand.

Definition at line 284 of file exec_context.hh.

References numVecRegWrites, X86ISA::reg, SimpleThread::setVecLane(), ArmISA::si, thread, and X86ISA::val.

Referenced by setVecLaneOperand().

◆ setVecPredRegOperand()

void SimpleExecContext::setVecPredRegOperand ( const StaticInst si,
int  idx,
const VecPredRegContainer val 
)
inlineoverridevirtual

Sets a destination predicate register operand to a value.

Implements ExecContext.

Definition at line 354 of file exec_context.hh.

References numVecPredRegWrites, X86ISA::reg, SimpleThread::setVecPredReg(), ArmISA::si, thread, and X86ISA::val.

◆ setVecRegOperand()

void SimpleExecContext::setVecRegOperand ( const StaticInst si,
int  idx,
const VecRegContainer val 
)
inlineoverridevirtual

Sets a vector register to a value.

Implements ExecContext.

Definition at line 236 of file exec_context.hh.

References numVecRegWrites, X86ISA::reg, SimpleThread::setVecReg(), ArmISA::si, thread, and X86ISA::val.

◆ syscall()

void SimpleExecContext::syscall ( )
inlineoverridevirtual

Executes a syscall specified by the callnum.

Implements ExecContext.

Definition at line 502 of file exec_context.hh.

References SimpleThread::syscall(), and thread.

◆ tcBase()

ThreadContext* SimpleExecContext::tcBase ( ) const
inlineoverridevirtual

Returns a pointer to the ThreadContext.

Implements ExecContext.

Definition at line 505 of file exec_context.hh.

References SimpleThread::getTC(), and thread.

Referenced by getHtmTransactionUid(), and newHtmTransactionUid().

◆ writeMem()

Fault SimpleExecContext::writeMem ( uint8_t *  data,
unsigned int  size,
Addr  addr,
Request::Flags  flags,
uint64_t *  res,
const std::vector< bool > &  byte_enable = std::vector< bool >() 
)
inlineoverridevirtual

For atomic-mode contexts, perform an atomic memory write operation.

For timing-mode contexts, initiate a timing memory write operation.

Implements ExecContext.

Definition at line 454 of file exec_context.hh.

References addr, cpu, data, and BaseSimpleCPU::writeMem().

Member Data Documentation

◆ cpu

BaseSimpleCPU* SimpleExecContext::cpu

◆ dcacheStallCycles

Stats::Scalar SimpleExecContext::dcacheStallCycles

Definition at line 150 of file exec_context.hh.

Referenced by BaseSimpleCPU::regStats().

◆ fetchOffset

Addr SimpleExecContext::fetchOffset

◆ icacheStallCycles

Stats::Scalar SimpleExecContext::icacheStallCycles

Definition at line 146 of file exec_context.hh.

Referenced by BaseSimpleCPU::regStats().

◆ idleFraction

Stats::Formula SimpleExecContext::idleFraction

Definition at line 143 of file exec_context.hh.

Referenced by BaseSimpleCPU::regStats().

◆ lastDcacheStall

Counter SimpleExecContext::lastDcacheStall

Definition at line 151 of file exec_context.hh.

◆ lastIcacheStall

Counter SimpleExecContext::lastIcacheStall

Definition at line 147 of file exec_context.hh.

◆ notIdleFraction

Stats::Average SimpleExecContext::notIdleFraction

Definition at line 142 of file exec_context.hh.

Referenced by BaseSimpleCPU::regStats().

◆ numBranches

Stats::Scalar SimpleExecContext::numBranches

Total number of branches fetched

Definition at line 155 of file exec_context.hh.

Referenced by BaseSimpleCPU::postExecute(), and BaseSimpleCPU::regStats().

◆ numBranchMispred

Stats::Scalar SimpleExecContext::numBranchMispred

Number of misprediced branches.

Definition at line 159 of file exec_context.hh.

Referenced by BaseSimpleCPU::advancePC(), and BaseSimpleCPU::regStats().

◆ numBusyCycles

Stats::Formula SimpleExecContext::numBusyCycles

Definition at line 136 of file exec_context.hh.

Referenced by BaseSimpleCPU::regStats().

◆ numCallsReturns

Stats::Scalar SimpleExecContext::numCallsReturns

Definition at line 93 of file exec_context.hh.

Referenced by BaseSimpleCPU::postExecute(), and BaseSimpleCPU::regStats().

◆ numCCRegReads

Stats::Scalar SimpleExecContext::numCCRegReads

Definition at line 124 of file exec_context.hh.

Referenced by readCCRegOperand(), and BaseSimpleCPU::regStats().

◆ numCCRegWrites

Stats::Scalar SimpleExecContext::numCCRegWrites

Definition at line 125 of file exec_context.hh.

Referenced by BaseSimpleCPU::regStats(), and setCCRegOperand().

◆ numCondCtrlInsts

Stats::Scalar SimpleExecContext::numCondCtrlInsts

Definition at line 96 of file exec_context.hh.

Referenced by BaseSimpleCPU::postExecute(), and BaseSimpleCPU::regStats().

◆ numFpAluAccesses

Stats::Scalar SimpleExecContext::numFpAluAccesses

Definition at line 87 of file exec_context.hh.

Referenced by BaseSimpleCPU::postExecute(), and BaseSimpleCPU::regStats().

◆ numFpInsts

Stats::Scalar SimpleExecContext::numFpInsts

Definition at line 102 of file exec_context.hh.

Referenced by BaseSimpleCPU::postExecute(), and BaseSimpleCPU::regStats().

◆ numFpRegReads

Stats::Scalar SimpleExecContext::numFpRegReads

Definition at line 112 of file exec_context.hh.

Referenced by readFloatRegOperandBits(), and BaseSimpleCPU::regStats().

◆ numFpRegWrites

Stats::Scalar SimpleExecContext::numFpRegWrites

Definition at line 113 of file exec_context.hh.

Referenced by BaseSimpleCPU::regStats(), and setFloatRegOperandBits().

◆ numIdleCycles

Stats::Formula SimpleExecContext::numIdleCycles

Definition at line 133 of file exec_context.hh.

Referenced by BaseSimpleCPU::regStats().

◆ numInst

Counter SimpleExecContext::numInst

◆ numInsts

Stats::Scalar SimpleExecContext::numInsts

Definition at line 79 of file exec_context.hh.

Referenced by BaseSimpleCPU::countInst(), and BaseSimpleCPU::regStats().

◆ numIntAluAccesses

Stats::Scalar SimpleExecContext::numIntAluAccesses

Definition at line 84 of file exec_context.hh.

Referenced by BaseSimpleCPU::postExecute(), and BaseSimpleCPU::regStats().

◆ numIntInsts

Stats::Scalar SimpleExecContext::numIntInsts

Definition at line 99 of file exec_context.hh.

Referenced by BaseSimpleCPU::postExecute(), and BaseSimpleCPU::regStats().

◆ numIntRegReads

Stats::Scalar SimpleExecContext::numIntRegReads

◆ numIntRegWrites

Stats::Scalar SimpleExecContext::numIntRegWrites

◆ numLoad

Counter SimpleExecContext::numLoad

Definition at line 139 of file exec_context.hh.

Referenced by BaseSimpleCPU::postExecute().

◆ numLoadInsts

Stats::Scalar SimpleExecContext::numLoadInsts

Definition at line 129 of file exec_context.hh.

Referenced by BaseSimpleCPU::postExecute(), and BaseSimpleCPU::regStats().

◆ numMemRefs

Stats::Scalar SimpleExecContext::numMemRefs

Definition at line 128 of file exec_context.hh.

Referenced by BaseSimpleCPU::postExecute(), and BaseSimpleCPU::regStats().

◆ numOp

Counter SimpleExecContext::numOp

Definition at line 80 of file exec_context.hh.

Referenced by BaseSimpleCPU::countInst().

◆ numOps

Stats::Scalar SimpleExecContext::numOps

Definition at line 81 of file exec_context.hh.

Referenced by BaseSimpleCPU::countInst(), and BaseSimpleCPU::regStats().

◆ numPredictedBranches

Stats::Scalar SimpleExecContext::numPredictedBranches

Number of branches predicted as taken.

Definition at line 157 of file exec_context.hh.

Referenced by BaseSimpleCPU::preExecute(), and BaseSimpleCPU::regStats().

◆ numStoreInsts

Stats::Scalar SimpleExecContext::numStoreInsts

Definition at line 130 of file exec_context.hh.

Referenced by BaseSimpleCPU::postExecute(), and BaseSimpleCPU::regStats().

◆ numVecAluAccesses

Stats::Scalar SimpleExecContext::numVecAluAccesses

Definition at line 90 of file exec_context.hh.

Referenced by BaseSimpleCPU::postExecute(), and BaseSimpleCPU::regStats().

◆ numVecInsts

Stats::Scalar SimpleExecContext::numVecInsts

Definition at line 105 of file exec_context.hh.

Referenced by BaseSimpleCPU::postExecute(), and BaseSimpleCPU::regStats().

◆ numVecPredRegReads

Stats::Scalar SimpleExecContext::numVecPredRegReads
mutable

Definition at line 120 of file exec_context.hh.

Referenced by readVecPredRegOperand().

◆ numVecPredRegWrites

Stats::Scalar SimpleExecContext::numVecPredRegWrites

Definition at line 121 of file exec_context.hh.

Referenced by getWritableVecPredRegOperand(), and setVecPredRegOperand().

◆ numVecRegReads

Stats::Scalar SimpleExecContext::numVecRegReads
mutable

◆ numVecRegWrites

Stats::Scalar SimpleExecContext::numVecRegWrites

◆ predPC

TheISA::PCState SimpleExecContext::predPC

Definition at line 73 of file exec_context.hh.

Referenced by BaseSimpleCPU::advancePC(), and BaseSimpleCPU::preExecute().

◆ statExecutedInstType

Stats::Vector SimpleExecContext::statExecutedInstType

Definition at line 163 of file exec_context.hh.

Referenced by BaseSimpleCPU::postExecute(), and BaseSimpleCPU::regStats().

◆ stayAtPC

bool SimpleExecContext::stayAtPC

◆ thread

SimpleThread* SimpleExecContext::thread

The documentation for this class was generated from the following file:

Generated on Wed Sep 30 2020 14:02:31 for gem5 by doxygen 1.8.17