gem5  v20.1.0.0
vfp.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2010-2013, 2019 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #ifndef __ARCH_ARM_INSTS_VFP_HH__
39 #define __ARCH_ARM_INSTS_VFP_HH__
40 
41 #include <fenv.h>
42 
43 #include <cmath>
44 
45 #include "arch/arm/insts/misc.hh"
46 #include "arch/arm/miscregs.hh"
47 
48 namespace ArmISA
49 {
50 
56 };
57 
58 template<class T>
59 static inline void
61 {
62  switch (mode) {
63  case VfpMicroop:
64  flags[StaticInst::IsMicroop] = true;
65  break;
66  case VfpFirstMicroop:
67  flags[StaticInst::IsMicroop] =
68  flags[StaticInst::IsFirstMicroop] = true;
69  break;
70  case VfpLastMicroop:
71  flags[StaticInst::IsMicroop] =
72  flags[StaticInst::IsLastMicroop] = true;
73  break;
74  case VfpNotAMicroop:
75  break;
76  }
77  if (mode == VfpMicroop || mode == VfpFirstMicroop) {
78  flags[StaticInst::IsDelayedCommit] = true;
79  }
80 }
81 
83 {
84  FeDivByZero = FE_DIVBYZERO,
85  FeInexact = FE_INEXACT,
86  FeInvalid = FE_INVALID,
87  FeOverflow = FE_OVERFLOW,
88  FeUnderflow = FE_UNDERFLOW,
89  FeAllExceptions = FE_ALL_EXCEPT
90 };
91 
93 {
94  FeRoundDown = FE_DOWNWARD,
95  FeRoundNearest = FE_TONEAREST,
96  FeRoundZero = FE_TOWARDZERO,
97  FeRoundUpward = FE_UPWARD
98 };
99 
101 {
107 };
108 
109 static inline float bitsToFp(uint64_t, float);
110 static inline double bitsToFp(uint64_t, double);
111 static inline uint32_t fpToBits(float);
112 static inline uint64_t fpToBits(double);
113 
114 template <class fpType>
115 static inline bool
116 flushToZero(fpType &op)
117 {
118  fpType junk = 0.0;
119  if (std::fpclassify(op) == FP_SUBNORMAL) {
120  uint64_t bitMask = ULL(0x1) << (sizeof(fpType) * 8 - 1);
121  op = bitsToFp(fpToBits(op) & bitMask, junk);
122  return true;
123  }
124  return false;
125 }
126 
127 template <class fpType>
128 static inline bool
129 flushToZero(fpType &op1, fpType &op2)
130 {
131  bool flush1 = flushToZero(op1);
132  bool flush2 = flushToZero(op2);
133  return flush1 || flush2;
134 }
135 
136 template <class fpType>
137 static inline void
138 vfpFlushToZero(FPSCR &fpscr, fpType &op)
139 {
140  if (fpscr.fz == 1 && flushToZero(op)) {
141  fpscr.idc = 1;
142  }
143 }
144 
145 template <class fpType>
146 static inline void
147 vfpFlushToZero(FPSCR &fpscr, fpType &op1, fpType &op2)
148 {
149  vfpFlushToZero(fpscr, op1);
150  vfpFlushToZero(fpscr, op2);
151 }
152 
153 static inline uint32_t
154 fpToBits(float fp)
155 {
156  union
157  {
158  float fp;
159  uint32_t bits;
160  } val;
161  val.fp = fp;
162  return val.bits;
163 }
164 
165 static inline uint64_t
166 fpToBits(double fp)
167 {
168  union
169  {
170  double fp;
171  uint64_t bits;
172  } val;
173  val.fp = fp;
174  return val.bits;
175 }
176 
177 static inline float
178 bitsToFp(uint64_t bits, float junk)
179 {
180  union
181  {
182  float fp;
183  uint32_t bits;
184  } val;
185  val.bits = bits;
186  return val.fp;
187 }
188 
189 static inline double
190 bitsToFp(uint64_t bits, double junk)
191 {
192  union
193  {
194  double fp;
195  uint64_t bits;
196  } val;
197  val.bits = bits;
198  return val.fp;
199 }
200 
201 template <class fpType>
202 static inline bool
203 isSnan(fpType val)
204 {
205  const bool single = (sizeof(fpType) == sizeof(float));
206  const uint64_t qnan =
207  single ? 0x7fc00000 : ULL(0x7ff8000000000000);
208  return std::isnan(val) && ((fpToBits(val) & qnan) != qnan);
209 }
210 
211 typedef int VfpSavedState;
212 
214 void finishVfp(FPSCR &fpscr, VfpSavedState state, bool flush, FPSCR mask = FpscrExcMask);
215 
216 template <class fpType>
217 fpType fixDest(FPSCR fpscr, fpType val, fpType op1);
218 
219 template <class fpType>
220 fpType fixDest(FPSCR fpscr, fpType val, fpType op1, fpType op2);
221 
222 template <class fpType>
223 fpType fixDivDest(FPSCR fpscr, fpType val, fpType op1, fpType op2);
224 
225 float fixFpDFpSDest(FPSCR fpscr, double val);
226 double fixFpSFpDDest(FPSCR fpscr, float val);
227 
228 uint16_t vcvtFpSFpH(FPSCR &fpscr, bool flush, bool defaultNan,
229  uint32_t rMode, bool ahp, float op);
230 uint16_t vcvtFpDFpH(FPSCR &fpscr, bool flush, bool defaultNan,
231  uint32_t rMode, bool ahp, double op);
232 
233 float vcvtFpHFpS(FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op);
234 double vcvtFpHFpD(FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op);
235 
236 static inline double
237 makeDouble(uint32_t low, uint32_t high)
238 {
239  double junk = 0.0;
240  return bitsToFp((uint64_t)low | ((uint64_t)high << 32), junk);
241 }
242 
243 static inline uint32_t
245 {
246  return fpToBits(val);
247 }
248 
249 static inline uint32_t
251 {
252  return fpToBits(val) >> 32;
253 }
254 
255 static inline void
256 setFPExceptions(int exceptions) {
257  feclearexcept(FeAllExceptions);
258  feraiseexcept(exceptions);
259 }
260 
261 template <typename T>
262 uint64_t
263 vfpFpToFixed(T val, bool isSigned, uint8_t width, uint8_t imm, bool
264  useRmode = true, VfpRoundingMode roundMode = VfpRoundZero,
265  bool aarch64 = false)
266 {
267  int rmode;
268  bool roundAwayFix = false;
269 
270  if (!useRmode) {
271  rmode = fegetround();
272  } else {
273  switch (roundMode)
274  {
275  case VfpRoundNearest:
276  rmode = FeRoundNearest;
277  break;
278  case VfpRoundUpward:
279  rmode = FeRoundUpward;
280  break;
281  case VfpRoundDown:
282  rmode = FeRoundDown;
283  break;
284  case VfpRoundZero:
285  rmode = FeRoundZero;
286  break;
287  case VfpRoundAway:
288  // There is no equivalent rounding mode, use round down and we'll
289  // fix it later
290  rmode = FeRoundDown;
291  roundAwayFix = true;
292  break;
293  default:
294  panic("Unsupported roundMode %d\n", roundMode);
295  }
296  }
297  __asm__ __volatile__("" : "=m" (rmode) : "m" (rmode));
298  fesetround(FeRoundNearest);
299  val = val * pow(2.0, imm);
300  __asm__ __volatile__("" : "=m" (val) : "m" (val));
301  fesetround(rmode);
302  feclearexcept(FeAllExceptions);
303  __asm__ __volatile__("" : "=m" (val) : "m" (val));
304  T origVal = val;
305  val = rint(val);
306  __asm__ __volatile__("" : "=m" (val) : "m" (val));
307 
308  int exceptions = fetestexcept(FeAllExceptions);
309 
310  int fpType = std::fpclassify(val);
311  if (fpType == FP_SUBNORMAL || fpType == FP_NAN) {
312  if (fpType == FP_NAN) {
313  exceptions |= FeInvalid;
314  }
315  val = 0.0;
316  } else if (origVal != val) {
317  switch (rmode) {
318  case FeRoundNearest:
319  if (origVal - val > 0.5)
320  val += 1.0;
321  else if (val - origVal > 0.5)
322  val -= 1.0;
323  break;
324  case FeRoundDown:
325  if (roundAwayFix) {
326  // The ordering on the subtraction looks a bit odd in that we
327  // don't do the obvious origVal - val, instead we do
328  // -(val - origVal). This is required to get the corruct bit
329  // exact behaviour when very close to the 0.5 threshold.
330  volatile T error = val;
331  error -= origVal;
332  error = -error;
333  if ( (error > 0.5) ||
334  ((error == 0.5) && (val >= 0)) )
335  val += 1.0;
336  } else {
337  if (origVal < val)
338  val -= 1.0;
339  }
340  break;
341  case FeRoundUpward:
342  if (origVal > val)
343  val += 1.0;
344  break;
345  }
346  exceptions |= FeInexact;
347  }
348 
349  __asm__ __volatile__("" : "=m" (val) : "m" (val));
350 
351  if (isSigned) {
352  bool outOfRange = false;
353  int64_t result = (int64_t) val;
354  uint64_t finalVal;
355 
356  if (!aarch64) {
357  if (width == 16) {
358  finalVal = (int16_t)val;
359  } else if (width == 32) {
360  finalVal =(int32_t)val;
361  } else if (width == 64) {
362  finalVal = result;
363  } else {
364  panic("Unsupported width %d\n", width);
365  }
366 
367  // check if value is in range
368  int64_t minVal = ~mask(width-1);
369  if ((double)val < minVal) {
370  outOfRange = true;
371  finalVal = minVal;
372  }
373  int64_t maxVal = mask(width-1);
374  if ((double)val > maxVal) {
375  outOfRange = true;
376  finalVal = maxVal;
377  }
378  } else {
379  bool isNeg = val < 0;
380  finalVal = result & mask(width);
381  // If the result is supposed to be less than 64 bits check that the
382  // upper bits that got thrown away are just sign extension bits
383  if (width != 64) {
384  outOfRange = ((uint64_t) result >> (width - 1)) !=
385  (isNeg ? mask(64-width+1) : 0);
386  }
387  // Check if the original floating point value doesn't matches the
388  // integer version we are also out of range. So create a saturated
389  // result.
390  if (isNeg) {
391  outOfRange |= val < result;
392  if (outOfRange) {
393  finalVal = 1LL << (width-1);
394  }
395  } else {
396  outOfRange |= val > result;
397  if (outOfRange) {
398  finalVal = mask(width-1);
399  }
400  }
401  }
402 
403  // Raise an exception if the value was out of range
404  if (outOfRange) {
405  exceptions |= FeInvalid;
406  exceptions &= ~FeInexact;
407  }
408  setFPExceptions(exceptions);
409  return finalVal;
410  } else {
411  if ((double)val < 0) {
412  exceptions |= FeInvalid;
413  exceptions &= ~FeInexact;
414  setFPExceptions(exceptions);
415  return 0;
416  }
417 
418  uint64_t result = ((uint64_t) val) & mask(width);
419  if (val > result) {
420  exceptions |= FeInvalid;
421  exceptions &= ~FeInexact;
422  setFPExceptions(exceptions);
423  return mask(width);
424  }
425 
426  setFPExceptions(exceptions);
427  return result;
428  }
429 };
430 
431 
432 float vfpUFixedToFpS(bool flush, bool defaultNan,
433  uint64_t val, uint8_t width, uint8_t imm);
434 float vfpSFixedToFpS(bool flush, bool defaultNan,
435  int64_t val, uint8_t width, uint8_t imm);
436 
437 double vfpUFixedToFpD(bool flush, bool defaultNan,
438  uint64_t val, uint8_t width, uint8_t imm);
439 double vfpSFixedToFpD(bool flush, bool defaultNan,
440  int64_t val, uint8_t width, uint8_t imm);
441 
442 float fprSqrtEstimate(FPSCR &fpscr, float op);
443 uint32_t unsignedRSqrtEstimate(uint32_t op);
444 
445 float fpRecipEstimate(FPSCR &fpscr, float op);
446 uint32_t unsignedRecipEstimate(uint32_t op);
447 
448 FPSCR
449 fpStandardFPSCRValue(const FPSCR &fpscr);
450 
451 class VfpMacroOp : public PredMacroOp
452 {
453  public:
454  static bool
456  {
457  return (idx % 32) < 8;
458  }
459 
460  protected:
461  bool wide;
462 
463  VfpMacroOp(const char *mnem, ExtMachInst _machInst,
464  OpClass __opClass, bool _wide) :
465  PredMacroOp(mnem, _machInst, __opClass), wide(_wide)
466  {}
467 
468  IntRegIndex addStride(IntRegIndex idx, unsigned stride);
469  void nextIdxs(IntRegIndex &dest, IntRegIndex &op1, IntRegIndex &op2);
470  void nextIdxs(IntRegIndex &dest, IntRegIndex &op1);
471  void nextIdxs(IntRegIndex &dest);
472 };
473 
474 template <typename T>
475 static inline T
476 fpAdd(T a, T b)
477 {
478  return a + b;
479 };
480 
481 template <typename T>
482 static inline T
483 fpSub(T a, T b)
484 {
485  return a - b;
486 };
487 
488 static inline float
489 fpAddS(float a, float b)
490 {
491  return a + b;
492 }
493 
494 static inline double
495 fpAddD(double a, double b)
496 {
497  return a + b;
498 }
499 
500 static inline float
501 fpSubS(float a, float b)
502 {
503  return a - b;
504 }
505 
506 static inline double
507 fpSubD(double a, double b)
508 {
509  return a - b;
510 }
511 
512 static inline float
513 fpDivS(float a, float b)
514 {
515  return a / b;
516 }
517 
518 static inline double
519 fpDivD(double a, double b)
520 {
521  return a / b;
522 }
523 
524 template <typename T>
525 static inline T
526 fpDiv(T a, T b)
527 {
528  return a / b;
529 };
530 
531 template <typename T>
532 static inline T
533 fpMulX(T a, T b)
534 {
535  uint64_t opData;
536  uint32_t sign1;
537  uint32_t sign2;
538  const bool single = (sizeof(T) == sizeof(float));
539  if (single) {
540  opData = (fpToBits(a));
541  sign1 = opData>>31;
542  opData = (fpToBits(b));
543  sign2 = opData>>31;
544  } else {
545  opData = (fpToBits(a));
546  sign1 = opData>>63;
547  opData = (fpToBits(b));
548  sign2 = opData>>63;
549  }
550  bool inf1 = (std::fpclassify(a) == FP_INFINITE);
551  bool inf2 = (std::fpclassify(b) == FP_INFINITE);
552  bool zero1 = (std::fpclassify(a) == FP_ZERO);
553  bool zero2 = (std::fpclassify(b) == FP_ZERO);
554  if ((inf1 && zero2) || (zero1 && inf2)) {
555  if (sign1 ^ sign2)
556  return (T)(-2.0);
557  else
558  return (T)(2.0);
559  } else {
560  return (a * b);
561  }
562 };
563 
564 
565 template <typename T>
566 static inline T
567 fpMul(T a, T b)
568 {
569  return a * b;
570 };
571 
572 static inline float
573 fpMulS(float a, float b)
574 {
575  return a * b;
576 }
577 
578 static inline double
579 fpMulD(double a, double b)
580 {
581  return a * b;
582 }
583 
584 template <typename T>
585 static inline T
586 // @todo remove this when all calls to it have been replaced with the new fplib implementation
587 fpMulAdd(T op1, T op2, T addend)
588 {
589  T result;
590 
591  if (sizeof(T) == sizeof(float))
592  result = fmaf(op1, op2, addend);
593  else
594  result = fma(op1, op2, addend);
595 
596  // ARM doesn't generate signed nan's from this opperation, so fix up the result
597  if (std::isnan(result) && !std::isnan(op1) &&
598  !std::isnan(op2) && !std::isnan(addend))
599  {
600  uint64_t bitMask = ULL(0x1) << ((sizeof(T) * 8) - 1);
601  result = bitsToFp(fpToBits(result) & ~bitMask, op1);
602  }
603  return result;
604 }
605 
606 template <typename T>
607 static inline T
608 fpRIntX(T a, FPSCR &fpscr)
609 {
610  T rVal;
611 
612  rVal = rint(a);
613  if (rVal != a && !std::isnan(a))
614  fpscr.ixc = 1;
615  return (rVal);
616 };
617 
618 template <typename T>
619 static inline T
620 fpMaxNum(T a, T b)
621 {
622  const bool single = (sizeof(T) == sizeof(float));
623  const uint64_t qnan = single ? 0x7fc00000 : ULL(0x7ff8000000000000);
624 
625  if (std::isnan(a))
626  return ((fpToBits(a) & qnan) == qnan) ? b : a;
627  if (std::isnan(b))
628  return ((fpToBits(b) & qnan) == qnan) ? a : b;
629  // Handle comparisons of +0 and -0.
630  if (!std::signbit(a) && std::signbit(b))
631  return a;
632  return fmax(a, b);
633 };
634 
635 template <typename T>
636 static inline T
637 fpMax(T a, T b)
638 {
639  if (std::isnan(a))
640  return a;
641  if (std::isnan(b))
642  return b;
643  return fpMaxNum<T>(a, b);
644 };
645 
646 template <typename T>
647 static inline T
648 fpMinNum(T a, T b)
649 {
650  const bool single = (sizeof(T) == sizeof(float));
651  const uint64_t qnan = single ? 0x7fc00000 : ULL(0x7ff8000000000000);
652 
653  if (std::isnan(a))
654  return ((fpToBits(a) & qnan) == qnan) ? b : a;
655  if (std::isnan(b))
656  return ((fpToBits(b) & qnan) == qnan) ? a : b;
657  // Handle comparisons of +0 and -0.
658  if (std::signbit(a) && !std::signbit(b))
659  return a;
660  return fmin(a, b);
661 };
662 
663 template <typename T>
664 static inline T
665 fpMin(T a, T b)
666 {
667  if (std::isnan(a))
668  return a;
669  if (std::isnan(b))
670  return b;
671  return fpMinNum<T>(a, b);
672 };
673 
674 template <typename T>
675 static inline T
676 fpRSqrts(T a, T b)
677 {
678  int fpClassA = std::fpclassify(a);
679  int fpClassB = std::fpclassify(b);
680  T aXb;
681  int fpClassAxB;
682 
683  if ((fpClassA == FP_ZERO && fpClassB == FP_INFINITE) ||
684  (fpClassA == FP_INFINITE && fpClassB == FP_ZERO)) {
685  return 1.5;
686  }
687  aXb = a*b;
688  fpClassAxB = std::fpclassify(aXb);
689  if (fpClassAxB == FP_SUBNORMAL) {
690  feraiseexcept(FeUnderflow);
691  return 1.5;
692  }
693  return (3.0 - (a * b)) / 2.0;
694 };
695 
696 template <typename T>
697 static inline T
698 fpRecps(T a, T b)
699 {
700  int fpClassA = std::fpclassify(a);
701  int fpClassB = std::fpclassify(b);
702  T aXb;
703  int fpClassAxB;
704 
705  if ((fpClassA == FP_ZERO && fpClassB == FP_INFINITE) ||
706  (fpClassA == FP_INFINITE && fpClassB == FP_ZERO)) {
707  return 2.0;
708  }
709  aXb = a*b;
710  fpClassAxB = std::fpclassify(aXb);
711  if (fpClassAxB == FP_SUBNORMAL) {
712  feraiseexcept(FeUnderflow);
713  return 2.0;
714  }
715  return 2.0 - (a * b);
716 };
717 
718 
719 static inline float
720 fpRSqrtsS(float a, float b)
721 {
722  int fpClassA = std::fpclassify(a);
723  int fpClassB = std::fpclassify(b);
724  float aXb;
725  int fpClassAxB;
726 
727  if ((fpClassA == FP_ZERO && fpClassB == FP_INFINITE) ||
728  (fpClassA == FP_INFINITE && fpClassB == FP_ZERO)) {
729  return 1.5;
730  }
731  aXb = a*b;
732  fpClassAxB = std::fpclassify(aXb);
733  if (fpClassAxB == FP_SUBNORMAL) {
734  feraiseexcept(FeUnderflow);
735  return 1.5;
736  }
737  return (3.0 - (a * b)) / 2.0;
738 }
739 
740 static inline float
741 fpRecpsS(float a, float b)
742 {
743  int fpClassA = std::fpclassify(a);
744  int fpClassB = std::fpclassify(b);
745  float aXb;
746  int fpClassAxB;
747 
748  if ((fpClassA == FP_ZERO && fpClassB == FP_INFINITE) ||
749  (fpClassA == FP_INFINITE && fpClassB == FP_ZERO)) {
750  return 2.0;
751  }
752  aXb = a*b;
753  fpClassAxB = std::fpclassify(aXb);
754  if (fpClassAxB == FP_SUBNORMAL) {
755  feraiseexcept(FeUnderflow);
756  return 2.0;
757  }
758  return 2.0 - (a * b);
759 }
760 
761 template <typename T>
762 static inline T
764  T val;
765 
766  val = round(a);
767  if (a - val == 0.5) {
768  if ( (((int) a) & 1) == 0 ) val += 1.0;
769  }
770  else if (a - val == -0.5) {
771  if ( (((int) a) & 1) == 0 ) val -= 1.0;
772  }
773  return val;
774 }
775 
776 
777 
778 class FpOp : public PredOp
779 {
780  protected:
781  FpOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
782  PredOp(mnem, _machInst, __opClass)
783  {}
784 
785  virtual float
786  doOp(float op1, float op2) const
787  {
788  panic("Unimplemented version of doOp called.\n");
789  }
790 
791  virtual float
792  doOp(float op1) const
793  {
794  panic("Unimplemented version of doOp called.\n");
795  }
796 
797  virtual double
798  doOp(double op1, double op2) const
799  {
800  panic("Unimplemented version of doOp called.\n");
801  }
802 
803  virtual double
804  doOp(double op1) const
805  {
806  panic("Unimplemented version of doOp called.\n");
807  }
808 
809  double
810  dbl(uint32_t low, uint32_t high) const
811  {
812  double junk = 0.0;
813  return bitsToFp((uint64_t)low | ((uint64_t)high << 32), junk);
814  }
815 
816  uint32_t
817  dblLow(double val) const
818  {
819  return fpToBits(val);
820  }
821 
822  uint32_t
823  dblHi(double val) const
824  {
825  return fpToBits(val) >> 32;
826  }
827 
828  template <class fpType>
829  fpType
830  processNans(FPSCR &fpscr, bool &done, bool defaultNan,
831  fpType op1, fpType op2) const;
832 
833  template <class fpType>
834  fpType
835  ternaryOp(FPSCR &fpscr, fpType op1, fpType op2, fpType op3,
836  fpType (*func)(fpType, fpType, fpType),
837  bool flush, bool defaultNan, uint32_t rMode) const;
838 
839  template <class fpType>
840  fpType
841  binaryOp(FPSCR &fpscr, fpType op1, fpType op2,
842  fpType (*func)(fpType, fpType),
843  bool flush, bool defaultNan, uint32_t rMode) const;
844 
845  template <class fpType>
846  fpType
847  unaryOp(FPSCR &fpscr, fpType op1,
848  fpType (*func)(fpType),
849  bool flush, uint32_t rMode) const;
850 
851  void
852  advancePC(PCState &pcState) const override
853  {
854  if (flags[IsLastMicroop]) {
855  pcState.uEnd();
856  } else if (flags[IsMicroop]) {
857  pcState.uAdvance();
858  } else {
859  pcState.advance();
860  }
861  }
862 
863  float
864  fpSqrt (FPSCR fpscr,float x) const
865  {
866 
867  return unaryOp(fpscr,x,sqrtf,fpscr.fz,fpscr.rMode);
868 
869  }
870 
871  double
872  fpSqrt (FPSCR fpscr,double x) const
873  {
874 
875  return unaryOp(fpscr,x,sqrt,fpscr.fz,fpscr.rMode);
876 
877  }
878 };
879 
880 class FpCondCompRegOp : public FpOp
881 {
882  protected:
885  uint8_t defCc;
886 
887  FpCondCompRegOp(const char *mnem, ExtMachInst _machInst,
888  OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2,
889  ConditionCode _condCode, uint8_t _defCc) :
890  FpOp(mnem, _machInst, __opClass),
891  op1(_op1), op2(_op2), condCode(_condCode), defCc(_defCc)
892  {}
893 
894  std::string generateDisassembly(
895  Addr pc, const Loader::SymbolTable *symtab) const override;
896 };
897 
898 class FpCondSelOp : public FpOp
899 {
900  protected:
903 
904  FpCondSelOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
905  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
906  ConditionCode _condCode) :
907  FpOp(mnem, _machInst, __opClass),
908  dest(_dest), op1(_op1), op2(_op2), condCode(_condCode)
909  {}
910 
911  std::string generateDisassembly(
912  Addr pc, const Loader::SymbolTable *symtab) const override;
913 };
914 
915 class FpRegRegOp : public FpOp
916 {
917  protected:
920 
921  FpRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
922  IntRegIndex _dest, IntRegIndex _op1,
924  FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
925  {
927  }
928 
929  std::string generateDisassembly(
930  Addr pc, const Loader::SymbolTable *symtab) const override;
931 };
932 
933 class FpRegImmOp : public FpOp
934 {
935  protected:
937  uint64_t imm;
938 
939  FpRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
940  IntRegIndex _dest, uint64_t _imm,
942  FpOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm)
943  {
945  }
946 
947  std::string generateDisassembly(
948  Addr pc, const Loader::SymbolTable *symtab) const override;
949 };
950 
951 class FpRegRegImmOp : public FpOp
952 {
953  protected:
956  uint64_t imm;
957 
958  FpRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
959  IntRegIndex _dest, IntRegIndex _op1,
960  uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop) :
961  FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1), imm(_imm)
962  {
964  }
965 
966  std::string generateDisassembly(
967  Addr pc, const Loader::SymbolTable *symtab) const override;
968 };
969 
970 class FpRegRegRegOp : public FpOp
971 {
972  protected:
976 
977  FpRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
978  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
980  FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2)
981  {
983  }
984 
985  std::string generateDisassembly(
986  Addr pc, const Loader::SymbolTable *symtab) const override;
987 };
988 
989 class FpRegRegRegCondOp : public FpOp
990 {
991  protected:
996 
997  FpRegRegRegCondOp(const char *mnem, ExtMachInst _machInst,
998  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
999  IntRegIndex _op2, ConditionCode _cond,
1001  FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2),
1002  cond(_cond)
1003  {
1005  }
1006 
1007  std::string generateDisassembly(
1008  Addr pc, const Loader::SymbolTable *symtab) const override;
1009 };
1010 
1011 class FpRegRegRegRegOp : public FpOp
1012 {
1013  protected:
1018 
1019  FpRegRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
1020  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
1022  FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2),
1023  op3(_op3)
1024  {
1026  }
1027 
1028  std::string generateDisassembly(
1029  Addr pc, const Loader::SymbolTable *symtab) const override;
1030 };
1031 
1032 class FpRegRegRegImmOp : public FpOp
1033 {
1034  protected:
1038  uint64_t imm;
1039 
1040  FpRegRegRegImmOp(const char *mnem, ExtMachInst _machInst,
1041  OpClass __opClass, IntRegIndex _dest,
1042  IntRegIndex _op1, IntRegIndex _op2,
1043  uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop) :
1044  FpOp(mnem, _machInst, __opClass),
1045  dest(_dest), op1(_op1), op2(_op2), imm(_imm)
1046  {
1048  }
1049 
1050  std::string generateDisassembly(
1051  Addr pc, const Loader::SymbolTable *symtab) const override;
1052 };
1053 
1054 }
1055 
1056 #endif //__ARCH_ARM_INSTS_VFP_HH__
ArmISA::FpOp::doOp
virtual float doOp(float op1, float op2) const
Definition: vfp.hh:786
ArmISA::FpRegRegRegImmOp
Definition: vfp.hh:1032
ArmISA::FpRegRegRegCondOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:130
ArmISA::FpCondCompRegOp::defCc
uint8_t defCc
Definition: vfp.hh:885
ArmISA::fp
Bitfield< 19, 16 > fp
Definition: miscregs_types.hh:173
ArmISA::vcvtFpSFpH
uint16_t vcvtFpSFpH(FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, float op)
Definition: vfp.cc:574
StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:99
ArmISA::FpOp::doOp
virtual double doOp(double op1, double op2) const
Definition: vfp.hh:798
ArmISA::fpMinNum
static T fpMinNum(T a, T b)
Definition: vfp.hh:648
ArmISA::fpMulD
static double fpMulD(double a, double b)
Definition: vfp.hh:579
LL
#define LL(N)
int64_t constant
Definition: types.hh:52
misc.hh
ArmISA::FpOp::ternaryOp
fpType ternaryOp(FPSCR &fpscr, fpType op1, fpType op2, fpType op3, fpType(*func)(fpType, fpType, fpType), bool flush, bool defaultNan, uint32_t rMode) const
Definition: vfp.cc:958
ArmISA::FpCondCompRegOp::op1
IntRegIndex op1
Definition: vfp.hh:883
ArmISA::FpOp::dblLow
uint32_t dblLow(double val) const
Definition: vfp.hh:817
ArmISA::FpCondCompRegOp::condCode
ConditionCode condCode
Definition: vfp.hh:884
ArmISA::ConditionCode
ConditionCode
Definition: ccregs.hh:63
ArmISA::VfpMacroOp
Definition: vfp.hh:451
ArmISA::makeDouble
static double makeDouble(uint32_t low, uint32_t high)
Definition: vfp.hh:237
ArmISA::FpRegRegOp::FpRegRegOp
FpRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, VfpMicroMode mode=VfpNotAMicroop)
Definition: vfp.hh:921
ArmISA::fpRecpsS
static float fpRecpsS(float a, float b)
Definition: vfp.hh:741
ArmISA::vfpSFixedToFpS
float vfpSFixedToFpS(bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
Definition: vfp.cc:690
ArmISA::FpCondSelOp::condCode
ConditionCode condCode
Definition: vfp.hh:902
ArmISA::fpRSqrts
static T fpRSqrts(T a, T b)
Definition: vfp.hh:676
ArmISA::FpRegRegRegCondOp::dest
IntRegIndex dest
Definition: vfp.hh:992
ArmISA::FpOp::fpSqrt
double fpSqrt(FPSCR fpscr, double x) const
Definition: vfp.hh:872
ArmISA::FeInvalid
@ FeInvalid
Definition: vfp.hh:86
ArmISA::FeUnderflow
@ FeUnderflow
Definition: vfp.hh:88
ArmISA::FeInexact
@ FeInexact
Definition: vfp.hh:85
ArmISA::FpRegImmOp
Definition: vfp.hh:933
ArmISA::width
Bitfield< 4 > width
Definition: miscregs_types.hh:68
ArmISA::FpRegRegImmOp::FpRegRegImmOp
FpRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm, VfpMicroMode mode=VfpNotAMicroop)
Definition: vfp.hh:958
ArmISA::FpRegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:80
ArmISA::VfpRoundDown
@ VfpRoundDown
Definition: vfp.hh:104
ArmISA::FpCondSelOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:64
Loader::SymbolTable
Definition: symtab.hh:59
ArmISA::IntRegIndex
IntRegIndex
Definition: intregs.hh:51
ArmISA::FeDivByZero
@ FeDivByZero
Definition: vfp.hh:84
ArmISA::fpRIntX
static T fpRIntX(T a, FPSCR &fpscr)
Definition: vfp.hh:608
ArmISA::VfpMicroMode
VfpMicroMode
Definition: vfp.hh:51
X86ISA::op
Bitfield< 4 > op
Definition: types.hh:78
ArmISA::FpRegRegRegOp
Definition: vfp.hh:970
ArmISA::FpOp::unaryOp
fpType unaryOp(FPSCR &fpscr, fpType op1, fpType(*func)(fpType), bool flush, uint32_t rMode) const
Definition: vfp.cc:1107
ArmISA::fpMax
static T fpMax(T a, T b)
Definition: vfp.hh:637
ArmISA::PredOp
Base class for predicated integer operations.
Definition: pred_inst.hh:210
ArmISA::ahp
Bitfield< 26 > ahp
Definition: miscregs_types.hh:445
ArmISA::FpCondSelOp::dest
IntRegIndex dest
Definition: vfp.hh:901
ArmISA::lowFromDouble
static uint32_t lowFromDouble(double val)
Definition: vfp.hh:244
ArmISA::FeOverflow
@ FeOverflow
Definition: vfp.hh:87
ArmISA::fpSub
static T fpSub(T a, T b)
Definition: vfp.hh:483
ArmISA::bitsToFp
static float bitsToFp(uint64_t, float)
Definition: vfp.hh:178
ArmISA
Definition: ccregs.hh:41
ArmISA::FeRoundNearest
@ FeRoundNearest
Definition: vfp.hh:95
ArmISA::vfpFpToFixed
uint64_t vfpFpToFixed(T val, bool isSigned, uint8_t width, uint8_t imm, bool useRmode=true, VfpRoundingMode roundMode=VfpRoundZero, bool aarch64=false)
Definition: vfp.hh:263
ArmISA::fpMulX
static T fpMulX(T a, T b)
Definition: vfp.hh:533
ArmISA::FpCondSelOp::op1
IntRegIndex op1
Definition: vfp.hh:901
ArmISA::VfpSavedState
int VfpSavedState
Definition: vfp.hh:211
ArmISA::FpRegRegImmOp
Definition: vfp.hh:951
ArmISA::FpRegRegRegImmOp::op2
IntRegIndex op2
Definition: vfp.hh:1037
ArmISA::FpOp::processNans
fpType processNans(FPSCR &fpscr, bool &done, bool defaultNan, fpType op1, fpType op2) const
Definition: vfp.cc:914
ArmISA::aarch64
Bitfield< 34 > aarch64
Definition: types.hh:90
ArmISA::FpRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:92
ArmISA::FpOp::dblHi
uint32_t dblHi(double val) const
Definition: vfp.hh:823
ArmISA::FpRegRegRegOp::FpRegRegRegOp
FpRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, VfpMicroMode mode=VfpNotAMicroop)
Definition: vfp.hh:977
ArmISA::FpRegRegRegImmOp::dest
IntRegIndex dest
Definition: vfp.hh:1035
ArmISA::VfpMacroOp::wide
bool wide
Definition: vfp.hh:461
ArmISA::unsignedRSqrtEstimate
uint32_t unsignedRSqrtEstimate(uint32_t op)
Definition: vfp.cc:811
ArmISA::FpRegRegRegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:146
ArmISA::VfpLastMicroop
@ VfpLastMicroop
Definition: vfp.hh:55
ArmISA::fpToBits
static uint32_t fpToBits(float)
Definition: vfp.hh:154
ArmISA::fixFpSFpDDest
double fixFpSFpDDest(FPSCR fpscr, float val)
Definition: vfp.cc:370
ArmISA::fixFpDFpSDest
float fixFpDFpSDest(FPSCR fpscr, double val)
Definition: vfp.cc:334
ArmISA::FpCondCompRegOp::FpCondCompRegOp
FpCondCompRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _condCode, uint8_t _defCc)
Definition: vfp.hh:887
ArmISA::a
Bitfield< 8 > a
Definition: miscregs_types.hh:62
ArmISA::fpRecipEstimate
float fpRecipEstimate(FPSCR &fpscr, float op)
Definition: vfp.cc:850
ArmISA::FeAllExceptions
@ FeAllExceptions
Definition: vfp.hh:89
ArmISA::fpStandardFPSCRValue
FPSCR fpStandardFPSCRValue(const FPSCR &fpscr)
Definition: vfp.cc:902
ArmISA::FeRoundUpward
@ FeRoundUpward
Definition: vfp.hh:97
ArmISA::FpRegRegRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:162
ArmISA::FpRegRegRegImmOp::FpRegRegRegImmOp
FpRegRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm, VfpMicroMode mode=VfpNotAMicroop)
Definition: vfp.hh:1040
ArmISA::vcvtFpHFpS
float vcvtFpHFpS(FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
Definition: vfp.cc:662
ArmISA::FpRegRegRegCondOp::op2
IntRegIndex op2
Definition: vfp.hh:994
ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:141
ArmISA::fpRSqrtsS
static float fpRSqrtsS(float a, float b)
Definition: vfp.hh:720
ArmISA::FpRegRegRegImmOp::op1
IntRegIndex op1
Definition: vfp.hh:1036
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
ArmISA::fpSubD
static double fpSubD(double a, double b)
Definition: vfp.hh:507
ArmISA::fpMaxNum
static T fpMaxNum(T a, T b)
Definition: vfp.hh:620
ArmISA::FpRegRegRegRegOp::dest
IntRegIndex dest
Definition: vfp.hh:1014
ArmISA::FpRegRegImmOp::op1
IntRegIndex op1
Definition: vfp.hh:955
ArmISA::FpscrExcMask
static const uint32_t FpscrExcMask
Definition: miscregs.hh:2196
ArmISA::isSnan
static bool isSnan(fpType val)
Definition: vfp.hh:203
ArmISA::FpOp::advancePC
void advancePC(PCState &pcState) const override
Definition: vfp.hh:852
ArmISA::FpRegRegRegCondOp::FpRegRegRegCondOp
FpRegRegRegCondOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _cond, VfpMicroMode mode=VfpNotAMicroop)
Definition: vfp.hh:997
ArmISA::VfpNotAMicroop
@ VfpNotAMicroop
Definition: vfp.hh:52
ArmISA::fpDiv
static T fpDiv(T a, T b)
Definition: vfp.hh:526
ArmISA::mode
Bitfield< 4, 0 > mode
Definition: miscregs_types.hh:70
ArmISA::FeExceptionBit
FeExceptionBit
Definition: vfp.hh:82
ArmISA::vcvtFpDFpH
uint16_t vcvtFpDFpH(FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, double op)
Definition: vfp.cc:582
ArmISA::FpRegRegOp::dest
IntRegIndex dest
Definition: vfp.hh:918
ArmISA::VfpFirstMicroop
@ VfpFirstMicroop
Definition: vfp.hh:54
ArmISA::FpRegRegImmOp::imm
uint64_t imm
Definition: vfp.hh:956
ArmISA::FpRegImmOp::dest
IntRegIndex dest
Definition: vfp.hh:936
ArmISA::vcvtFpHFpD
double vcvtFpHFpD(FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
Definition: vfp.cc:652
ArmISA::PredMacroOp
Base class for predicated macro-operations.
Definition: pred_inst.hh:336
ArmISA::fpRecps
static T fpRecps(T a, T b)
Definition: vfp.hh:698
ArmISA::FpOp::doOp
virtual float doOp(float op1) const
Definition: vfp.hh:792
ArmISA::FpRegRegRegRegOp
Definition: vfp.hh:1011
ArmISA::FpOp::fpSqrt
float fpSqrt(FPSCR fpscr, float x) const
Definition: vfp.hh:864
ArmISA::FpOp
Definition: vfp.hh:778
StaticInst::ExtMachInst
TheISA::ExtMachInst ExtMachInst
Binary extended machine instruction type.
Definition: static_inst.hh:89
ArmISA::FpRegRegRegCondOp::op1
IntRegIndex op1
Definition: vfp.hh:993
ArmISA::FpRegRegRegRegOp::op3
IntRegIndex op3
Definition: vfp.hh:1017
ArmISA::VfpMacroOp::inScalarBank
static bool inScalarBank(IntRegIndex idx)
Definition: vfp.hh:455
RiscvISA::x
Bitfield< 3 > x
Definition: pagetable.hh:69
ArmISA::FpRegRegOp::op1
IntRegIndex op1
Definition: vfp.hh:919
ArmISA::FpRegRegRegRegOp::op2
IntRegIndex op2
Definition: vfp.hh:1016
ArmISA::vfpSFixedToFpD
double vfpSFixedToFpD(bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
Definition: vfp.cc:729
ArmISA::FpRegRegRegOp::op2
IntRegIndex op2
Definition: vfp.hh:975
ArmISA::fpDivD
static double fpDivD(double a, double b)
Definition: vfp.hh:519
ArmISA::FpRegRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:103
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
ArmISA::FpCondCompRegOp::op2
IntRegIndex op2
Definition: vfp.hh:883
ArmISA::FpRegImmOp::FpRegImmOp
FpRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode=VfpNotAMicroop)
Definition: vfp.hh:939
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ArmISA::VfpRoundAway
@ VfpRoundAway
Definition: vfp.hh:106
ArmISA::FpRegRegRegOp::dest
IntRegIndex dest
Definition: vfp.hh:973
ArmISA::FpRegRegImmOp::dest
IntRegIndex dest
Definition: vfp.hh:954
ArmISA::FpCondSelOp
Definition: vfp.hh:898
ArmISA::FpRegRegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:116
ArmISA::rMode
Bitfield< 23, 22 > rMode
Definition: miscregs_types.hh:442
miscregs.hh
ArmISA::VfpRoundUpward
@ VfpRoundUpward
Definition: vfp.hh:103
ArmISA::roundNEven
static T roundNEven(T a)
Definition: vfp.hh:763
ArmISA::VfpMacroOp::addStride
IntRegIndex addStride(IntRegIndex idx, unsigned stride)
Definition: vfp.cc:1164
ArmISA::fpSubS
static float fpSubS(float a, float b)
Definition: vfp.hh:501
ArmISA::VfpMacroOp::VfpMacroOp
VfpMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, bool _wide)
Definition: vfp.hh:463
ArmISA::FpRegRegRegRegOp::FpRegRegRegRegOp
FpRegRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3, VfpMicroMode mode=VfpNotAMicroop)
Definition: vfp.hh:1019
ArmISA::FpRegRegRegRegOp::op1
IntRegIndex op1
Definition: vfp.hh:1015
ArmISA::FpRegImmOp::imm
uint64_t imm
Definition: vfp.hh:937
ArmISA::fprSqrtEstimate
float fprSqrtEstimate(FPSCR &fpscr, float op)
Definition: vfp.cc:768
ArmISA::FeRoundDown
@ FeRoundDown
Definition: vfp.hh:94
ArmISA::VfpRoundNearest
@ VfpRoundNearest
Definition: vfp.hh:102
ArmISA::setFPExceptions
static void setFPExceptions(int exceptions)
Definition: vfp.hh:256
ArmISA::b
Bitfield< 7 > b
Definition: miscregs_types.hh:376
ArmISA::VfpMicroop
@ VfpMicroop
Definition: vfp.hh:53
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
ArmISA::vfpUFixedToFpS
float vfpUFixedToFpS(bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
Definition: vfp.cc:672
ArmISA::FpCondSelOp::op2
IntRegIndex op2
Definition: vfp.hh:901
ArmISA::FpCondCompRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:49
ArmISA::VfpRoundingMode
VfpRoundingMode
Definition: vfp.hh:100
ArmISA::FpRegRegOp
Definition: vfp.hh:915
ArmISA::setVfpMicroFlags
static void setVfpMicroFlags(VfpMicroMode mode, T &flags)
Definition: vfp.hh:60
ArmISA::fixDivDest
fpType fixDivDest(bool flush, bool defaultNan, fpType val, fpType op1, fpType op2)
Definition: vfp.cc:299
ArmISA::fpMul
static T fpMul(T a, T b)
Definition: vfp.hh:567
ArmISA::FpCondCompRegOp
Definition: vfp.hh:880
ArmISA::fpAddS
static float fpAddS(float a, float b)
Definition: vfp.hh:489
ArmISA::fpMin
static T fpMin(T a, T b)
Definition: vfp.hh:665
ArmISA::vfpUFixedToFpD
double vfpUFixedToFpD(bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
Definition: vfp.cc:710
ArmISA::stride
Bitfield< 21, 20 > stride
Definition: miscregs_types.hh:441
ArmISA::prepFpState
VfpSavedState prepFpState(uint32_t rMode)
Definition: vfp.cc:180
ArmISA::fpAdd
static T fpAdd(T a, T b)
Definition: vfp.hh:476
ArmISA::finishVfp
void finishVfp(FPSCR &fpscr, VfpSavedState state, bool flush, FPSCR mask)
Definition: vfp.cc:202
ArmISA::highFromDouble
static uint32_t highFromDouble(double val)
Definition: vfp.hh:250
ArmISA::fpMulAdd
static T fpMulAdd(T op1, T op2, T addend)
Definition: vfp.hh:587
ArmISA::unsignedRecipEstimate
uint32_t unsignedRecipEstimate(uint32_t op)
Definition: vfp.cc:886
ArmISA::FpRegRegRegCondOp
Definition: vfp.hh:989
ArmISA::fpAddD
static double fpAddD(double a, double b)
Definition: vfp.hh:495
ArmISA::VfpRoundZero
@ VfpRoundZero
Definition: vfp.hh:105
ArmISA::flushToZero
flushToZero
Definition: miscregs_types.hh:471
ArmISA::FpRegRegRegOp::op1
IntRegIndex op1
Definition: vfp.hh:974
ArmISA::vfpFlushToZero
static void vfpFlushToZero(FPSCR &fpscr, fpType &op)
Definition: vfp.hh:138
ArmISA::fpMulS
static float fpMulS(float a, float b)
Definition: vfp.hh:573
ArmISA::FpOp::binaryOp
fpType binaryOp(FPSCR &fpscr, fpType op1, fpType op2, fpType(*func)(fpType, fpType), bool flush, bool defaultNan, uint32_t rMode) const
Definition: vfp.cc:1036
ArmISA::FpOp::dbl
double dbl(uint32_t low, uint32_t high) const
Definition: vfp.hh:810
ArmISA::VfpMacroOp::nextIdxs
void nextIdxs(IntRegIndex &dest, IntRegIndex &op1, IntRegIndex &op2)
Definition: vfp.cc:1177
ArmISA::FpOp::FpOp
FpOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: vfp.hh:781
ArmISA::FeRoundingMode
FeRoundingMode
Definition: vfp.hh:92
ArmISA::FpRegRegRegImmOp::imm
uint64_t imm
Definition: vfp.hh:1038
ArmISA::fpDivS
static float fpDivS(float a, float b)
Definition: vfp.hh:513
ArmISA::FpCondSelOp::FpCondSelOp
FpCondSelOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _condCode)
Definition: vfp.hh:904
ArmISA::FpRegRegRegCondOp::cond
ConditionCode cond
Definition: vfp.hh:995
ArmISA::fixDest
fpType fixDest(bool flush, bool defaultNan, fpType val, fpType op1)
Definition: vfp.cc:228
ULL
#define ULL(N)
uint64_t constant
Definition: types.hh:50
ArmISA::mask
Bitfield< 28, 24 > mask
Definition: miscregs_types.hh:711
ArmISA::FeRoundZero
@ FeRoundZero
Definition: vfp.hh:96
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
ArmISA::FpOp::doOp
virtual double doOp(double op1) const
Definition: vfp.hh:804
bits
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:75

Generated on Wed Sep 30 2020 14:02:00 for gem5 by doxygen 1.8.17