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28 #ifndef __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
29 #define __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
40 #include "params/FastModelScxEvsCortexR52x1.hh"
41 #include "params/FastModelScxEvsCortexR52x2.hh"
42 #include "params/FastModelScxEvsCortexR52x3.hh"
43 #include "params/FastModelScxEvsCortexR52x4.hh"
44 #include "scx_evs_CortexR52x1.h"
45 #include "scx_evs_CortexR52x2.h"
46 #include "scx_evs_CortexR52x3.h"
47 #include "scx_evs_CortexR52x4.h"
55 class CortexR52Cluster;
57 template <
class Types>
64 using Base =
typename Types::Base;
65 using Params =
typename Types::Params;
120 this->signalInterrupt->spi(num,
true);
126 this->signalInterrupt->spi(num,
false);
134 Base::end_of_elaboration();
135 Base::start_of_simulation();
150 using Base = scx_evs_CortexR52x1;
151 using Params = FastModelScxEvsCortexR52x1Params;
159 using Base = scx_evs_CortexR52x2;
160 using Params = FastModelScxEvsCortexR52x2Params;
161 static const int CoreCount = 2;
168 using Base = scx_evs_CortexR52x3;
169 using Params = FastModelScxEvsCortexR52x3Params;
170 static const int CoreCount = 3;
177 using Base = scx_evs_CortexR52x4;
178 using Params = FastModelScxEvsCortexR52x4Params;
179 static const int CoreCount = 4;
186 #endif // __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
ClockRateControlInitiatorSocket clockRateControl
static const int SpiCount
FastModelScxEvsCortexR52x4Params Params
void setSysCounterFrq(uint64_t sys_counter_frq) override
FastModelScxEvsCortexR52x1Params Params
FastModelScxEvsCortexR52x2Params Params
uint64_t Tick
Tick count type.
void setClkPeriod(Tick clk_period) override
void lowerInterruptPin(int num)
CortexR52Cluster * gem5CpuCluster
std::vector< std::unique_ptr< CoreInt > > ppis
typename Types::Params Params
void setCluster(SimObject *cluster) override
CorePins(Evs *_evs, int _cpu)
ScxEvsCortexR52(const Params &p)
static const int PpiCount
SignalInterruptInitiatorSocket signalInterrupt
Ports are used to interface objects to each other.
void sendFunc(PacketPtr pkt) override
void raiseInterruptPin(int num)
typename Types::Base Base
Port & gem5_getPort(const std::string &if_name, int idx) override
const std::string & name()
void raiseInterruptPin(int num)
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
std::vector< std::unique_ptr< ClstrInt > > spis
void start_of_simulation() override
void end_of_elaboration() override
std::vector< std::unique_ptr< CorePins > > corePins
void lowerInterruptPin(int num)
FastModelScxEvsCortexR52x3Params Params
static const int CoreCount
static const int CoreCount
SC_HAS_PROCESS(ScxEvsCortexR52)
Abstract superclass for simulation objects.
Generated on Tue Jun 22 2021 15:28:19 for gem5 by doxygen 1.8.17