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evs.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
29 #define __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
30 
31 #include <memory>
32 
38 #include "dev/intpin.hh"
39 #include "mem/port_proxy.hh"
40 #include "params/FastModelScxEvsCortexR52x1.hh"
41 #include "params/FastModelScxEvsCortexR52x2.hh"
42 #include "params/FastModelScxEvsCortexR52x3.hh"
43 #include "params/FastModelScxEvsCortexR52x4.hh"
44 #include "scx_evs_CortexR52x1.h"
45 #include "scx_evs_CortexR52x2.h"
46 #include "scx_evs_CortexR52x3.h"
47 #include "scx_evs_CortexR52x4.h"
51 
52 namespace FastModel
53 {
54 
55 class CortexR52Cluster;
56 
57 template <class Types>
58 class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs
59 {
60  private:
61  static const int CoreCount = Types::CoreCount;
62  static const int PpiCount = 9;
63  static const int SpiCount = 960;
64  using Base = typename Types::Base;
65  using Params = typename Types::Params;
67 
69 
72 
73  // A structure to collect per-core connections, and also plumb up PPIs.
74  struct CorePins
75  {
77 
78  std::string name;
79  Evs *evs;
80  int cpu;
81 
82  CorePins(Evs *_evs, int _cpu);
83 
84  void
86  {
87  evs->signalInterrupt->ppi(cpu, num, true);
88  }
89 
90  void
92  {
93  evs->signalInterrupt->ppi(cpu, num, false);
94  }
95 
97 
101  };
102 
104 
106 
108 
110 
111  const Params &params;
112 
113  public:
114  ScxEvsCortexR52(const Params &p) : ScxEvsCortexR52(p.name.c_str(), p) {}
115  ScxEvsCortexR52(const sc_core::sc_module_name &mod_name, const Params &p);
116 
117  void
119  {
120  this->signalInterrupt->spi(num, true);
121  }
122 
123  void
125  {
126  this->signalInterrupt->spi(num, false);
127  }
128 
129  Port &gem5_getPort(const std::string &if_name, int idx) override;
130 
131  void
133  {
134  Base::end_of_elaboration();
135  Base::start_of_simulation();
136  }
137  void start_of_simulation() override {}
138 
139  void sendFunc(PacketPtr pkt) override;
140 
141  void setClkPeriod(Tick clk_period) override;
142 
143  void setSysCounterFrq(uint64_t sys_counter_frq) override;
144 
145  void setCluster(SimObject *cluster) override;
146 };
147 
149 {
150  using Base = scx_evs_CortexR52x1;
151  using Params = FastModelScxEvsCortexR52x1Params;
152  static const int CoreCount = 1;
153 };
155 extern template class ScxEvsCortexR52<ScxEvsCortexR52x1Types>;
156 
158 {
159  using Base = scx_evs_CortexR52x2;
160  using Params = FastModelScxEvsCortexR52x2Params;
161  static const int CoreCount = 2;
162 };
164 extern template class ScxEvsCortexR52<ScxEvsCortexR52x2Types>;
165 
167 {
168  using Base = scx_evs_CortexR52x3;
169  using Params = FastModelScxEvsCortexR52x3Params;
170  static const int CoreCount = 3;
171 };
173 extern template class ScxEvsCortexR52<ScxEvsCortexR52x3Types>;
174 
176 {
177  using Base = scx_evs_CortexR52x4;
178  using Params = FastModelScxEvsCortexR52x4Params;
179  static const int CoreCount = 4;
180 };
182 extern template class ScxEvsCortexR52<ScxEvsCortexR52x4Types>;
183 
184 } // namespace FastModel
185 
186 #endif // __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
FastModel::ScxEvsCortexR52::CorePins::evs
Evs * evs
Definition: evs.hh:79
FastModel::ScxEvsCortexR52x4Types
Definition: evs.hh:175
FastModel::ScxEvsCortexR52::CorePins::name
std::string name
Definition: evs.hh:78
FastModel::ScxEvsCortexR52::clockRateControl
ClockRateControlInitiatorSocket clockRateControl
Definition: evs.hh:70
FastModel::ScxEvsCortexR52::SpiCount
static const int SpiCount
Definition: evs.hh:63
FastModel::ScxEvsCortexR52x4Types::Base
scx_evs_CortexR52x4 Base
Definition: evs.hh:177
FastModel::ScxEvsCortexR52x4Types::Params
FastModelScxEvsCortexR52x4Params Params
Definition: evs.hh:178
FastModel::ScxEvsCortexR52x1Types::Base
scx_evs_CortexR52x1 Base
Definition: evs.hh:150
FastModel::ScxEvsCortexR52::setSysCounterFrq
void setSysCounterFrq(uint64_t sys_counter_frq) override
Definition: evs.cc:48
FastModel::ScxEvsCortexR52x1Types::Params
FastModelScxEvsCortexR52x1Params Params
Definition: evs.hh:151
FastModel::ScxEvsCortexR52x2Types::Params
FastModelScxEvsCortexR52x2Params Params
Definition: evs.hh:160
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:59
FastModel::ScxEvsCortexR52::setClkPeriod
void setClkPeriod(Tick clk_period) override
Definition: evs.cc:41
FastModel::ScxEvsCortexR52::CorePins::lowerInterruptPin
void lowerInterruptPin(int num)
Definition: evs.hh:91
SignalInterruptInitiatorSocket
Definition: signal_interrupt.hh:57
std::vector
STL vector class.
Definition: stl.hh:37
FastModel::ScxEvsCortexR52::CorePins
Definition: evs.hh:74
FastModel::ScxEvsCortexR52x2Types::Base
scx_evs_CortexR52x2 Base
Definition: evs.hh:159
FastModel::ScxEvsCortexR52::gem5CpuCluster
CortexR52Cluster * gem5CpuCluster
Definition: evs.hh:109
FastModel::ScxEvsCortexR52::CorePins::ppis
std::vector< std::unique_ptr< CoreInt > > ppis
Definition: evs.hh:96
FastModel::ScxEvsCortexR52::Params
typename Types::Params Params
Definition: evs.hh:65
FastModel::ScxEvsCortexR52::setCluster
void setCluster(SimObject *cluster) override
Definition: evs.cc:55
FastModel::ScxEvsCortexR52::CorePins::CorePins
CorePins(Evs *_evs, int _cpu)
Definition: evs.cc:62
FastModel::ScxEvsCortexR52x1Types
Definition: evs.hh:148
cpu.hh
FastModel::ScxEvsCortexR52::ScxEvsCortexR52
ScxEvsCortexR52(const Params &p)
Definition: evs.hh:114
FastModel::ScxEvsCortexR52::PpiCount
static const int PpiCount
Definition: evs.hh:62
sc_event.hh
FastModel::ScxEvsCortexR52::CorePins::cpu
int cpu
Definition: evs.hh:80
FastModel::ScxEvsCortexR52::signalInterrupt
SignalInterruptInitiatorSocket signalInterrupt
Definition: evs.hh:71
FastModel::ScxEvsCortexR52
Definition: evs.hh:58
Port
Ports are used to interface objects to each other.
Definition: port.hh:56
FastModel::ScxEvsCortexR52::sendFunc
void sendFunc(PacketPtr pkt) override
Definition: evs.cc:96
port_proxy.hh
IntSinkPin
Definition: intpin.hh:75
FastModel::ScxEvsCortexR52::CorePins::raiseInterruptPin
void raiseInterruptPin(int num)
Definition: evs.hh:85
FastModel::ScxEvsCortexR52::Base
typename Types::Base Base
Definition: evs.hh:64
FastModel::ScxEvsCortexR52::gem5_getPort
Port & gem5_getPort(const std::string &if_name, int idx) override
Definition: evs.cc:106
sc_core::sc_module_name
Definition: sc_module_name.hh:41
FastModel::ScxEvsCortexR52x3Types
Definition: evs.hh:166
signal_interrupt.hh
name
const std::string & name()
Definition: trace.cc:48
sc_module.hh
amba_ports.hh
ClockRateControlInitiatorSocket
Definition: exported_clock_rate_control.hh:60
FastModel
Definition: amba_from_tlm_bridge.cc:32
FastModel::ScxEvsCortexR52::raiseInterruptPin
void raiseInterruptPin(int num)
Definition: evs.hh:118
FastModel::ScxEvsCortexR52::CorePins::amba
AmbaInitiator amba
Definition: evs.hh:100
sc_gem5::TlmInitiatorBaseWrapper
Definition: tlm_port_wrapper.hh:40
FastModel::ScxEvsCortexR52x2Types
Definition: evs.hh:157
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:258
FastModel::ScxEvsCortexR52::spis
std::vector< std::unique_ptr< ClstrInt > > spis
Definition: evs.hh:107
FastModel::ScxEvsCortexR52::start_of_simulation
void start_of_simulation() override
Definition: evs.hh:137
exported_clock_rate_control.hh
FastModel::CortexR52Cluster
Definition: cortex_r52.hh:75
FastModel::ScxEvsCortexR52::end_of_elaboration
void end_of_elaboration() override
Definition: evs.hh:132
tlm_port_wrapper.hh
FastModel::ScxEvsCortexR52::corePins
std::vector< std::unique_ptr< CorePins > > corePins
Definition: evs.hh:103
FastModel::ScxEvsCortexR52::params
const Params & params
Definition: evs.hh:111
FastModel::ScxEvsCortexR52::lowerInterruptPin
void lowerInterruptPin(int num)
Definition: evs.hh:124
FastModel::ScxEvsCortexR52x3Types::Params
FastModelScxEvsCortexR52x3Params Params
Definition: evs.hh:169
intpin.hh
FastModel::ScxEvsCortexR52x1Types::CoreCount
static const int CoreCount
Definition: evs.hh:152
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
signal_receiver.hh
FastModel::ScxEvsCortexR52::CorePins::flash
AmbaInitiator flash
Definition: evs.hh:99
FastModel::ScxEvsCortexR52::CoreCount
static const int CoreCount
Definition: evs.hh:61
FastModel::ScxEvsCortexR52x3Types::Base
scx_evs_CortexR52x3 Base
Definition: evs.hh:168
Iris::BaseCpuEvs
Definition: cpu.hh:42
FastModel::ScxEvsCortexR52::SC_HAS_PROCESS
SC_HAS_PROCESS(ScxEvsCortexR52)
FastModel::ScxEvsCortexR52::CorePins::llpp
AmbaInitiator llpp
Definition: evs.hh:98
SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:141

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