gem5 v24.0.0.0
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BaseRoutingUnit.hh
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1/*
2 * Copyright (c) 2021 ARM Limited
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14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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39 */
40
41#ifndef __MEM_RUBY_NETWORK_SIMPLE_BASEROUTINGUNIT_HH__
42#define __MEM_RUBY_NETWORK_SIMPLE_BASEROUTINGUNIT_HH__
43
44#include <vector>
45
48#include "params/BaseRoutingUnit.hh"
49#include "sim/sim_object.hh"
50
51namespace gem5
52{
53
54namespace ruby
55{
56
57class Switch;
58
60{
61 public:
63
65 :SimObject(p)
66 {
67 }
68
69 virtual void addOutPort(LinkID link_id,
70 const std::vector<MessageBuffer*>& m_out_buffer,
71 const NetDest& routing_table_entry,
72 const PortDirection &direction,
73 int link_weight) = 0;
74
75 struct RouteInfo
76 {
77 RouteInfo(const NetDest &dests, const LinkID link_id)
78 :m_destinations(dests), m_link_id(link_id)
79 {}
82 };
83
84 virtual void route(const Message &msg,
85 int vnet,
86 bool deterministic,
87 std::vector<RouteInfo> &out_links) = 0;
88
89 void init_parent(Switch *parent_switch)
90 { m_parent_switch = parent_switch; }
91
92 protected:
93
95
96};
97
98} // namespace ruby
99} // namespace gem5
100
101#endif // __MEM_RUBY_NETWORK_SIMPLE_BASEROUTINGUNIT_HH__
Abstract superclass for simulation objects.
SimObjectParams Params
virtual void addOutPort(LinkID link_id, const std::vector< MessageBuffer * > &m_out_buffer, const NetDest &routing_table_entry, const PortDirection &direction, int link_weight)=0
virtual void route(const Message &msg, int vnet, bool deterministic, std::vector< RouteInfo > &out_links)=0
void init_parent(Switch *parent_switch)
STL vector class.
Definition stl.hh:37
Bitfield< 0 > p
unsigned int LinkID
std::string PortDirection
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
RouteInfo(const NetDest &dests, const LinkID link_id)

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