gem5  v22.0.0.2
amo.hh
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1 /*
2  * Copyright (c) 2015 RISC-V Foundation
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29 
30 #ifndef __ARCH_RISCV_INSTS_AMO_HH__
31 #define __ARCH_RISCV_INSTS_AMO_HH__
32 
33 #include <string>
34 
35 #include "arch/riscv/insts/mem.hh"
37 #include "cpu/static_inst.hh"
38 
39 namespace gem5
40 {
41 
42 namespace RiscvISA
43 {
44 
45 // memfence micro instruction
47 {
48  public:
49  MemFenceMicro(ExtMachInst _machInst, OpClass __opClass)
50  : RiscvMicroInst("fence", _machInst, __opClass)
51  { }
52  protected:
54 
55  Fault execute(ExecContext *, Trace::InstRecord *) const override;
56  std::string generateDisassembly(
57  Addr pc, const loader::SymbolTable *symtab) const override;
58 };
59 
60 // load-reserved
62 {
63  protected:
65 
66  std::string generateDisassembly(
67  Addr pc, const loader::SymbolTable *symtab) const override;
68 };
69 
71 {
72  protected:
75 
76  std::string generateDisassembly(
77  Addr pc, const loader::SymbolTable *symtab) const override;
78 };
79 
80 // store-cond
81 class StoreCond : public RiscvMacroInst
82 {
83  protected:
85 
86  std::string generateDisassembly(
87  Addr pc, const loader::SymbolTable *symtab) const override;
88 };
89 
91 {
92  protected:
95 
96  std::string generateDisassembly(
97  Addr pc, const loader::SymbolTable *symtab) const override;
98 };
99 
100 // AMOs
102 {
103  protected:
105 
106  std::string generateDisassembly(
107  Addr pc, const loader::SymbolTable *symtab) const override;
108 };
109 
111 {
112  protected:
115 
116  std::string generateDisassembly(
117  Addr pc, const loader::SymbolTable *symtab) const override;
118 };
119 
124 template<typename T>
126 {
127  public:
128  AtomicGenericOp(T _a, std::function<void(T*,T)> _op)
129  : a(_a), op(_op) { }
130  AtomicOpFunctor* clone() { return new AtomicGenericOp<T>(*this); }
131  void execute(T *b) { op(b, a); }
132  private:
133  T a;
134  std::function<void(T*,T)> op;
135 };
136 
137 } // namespace RiscvISA
138 } // namespace gem5
139 
140 #endif // __ARCH_RISCV_INSTS_AMO_HH__
gem5::RiscvISA::MemFenceMicro::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: amo.cc:48
mem.hh
gem5::RiscvISA::AtomicGenericOp::execute
void execute(T *b)
Definition: amo.hh:131
gem5::RiscvISA::StoreCondMicro::memAccessFlags
Request::Flags memAccessFlags
Definition: amo.hh:93
gem5::AtomicOpFunctor
Definition: amo.hh:43
gem5::RiscvISA::RiscvMicroInst::RiscvMicroInst
RiscvMicroInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:142
gem5::RiscvISA::RiscvMacroInst
Base class for all RISC-V Macroops.
Definition: static_inst.hh:96
gem5::RiscvISA::RiscvMacroInst::RiscvMacroInst
RiscvMacroInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:101
gem5::RiscvISA::LoadReservedMicro::memAccessFlags
Request::Flags memAccessFlags
Definition: amo.hh:73
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::RiscvISA::AtomicGenericOp::clone
AtomicOpFunctor * clone()
Definition: amo.hh:130
gem5::RiscvISA::AtomicGenericOp::op
std::function< void(T *, T)> op
Definition: amo.hh:134
gem5::RiscvISA::MemFenceMicro::execute
Fault execute(ExecContext *, Trace::InstRecord *) const override
Definition: amo.cc:56
gem5::TypedAtomicOpFunctor
Definition: amo.hh:56
gem5::RiscvISA::AtomicGenericOp::AtomicGenericOp
AtomicGenericOp(T _a, std::function< void(T *, T)> _op)
Definition: amo.hh:128
gem5::Flags< FlagsType >
gem5::RiscvISA::StoreCond
Definition: amo.hh:81
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:382
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::RiscvISA::MemFenceMicro::MemFenceMicro
MemFenceMicro(ExtMachInst _machInst, OpClass __opClass)
Definition: amo.hh:49
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::RiscvISA::StoreCondMicro::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: amo.cc:110
gem5::RiscvISA::AtomicMemOpMicro::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: amo.cc:140
static_inst.hh
gem5::RiscvISA::LoadReserved::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: amo.cc:64
gem5::RiscvISA::AtomicMemOpMicro
Definition: amo.hh:110
gem5::RiscvISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:54
gem5::RiscvISA::LoadReservedMicro::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: amo.cc:81
static_inst.hh
gem5::RiscvISA::AtomicMemOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: amo.cc:122
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::LoadReserved
Definition: amo.hh:61
gem5::RiscvISA::AtomicGenericOp::a
T a
Definition: amo.hh:133
gem5::RiscvISA::StoreCondMicro
Definition: amo.hh:90
gem5::RiscvISA::MemFenceMicro
Definition: amo.hh:46
gem5::RiscvISA::StoreCond::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: amo.cc:92
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::RiscvISA::AtomicGenericOp
A generic atomic op class.
Definition: amo.hh:125
gem5::RiscvISA::RiscvMicroInst
Base class for all RISC-V Microops.
Definition: static_inst.hh:139
gem5::Trace::InstRecord
Definition: insttracer.hh:61
gem5::RiscvISA::LoadReservedMicro
Definition: amo.hh:70
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::RiscvISA::AtomicMemOp
Definition: amo.hh:101
gem5::RiscvISA::AtomicMemOpMicro::memAccessFlags
Request::Flags memAccessFlags
Definition: amo.hh:113

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