gem5  v21.1.0.2
amo.cc
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1 /*
2  * Copyright (c) 2015 RISC-V Foundation
3  * Copyright (c) 2017 The University of Virginia
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are
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9  * notice, this list of conditions and the following disclaimer;
10  * redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution;
13  * neither the name of the copyright holders nor the names of its
14  * contributors may be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 #include "arch/riscv/insts/amo.hh"
31 
32 #include <sstream>
33 #include <string>
34 
36 #include "arch/riscv/utility.hh"
37 #include "cpu/exec_context.hh"
38 #include "cpu/static_inst.hh"
39 
40 namespace gem5
41 {
42 
43 namespace RiscvISA
44 {
45 
46 // memfence micro instruction
47 std::string
49  Addr pc, const loader::SymbolTable *symtab) const
50 {
51  std::stringstream ss;
52  ss << csprintf("0x%08x", machInst) << ' ' << mnemonic;
53  return ss.str();
54 }
55 
57  Trace::InstRecord *traceData) const
58 {
59  return NoFault;
60 }
61 
62 // load-reserved
63 std::string
65  Addr pc, const loader::SymbolTable *symtab) const
66 {
67  std::stringstream ss;
68  ss << mnemonic;
69  if (AQ || RL)
70  ss << '_';
71  if (AQ)
72  ss << "aq";
73  if (RL)
74  ss << "rl";
75  ss << ' ' << registerName(RegId(IntRegClass, RD)) << ", ("
76  << registerName(RegId(IntRegClass, RS1)) << ')';
77  return ss.str();
78 }
79 
80 std::string
82  Addr pc, const loader::SymbolTable *symtab) const
83 {
84  std::stringstream ss;
85  ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", ("
86  << registerName(srcRegIdx(0)) << ')';
87  return ss.str();
88 }
89 
90 // store-conditional
91 std::string
93  Addr pc, const loader::SymbolTable *symtab) const
94 {
95  std::stringstream ss;
96  ss << mnemonic;
97  if (AQ || RL)
98  ss << '_';
99  if (AQ)
100  ss << "aq";
101  if (RL)
102  ss << "rl";
103  ss << ' ' << registerName(RegId(IntRegClass, RD)) << ", "
104  << registerName(RegId(IntRegClass, RS2)) << ", ("
105  << registerName(RegId(IntRegClass, RS1)) << ')';
106  return ss.str();
107 }
108 
109 std::string
111  Addr pc, const loader::SymbolTable *symtab) const
112 {
113  std::stringstream ss;
114  ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
115  << registerName(srcRegIdx(1)) << ", ("
116  << registerName(srcRegIdx(0)) << ')';
117  return ss.str();
118 }
119 
120 // AMOs
121 std::string
123  Addr pc, const loader::SymbolTable *symtab) const
124 {
125  std::stringstream ss;
126  ss << mnemonic;
127  if (AQ || RL)
128  ss << '_';
129  if (AQ)
130  ss << "aq";
131  if (RL)
132  ss << "rl";
133  ss << ' ' << registerName(RegId(IntRegClass, RD)) << ", "
134  << registerName(RegId(IntRegClass, RS2)) << ", ("
135  << registerName(RegId(IntRegClass, RS1)) << ')';
136  return ss.str();
137 }
138 
139 std::string
141  Addr pc, const loader::SymbolTable *symtab) const
142 {
143  std::stringstream ss;
144  ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
145  << registerName(srcRegIdx(1)) << ", ("
146  << registerName(srcRegIdx(0)) << ')';
147  return ss.str();
148 }
149 
150 } // namespace RiscvISA
151 } // namespace gem5
gem5::RiscvISA::MemFenceMicro::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: amo.cc:48
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
RS1
#define RS1
Definition: bitfields.hh:16
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::RiscvISA::MemFenceMicro::execute
Fault execute(ExecContext *, Trace::InstRecord *) const override
Definition: amo.cc:56
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:237
gem5::RiscvISA::registerName
std::string registerName(RegId reg)
Definition: utility.hh:106
gem5::RiscvISA::ss
Bitfield< 11, 8 > ss
Definition: pra_constants.hh:257
gem5::RiscvISA::RiscvStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:58
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
RS2
#define RS2
Definition: bitfields.hh:17
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:247
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::RiscvISA::StoreCondMicro::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: amo.cc:110
gem5::RiscvISA::AtomicMemOpMicro::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: amo.cc:140
static_inst.hh
gem5::RiscvISA::LoadReserved::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: amo.cc:64
gem5::RiscvISA::LoadReservedMicro::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: amo.cc:81
gem5::RiscvISA::AtomicMemOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: amo.cc:122
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
RL
#define RL
Definition: bitfields.hh:15
RD
#define RD
Definition: bitfields.hh:14
gem5::RiscvISA::StoreCond::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: amo.cc:92
AQ
#define AQ
Definition: bitfields.hh:13
exec_context.hh
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
utility.hh
gem5::Trace::InstRecord
Definition: insttracer.hh:58
bitfields.hh
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
amo.hh

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