gem5  v22.0.0.2
exec_context.hh
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41 
42 #ifndef __CPU_EXEC_CONTEXT_HH__
43 #define __CPU_EXEC_CONTEXT_HH__
44 
45 #include "arch/vecregs.hh"
46 #include "base/types.hh"
47 #include "config/the_isa.hh"
48 #include "cpu/base.hh"
49 #include "cpu/reg_class.hh"
50 #include "cpu/static_inst_fwd.hh"
51 #include "cpu/translation.hh"
52 #include "mem/request.hh"
53 
54 namespace gem5
55 {
56 
74 {
75  public:
76 
77  virtual RegVal getRegOperand(const StaticInst *si, int idx) = 0;
78  virtual void getRegOperand(const StaticInst *si, int idx, void *val) = 0;
79  virtual void *getWritableRegOperand(const StaticInst *si, int idx) = 0;
80  virtual void setRegOperand(const StaticInst *si, int idx, RegVal val) = 0;
81  virtual void setRegOperand(const StaticInst *si, int idx,
82  const void *val) = 0;
83 
88  virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
89  virtual void setMiscRegOperand(const StaticInst *si,
90  int idx, RegVal val) = 0;
91 
96  virtual RegVal readMiscReg(int misc_reg) = 0;
97 
102  virtual void setMiscReg(int misc_reg, RegVal val) = 0;
103 
110  virtual const PCStateBase &pcState() const = 0;
111  virtual void pcState(const PCStateBase &val) = 0;
125  virtual Fault
126  readMem(Addr addr, uint8_t *data, unsigned int size,
127  Request::Flags flags, const std::vector<bool>& byte_enable)
128  {
129  panic("ExecContext::readMem() should be overridden\n");
130  }
131 
139  virtual Fault
140  initiateMemRead(Addr addr, unsigned int size,
141  Request::Flags flags, const std::vector<bool>& byte_enable)
142  {
143  panic("ExecContext::initiateMemRead() should be overridden\n");
144  }
145 
154 
159  virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
160  Request::Flags flags, uint64_t *res,
161  const std::vector<bool>& byte_enable) = 0;
162 
167  virtual Fault
168  amoMem(Addr addr, uint8_t *data, unsigned int size,
170  {
171  panic("ExecContext::amoMem() should be overridden\n");
172  }
173 
178  virtual Fault
180  AtomicOpFunctorPtr amo_op)
181  {
182  panic("ExecContext::initiateMemAMO() should be overridden\n");
183  }
184 
188  virtual void setStCondFailures(unsigned int sc_failures) = 0;
189 
193  virtual unsigned int readStCondFailures() const = 0;
194 
198  virtual ThreadContext *tcBase() const = 0;
199 
205  virtual bool readPredicate() const = 0;
206  virtual void setPredicate(bool val) = 0;
207  virtual bool readMemAccPredicate() const = 0;
208  virtual void setMemAccPredicate(bool val) = 0;
209 
210  // hardware transactional memory
211  virtual uint64_t newHtmTransactionUid() const = 0;
212  virtual uint64_t getHtmTransactionUid() const = 0;
213  virtual bool inHtmTransactionalState() const = 0;
214  virtual uint64_t getHtmTransactionalDepth() const = 0;
215 
226  virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
227  virtual void armMonitor(Addr address) = 0;
228  virtual bool mwait(PacketPtr pkt) = 0;
229  virtual void mwaitAtomic(ThreadContext *tc) = 0;
230  virtual AddressMonitor *getAddrMonitor() = 0;
231 
233 };
234 
235 } // namespace gem5
236 
237 #endif // __CPU_EXEC_CONTEXT_HH__
gem5::ExecContext::setStCondFailures
virtual void setStCondFailures(unsigned int sc_failures)=0
Sets the number of consecutive store conditional failures.
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ExecContext::setMemAccPredicate
virtual void setMemAccPredicate(bool val)=0
gem5::ExecContext::setMiscReg
virtual void setMiscReg(int misc_reg, RegVal val)=0
Sets a miscellaneous register, handling any architectural side effects due to writing that register.
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::ExecContext::readStCondFailures
virtual unsigned int readStCondFailures() const =0
Returns the number of consecutive store conditional failures.
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::ExecContext::inHtmTransactionalState
virtual bool inHtmTransactionalState() const =0
std::vector< bool >
gem5::ExecContext::readMiscReg
virtual RegVal readMiscReg(int misc_reg)=0
Reads a miscellaneous register, handling any architectural side effects due to reading that register.
gem5::ExecContext::getAddrMonitor
virtual AddressMonitor * getAddrMonitor()=0
gem5::ExecContext::mwaitAtomic
virtual void mwaitAtomic(ThreadContext *tc)=0
request.hh
gem5::ExecContext::readPredicate
virtual bool readPredicate() const =0
gem5::Flags< FlagsType >
translation.hh
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:88
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::ExecContext::initiateMemMgmtCmd
virtual Fault initiateMemMgmtCmd(Request::Flags flags)=0
Initiate a memory management command with no valid address.
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::ExecContext::writeMem
virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)=0
For atomic-mode contexts, perform an atomic memory write operation.
gem5::ExecContext::demapPage
virtual void demapPage(Addr vaddr, uint64_t asn)=0
Invalidate a page in the DTLB and ITLB.
gem5::ExecContext::tcBase
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
gem5::ExecContext::initiateMemRead
virtual Fault initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
Initiate a timing memory read operation.
Definition: exec_context.hh:140
flags
uint8_t flags
Definition: helpers.cc:66
gem5::ExecContext::readMemAccPredicate
virtual bool readMemAccPredicate() const =0
gem5::ExecContext::getHtmTransactionUid
virtual uint64_t getHtmTransactionUid() const =0
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:825
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ExecContext::setRegOperand
virtual void setRegOperand(const StaticInst *si, int idx, RegVal val)=0
gem5::ExecContext::setMiscRegOperand
virtual void setMiscRegOperand(const StaticInst *si, int idx, RegVal val)=0
gem5::ExecContext::getWritableRegOperand
virtual void * getWritableRegOperand(const StaticInst *si, int idx)=0
gem5::ExecContext::readMem
virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
Perform an atomic memory read operation.
Definition: exec_context.hh:126
gem5::ExecContext::newHtmTransactionUid
virtual uint64_t newHtmTransactionUid() const =0
gem5::ExecContext::pcState
virtual const PCStateBase & pcState() const =0
base.hh
types.hh
static_inst_fwd.hh
gem5::ExecContext::readMiscRegOperand
virtual RegVal readMiscRegOperand(const StaticInst *si, int idx)=0
reg_class.hh
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::ExecContext::getRegOperand
virtual RegVal getRegOperand(const StaticInst *si, int idx)=0
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::ExecContext::initiateMemAMO
virtual Fault initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)
Definition: exec_context.hh:179
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ExecContext::armMonitor
virtual void armMonitor(Addr address)=0
gem5::ExecContext::getHtmTransactionalDepth
virtual uint64_t getHtmTransactionalDepth() const =0
gem5::ExecContext::setPredicate
virtual void setPredicate(bool val)=0
gem5::ExecContext::amoMem
virtual Fault amoMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)
Definition: exec_context.hh:168
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ExecContext::mwait
virtual bool mwait(PacketPtr pkt)=0

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