gem5  v21.2.1.1
exec_context.hh
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41 
42 #ifndef __CPU_EXEC_CONTEXT_HH__
43 #define __CPU_EXEC_CONTEXT_HH__
44 
45 #include "arch/vecregs.hh"
46 #include "base/types.hh"
47 #include "config/the_isa.hh"
48 #include "cpu/base.hh"
49 #include "cpu/reg_class.hh"
50 #include "cpu/static_inst_fwd.hh"
51 #include "cpu/translation.hh"
52 #include "mem/request.hh"
53 
54 namespace gem5
55 {
56 
74 {
75  public:
83  virtual RegVal readIntRegOperand(const StaticInst *si, int idx) = 0;
84 
86  virtual void setIntRegOperand(const StaticInst *si,
87  int idx, RegVal val) = 0;
88 
99  virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx) = 0;
100 
103  virtual void setFloatRegOperandBits(const StaticInst *si,
104  int idx, RegVal val) = 0;
105 
112  const StaticInst *si, int idx) const = 0;
113 
116  const StaticInst *si, int idx) = 0;
117 
119  virtual void setVecRegOperand(const StaticInst *si, int idx,
120  const TheISA::VecRegContainer& val) = 0;
126  virtual RegVal readVecElemOperand(const StaticInst *si, int idx) const = 0;
127 
129  virtual void setVecElemOperand(
130  const StaticInst *si, int idx, RegVal val) = 0;
137  const StaticInst *si, int idx) const = 0;
138 
141  const StaticInst *si, int idx) = 0;
142 
144  virtual void setVecPredRegOperand(
145  const StaticInst *si, int idx,
146  const TheISA::VecPredRegContainer& val) = 0;
153  virtual RegVal readCCRegOperand(const StaticInst *si, int idx) = 0;
154  virtual void setCCRegOperand(
155  const StaticInst *si, int idx, RegVal val) = 0;
162  virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
163  virtual void setMiscRegOperand(const StaticInst *si,
164  int idx, RegVal val) = 0;
165 
170  virtual RegVal readMiscReg(int misc_reg) = 0;
171 
176  virtual void setMiscReg(int misc_reg, RegVal val) = 0;
177 
184  virtual const PCStateBase &pcState() const = 0;
185  virtual void pcState(const PCStateBase &val) = 0;
199  virtual Fault
200  readMem(Addr addr, uint8_t *data, unsigned int size,
201  Request::Flags flags, const std::vector<bool>& byte_enable)
202  {
203  panic("ExecContext::readMem() should be overridden\n");
204  }
205 
213  virtual Fault
214  initiateMemRead(Addr addr, unsigned int size,
215  Request::Flags flags, const std::vector<bool>& byte_enable)
216  {
217  panic("ExecContext::initiateMemRead() should be overridden\n");
218  }
219 
224  virtual Fault initiateHtmCmd(Request::Flags flags) = 0;
229  virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
230  Request::Flags flags, uint64_t *res,
231  const std::vector<bool>& byte_enable) = 0;
232 
237  virtual Fault
238  amoMem(Addr addr, uint8_t *data, unsigned int size,
239  Request::Flags flags, AtomicOpFunctorPtr amo_op)
240  {
241  panic("ExecContext::amoMem() should be overridden\n");
242  }
243 
248  virtual Fault
249  initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags,
250  AtomicOpFunctorPtr amo_op)
251  {
252  panic("ExecContext::initiateMemAMO() should be overridden\n");
253  }
254 
258  virtual void setStCondFailures(unsigned int sc_failures) = 0;
259 
263  virtual unsigned int readStCondFailures() const = 0;
264 
268  virtual ThreadContext *tcBase() const = 0;
269 
275  virtual bool readPredicate() const = 0;
276  virtual void setPredicate(bool val) = 0;
277  virtual bool readMemAccPredicate() const = 0;
278  virtual void setMemAccPredicate(bool val) = 0;
279 
280  // hardware transactional memory
281  virtual uint64_t newHtmTransactionUid() const = 0;
282  virtual uint64_t getHtmTransactionUid() const = 0;
283  virtual bool inHtmTransactionalState() const = 0;
284  virtual uint64_t getHtmTransactionalDepth() const = 0;
285 
296  virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
297  virtual void armMonitor(Addr address) = 0;
298  virtual bool mwait(PacketPtr pkt) = 0;
299  virtual void mwaitAtomic(ThreadContext *tc) = 0;
300  virtual AddressMonitor *getAddrMonitor() = 0;
301 
303 };
304 
305 } // namespace gem5
306 
307 #endif // __CPU_EXEC_CONTEXT_HH__
gem5::ExecContext::setStCondFailures
virtual void setStCondFailures(unsigned int sc_failures)=0
Sets the number of consecutive store conditional failures.
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ExecContext::setMemAccPredicate
virtual void setMemAccPredicate(bool val)=0
gem5::ExecContext::setMiscReg
virtual void setMiscReg(int misc_reg, RegVal val)=0
Sets a miscellaneous register, handling any architectural side effects due to writing that register.
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::ExecContext::setVecElemOperand
virtual void setVecElemOperand(const StaticInst *si, int idx, RegVal val)=0
Sets a vector register to a value.
gem5::ExecContext::readIntRegOperand
virtual RegVal readIntRegOperand(const StaticInst *si, int idx)=0
Reads an integer register.
gem5::ExecContext::readStCondFailures
virtual unsigned int readStCondFailures() const =0
Returns the number of consecutive store conditional failures.
gem5::ExecContext::setCCRegOperand
virtual void setCCRegOperand(const StaticInst *si, int idx, RegVal val)=0
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ExecContext::inHtmTransactionalState
virtual bool inHtmTransactionalState() const =0
std::vector< bool >
gem5::ExecContext::getWritableVecRegOperand
virtual TheISA::VecRegContainer & getWritableVecRegOperand(const StaticInst *si, int idx)=0
Gets destination vector register operand for modification.
gem5::ExecContext::readMiscReg
virtual RegVal readMiscReg(int misc_reg)=0
Reads a miscellaneous register, handling any architectural side effects due to reading that register.
gem5::ExecContext::getAddrMonitor
virtual AddressMonitor * getAddrMonitor()=0
gem5::ExecContext::mwaitAtomic
virtual void mwaitAtomic(ThreadContext *tc)=0
request.hh
gem5::ExecContext::setIntRegOperand
virtual void setIntRegOperand(const StaticInst *si, int idx, RegVal val)=0
Sets an integer register to a value.
gem5::ExecContext::readPredicate
virtual bool readPredicate() const =0
gem5::Flags< FlagsType >
translation.hh
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:87
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ExecContext::setVecRegOperand
virtual void setVecRegOperand(const StaticInst *si, int idx, const TheISA::VecRegContainer &val)=0
Sets a destination vector register operand to a value.
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ExecContext::writeMem
virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)=0
For atomic-mode contexts, perform an atomic memory write operation.
gem5::ExecContext::setVecPredRegOperand
virtual void setVecPredRegOperand(const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val)=0
Sets a destination predicate register operand to a value.
gem5::ExecContext::demapPage
virtual void demapPage(Addr vaddr, uint64_t asn)=0
Invalidate a page in the DTLB and ITLB.
gem5::ExecContext::tcBase
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
gem5::ExecContext::initiateMemRead
virtual Fault initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
Initiate a timing memory read operation.
Definition: exec_context.hh:214
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::ExecContext::readVecElemOperand
virtual RegVal readVecElemOperand(const StaticInst *si, int idx) const =0
Vector Elem Interfaces.
gem5::ExecContext::readMemAccPredicate
virtual bool readMemAccPredicate() const =0
gem5::ExecContext::getHtmTransactionUid
virtual uint64_t getHtmTransactionUid() const =0
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:773
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ExecContext::initiateHtmCmd
virtual Fault initiateHtmCmd(Request::Flags flags)=0
Initiate an HTM command, e.g.
gem5::ExecContext::setMiscRegOperand
virtual void setMiscRegOperand(const StaticInst *si, int idx, RegVal val)=0
gem5::ExecContext::readMem
virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
Perform an atomic memory read operation.
Definition: exec_context.hh:200
gem5::ExecContext::newHtmTransactionUid
virtual uint64_t newHtmTransactionUid() const =0
gem5::ExecContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ExecContext::readVecPredRegOperand
virtual const TheISA::VecPredRegContainer & readVecPredRegOperand(const StaticInst *si, int idx) const =0
Predicate registers interface.
base.hh
types.hh
static_inst_fwd.hh
gem5::ExecContext::readMiscRegOperand
virtual RegVal readMiscRegOperand(const StaticInst *si, int idx)=0
reg_class.hh
gem5::ExecContext::getWritableVecPredRegOperand
virtual TheISA::VecPredRegContainer & getWritableVecPredRegOperand(const StaticInst *si, int idx)=0
Gets destination predicate register operand for modification.
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::ExecContext::setFloatRegOperandBits
virtual void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)=0
Sets the bits of a floating point register of single width to a binary value.
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::ExecContext::initiateMemAMO
virtual Fault initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)
Definition: exec_context.hh:249
gem5::ExecContext::readCCRegOperand
virtual RegVal readCCRegOperand(const StaticInst *si, int idx)=0
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ExecContext::armMonitor
virtual void armMonitor(Addr address)=0
gem5::ExecContext::getHtmTransactionalDepth
virtual uint64_t getHtmTransactionalDepth() const =0
gem5::ExecContext::setPredicate
virtual void setPredicate(bool val)=0
gem5::ExecContext::amoMem
virtual Fault amoMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)
Definition: exec_context.hh:238
gem5::ExecContext::readVecRegOperand
virtual const TheISA::VecRegContainer & readVecRegOperand(const StaticInst *si, int idx) const =0
Vector Register Interfaces.
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ExecContext::mwait
virtual bool mwait(PacketPtr pkt)=0
gem5::ExecContext::readFloatRegOperandBits
virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx)=0
Reads a floating point register in its binary format, instead of by value.

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