gem5  v22.1.0.0
exec_context.hh
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41 
42 #ifndef __CPU_EXEC_CONTEXT_HH__
43 #define __CPU_EXEC_CONTEXT_HH__
44 
45 #include "base/types.hh"
46 #include "cpu/base.hh"
47 #include "cpu/reg_class.hh"
48 #include "cpu/static_inst_fwd.hh"
49 #include "cpu/translation.hh"
50 #include "mem/request.hh"
51 
52 namespace gem5
53 {
54 
72 {
73  public:
74 
75  virtual RegVal getRegOperand(const StaticInst *si, int idx) = 0;
76  virtual void getRegOperand(const StaticInst *si, int idx, void *val) = 0;
77  virtual void *getWritableRegOperand(const StaticInst *si, int idx) = 0;
78  virtual void setRegOperand(const StaticInst *si, int idx, RegVal val) = 0;
79  virtual void setRegOperand(const StaticInst *si, int idx,
80  const void *val) = 0;
81 
86  virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
87  virtual void setMiscRegOperand(const StaticInst *si,
88  int idx, RegVal val) = 0;
89 
94  virtual RegVal readMiscReg(int misc_reg) = 0;
95 
100  virtual void setMiscReg(int misc_reg, RegVal val) = 0;
101 
108  virtual const PCStateBase &pcState() const = 0;
109  virtual void pcState(const PCStateBase &val) = 0;
123  virtual Fault
124  readMem(Addr addr, uint8_t *data, unsigned int size,
125  Request::Flags flags, const std::vector<bool>& byte_enable)
126  {
127  panic("ExecContext::readMem() should be overridden\n");
128  }
129 
137  virtual Fault
138  initiateMemRead(Addr addr, unsigned int size,
139  Request::Flags flags, const std::vector<bool>& byte_enable)
140  {
141  panic("ExecContext::initiateMemRead() should be overridden\n");
142  }
143 
152 
157  virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
158  Request::Flags flags, uint64_t *res,
159  const std::vector<bool>& byte_enable) = 0;
160 
165  virtual Fault
166  amoMem(Addr addr, uint8_t *data, unsigned int size,
168  {
169  panic("ExecContext::amoMem() should be overridden\n");
170  }
171 
176  virtual Fault
178  AtomicOpFunctorPtr amo_op)
179  {
180  panic("ExecContext::initiateMemAMO() should be overridden\n");
181  }
182 
186  virtual void setStCondFailures(unsigned int sc_failures) = 0;
187 
191  virtual unsigned int readStCondFailures() const = 0;
192 
196  virtual ThreadContext *tcBase() const = 0;
197 
203  virtual bool readPredicate() const = 0;
204  virtual void setPredicate(bool val) = 0;
205  virtual bool readMemAccPredicate() const = 0;
206  virtual void setMemAccPredicate(bool val) = 0;
207 
208  // hardware transactional memory
209  virtual uint64_t newHtmTransactionUid() const = 0;
210  virtual uint64_t getHtmTransactionUid() const = 0;
211  virtual bool inHtmTransactionalState() const = 0;
212  virtual uint64_t getHtmTransactionalDepth() const = 0;
213 
224  virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
225  virtual void armMonitor(Addr address) = 0;
226  virtual bool mwait(PacketPtr pkt) = 0;
227  virtual void mwaitAtomic(ThreadContext *tc) = 0;
229 
231 };
232 
233 } // namespace gem5
234 
235 #endif // __CPU_EXEC_CONTEXT_HH__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
const char data[]
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:72
virtual Fault initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
Initiate a timing memory read operation.
virtual void armMonitor(Addr address)=0
virtual uint64_t getHtmTransactionUid() const =0
virtual Fault initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)
virtual bool mwait(PacketPtr pkt)=0
virtual Fault amoMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)
virtual void setRegOperand(const StaticInst *si, int idx, RegVal val)=0
virtual void mwaitAtomic(ThreadContext *tc)=0
virtual Fault initiateMemMgmtCmd(Request::Flags flags)=0
Initiate a memory management command with no valid address.
virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
Perform an atomic memory read operation.
virtual const PCStateBase & pcState() const =0
virtual void setRegOperand(const StaticInst *si, int idx, const void *val)=0
virtual uint64_t newHtmTransactionUid() const =0
virtual RegVal readMiscReg(int misc_reg)=0
Reads a miscellaneous register, handling any architectural side effects due to reading that register.
virtual void setMiscReg(int misc_reg, RegVal val)=0
Sets a miscellaneous register, handling any architectural side effects due to writing that register.
virtual bool readPredicate() const =0
virtual bool readMemAccPredicate() const =0
virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)=0
For atomic-mode contexts, perform an atomic memory write operation.
virtual RegVal getRegOperand(const StaticInst *si, int idx)=0
virtual void * getWritableRegOperand(const StaticInst *si, int idx)=0
virtual AddressMonitor * getAddrMonitor()=0
virtual void setPredicate(bool val)=0
virtual void setStCondFailures(unsigned int sc_failures)=0
Sets the number of consecutive store conditional failures.
virtual void setMemAccPredicate(bool val)=0
virtual void setMiscRegOperand(const StaticInst *si, int idx, RegVal val)=0
virtual bool inHtmTransactionalState() const =0
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
virtual void getRegOperand(const StaticInst *si, int idx, void *val)=0
virtual uint64_t getHtmTransactionalDepth() const =0
virtual RegVal readMiscRegOperand(const StaticInst *si, int idx)=0
virtual unsigned int readStCondFailures() const =0
Returns the number of consecutive store conditional failures.
virtual void pcState(const PCStateBase &val)=0
virtual void demapPage(Addr vaddr, uint64_t asn)=0
Invalidate a page in the DTLB and ITLB.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:294
Base, ISA-independent static instruction class.
Definition: static_inst.hh:89
ThreadContext is the external interface to all thread state for anything outside of the CPU.
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
uint8_t flags
Definition: helpers.cc:66
Bitfield< 6 > si
Definition: misc_types.hh:831
Bitfield< 63 > val
Definition: misc.hh:776
Bitfield< 3 > addr
Definition: types.hh:84
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
uint64_t RegVal
Definition: types.hh:173
Declaration of a request, the overall memory request consisting of the parts of the request that are ...

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