gem5  v21.1.0.2
static_inst.cc
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1 /*
2  * Copyright (c) 2015 RISC-V Foundation
3  * Copyright (c) 2016 The University of Virginia
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28  */
29 
31 
32 #include "arch/riscv/types.hh"
33 #include "cpu/static_inst.hh"
34 
35 namespace gem5
36 {
37 
38 namespace RiscvISA
39 {
40 
41 void
43 {
44  if (flags[IsLastMicroop]) {
45  pcState.uEnd();
46  } else {
47  pcState.uAdvance();
48  }
49 }
50 
51 } // namespace RiscvISA
52 } // namespace gem5
gem5::RiscvISA::PCState
Definition: pcstate.hh:53
types.hh
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
static_inst.hh
static_inst.hh
gem5::GenericISA::UPCState::uAdvance
void uAdvance()
Definition: types.hh:240
gem5::RiscvISA::RiscvMicroInst::advancePC
void advancePC(PCState &pcState) const override
Definition: static_inst.cc:42
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::GenericISA::UPCState::uEnd
void uEnd()
Definition: types.hh:248

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