gem5
v21.2.1.1
arch
riscv
insts
static_inst.cc
Go to the documentation of this file.
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/*
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* Copyright (c) 2015 RISC-V Foundation
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* Copyright (c) 2016 The University of Virginia
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
arch/riscv/insts/static_inst.hh
"
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#include "
arch/riscv/pcstate.hh
"
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#include "
arch/riscv/types.hh
"
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#include "
cpu/static_inst.hh
"
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namespace
gem5
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{
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namespace
RiscvISA
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{
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void
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RiscvMicroInst::advancePC
(
PCStateBase
&pcState)
const
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{
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auto
&rpc = pcState.
as
<
PCState
>();
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if
(
flags
[IsLastMicroop]) {
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rpc.
uEnd
();
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}
else
{
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rpc.uAdvance();
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}
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}
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void
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RiscvMicroInst::advancePC
(
ThreadContext
*tc)
const
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{
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PCState
pc
= tc->
pcState
().
as
<
PCState
>();
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if
(
flags
[IsLastMicroop]) {
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pc
.uEnd();
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}
else
{
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pc
.uAdvance();
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}
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tc->
pcState
(
pc
);
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}
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}
// namespace RiscvISA
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}
// namespace gem5
gem5::PCStateBase::as
Target & as()
Definition:
pcstate.hh:72
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::RiscvISA::RiscvMicroInst::advancePC
void advancePC(PCStateBase &pcState) const override
Definition:
static_inst.cc:43
gem5::RiscvISA::PCState
Definition:
pcstate.hh:53
pcstate.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition:
thread_context.hh:94
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition:
pra_constants.hh:243
types.hh
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition:
static_inst.hh:102
static_inst.hh
static_inst.hh
gem5::PCStateBase
Definition:
pcstate.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition:
tlb.cc:60
gem5::GenericISA::UPCState::uEnd
void uEnd()
Definition:
pcstate.hh:434
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