gem5  v22.0.0.2
static_inst.cc
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29 
31 
32 #include "arch/riscv/pcstate.hh"
33 #include "arch/riscv/types.hh"
34 #include "cpu/static_inst.hh"
35 
36 namespace gem5
37 {
38 
39 namespace RiscvISA
40 {
41 
42 void
44 {
45  auto &rpc = pcState.as<PCState>();
46  if (flags[IsLastMicroop]) {
47  rpc.uEnd();
48  } else {
49  rpc.uAdvance();
50  }
51 }
52 
53 void
55 {
56  PCState pc = tc->pcState().as<PCState>();
57  if (flags[IsLastMicroop]) {
58  pc.uEnd();
59  } else {
60  pc.uAdvance();
61  }
62  tc->pcState(pc);
63 }
64 
65 } // namespace RiscvISA
66 } // namespace gem5
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::RiscvISA::RiscvMicroInst::advancePC
void advancePC(PCStateBase &pcState) const override
Definition: static_inst.cc:43
gem5::RiscvISA::PCState
Definition: pcstate.hh:53
pcstate.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
types.hh
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
static_inst.hh
static_inst.hh
gem5::PCStateBase
Definition: pcstate.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::GenericISA::UPCState::uEnd
void uEnd()
Definition: pcstate.hh:434

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