gem5  v21.1.0.2
interrupts.cc
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27 
29 
31 #include "arch/arm/interrupts.hh"
32 #include "arch/arm/regs/misc.hh"
34 #include "arch/arm/types.hh"
35 #include "params/IrisInterrupts.hh"
36 
37 namespace gem5
38 {
39 
40 void
42 {
43  using namespace ArmISA;
44 
45  CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
46  CPSR orig_cpsr = cpsr;
48  SCR orig_scr = scr;
50  HCR orig_hcr = hcr;
51 
52  // Set up state so we can get either physical or virtual interrupt bits.
53  cpsr.mode = 0;
54  cpsr.width = 0;
55  cpsr.el = EL1;
56  tc->setMiscReg(MISCREG_CPSR, cpsr);
57  scr.eel2 = 1;
58  tc->setMiscReg(MISCREG_SCR, scr);
59 
60  // Get the virtual bits.
61  hcr.imo = 1;
62  hcr.fmo = 1;
63  hcr.amo = 1;
65 
67  // There is also a virtual abort, but it's not used by gem5.
68  bool virt_irq = bits(7, isr_el1);
69  bool virt_fiq = bits(6, isr_el1);
70 
71  // Get the physical bits.
72  hcr.imo = 0;
73  hcr.fmo = 0;
74  hcr.amo = 0;
76 
78  bool phys_abort = bits(8, isr_el1);
79  bool phys_irq = bits(7, isr_el1);
80  bool phys_fiq = bits(6, isr_el1);
81 
82  tc->setMiscReg(MISCREG_CPSR, orig_cpsr);
83  tc->setMiscReg(MISCREG_SCR_EL3, orig_scr);
84  tc->setMiscReg(MISCREG_HCR_EL2, orig_hcr);
85 
86  bool interrupts[ArmISA::NumInterruptTypes];
87  uint64_t intStatus = 0;
88 
89  for (bool &i: interrupts)
90  i = false;
91 
92  interrupts[ArmISA::INT_ABT] = phys_abort;
93  interrupts[ArmISA::INT_IRQ] = phys_irq;
94  interrupts[ArmISA::INT_FIQ] = phys_fiq;
96  interrupts[ArmISA::INT_VIRT_IRQ] = virt_irq;
97  interrupts[ArmISA::INT_VIRT_FIQ] = virt_fiq;
98 
99  for (int i = 0; i < NumInterruptTypes; i++) {
100  if (interrupts[i])
101  intStatus |= (0x1ULL << i);
102  }
103 
104  SERIALIZE_ARRAY(interrupts, NumInterruptTypes);
105  SERIALIZE_SCALAR(intStatus);
106 }
107 
108 void
110 {
111 }
112 
113 } // namespace gem5
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::Iris::Interrupts::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: interrupts.cc:41
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::BaseInterrupts::tc
ThreadContext * tc
Definition: interrupts.hh:44
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:593
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ArmISA::INT_VIRT_FIQ
@ INT_VIRT_FIQ
Definition: interrupts.hh:66
gem5::ArmISA::INT_FIQ
@ INT_FIQ
Definition: interrupts.hh:63
gem5::ArmISA::INT_VIRT_IRQ
@ INT_VIRT_IRQ
Definition: interrupts.hh:65
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
types.hh
gem5::ArmISA::INT_ABT
@ INT_ABT
Definition: interrupts.hh:61
interrupts.hh
gem5::Iris::Interrupts::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: interrupts.cc:109
misc_types.hh
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:610
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
interrupts.hh
gem5::ArmISA::INT_IRQ
@ INT_IRQ
Definition: interrupts.hh:62
misc.hh
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:243
gem5::ArmISA::NumInterruptTypes
@ NumInterruptTypes
Definition: interrupts.hh:67
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: misc.hh:92
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:586
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
thread_context.hh
gem5::ArmISA::MISCREG_ISR_EL1
@ MISCREG_ISR_EL1
Definition: misc.hh:739
gem5::ArmISA::INT_SEV
@ INT_SEV
Definition: interrupts.hh:64

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