gem5 v24.0.0.0
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interrupts.cc
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1/*
2 * Copyright 2019 Google Inc.
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6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
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13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26 */
27
29
32#include "arch/arm/regs/misc.hh"
34#include "arch/arm/types.hh"
35#include "params/IrisInterrupts.hh"
36
37namespace gem5
38{
39
40void
42{
43 using namespace ArmISA;
44
46 CPSR orig_cpsr = cpsr;
48 SCR orig_scr = scr;
50 HCR orig_hcr = hcr;
51
52 // Set up state so we can get either physical or virtual interrupt bits.
53 cpsr.mode = 0;
54 cpsr.width = 0;
55 cpsr.el = EL1;
57 scr.eel2 = 1;
59
60 // Get the virtual bits.
61 hcr.imo = 1;
62 hcr.fmo = 1;
63 hcr.amo = 1;
65
67 // There is also a virtual abort, but it's not used by gem5.
68 bool virt_irq = bits(7, isr_el1);
69 bool virt_fiq = bits(6, isr_el1);
70
71 // Get the physical bits.
72 hcr.imo = 0;
73 hcr.fmo = 0;
74 hcr.amo = 0;
76
78 bool phys_abort = bits(8, isr_el1);
79 bool phys_irq = bits(7, isr_el1);
80 bool phys_fiq = bits(6, isr_el1);
81
82 tc->setMiscReg(MISCREG_CPSR, orig_cpsr);
83 tc->setMiscReg(MISCREG_SCR_EL3, orig_scr);
84 tc->setMiscReg(MISCREG_HCR_EL2, orig_hcr);
85
86 bool interrupts[ArmISA::NumInterruptTypes];
87 uint64_t intStatus = 0;
88
89 for (bool &i: interrupts)
90 i = false;
91
92 interrupts[ArmISA::INT_ABT] = phys_abort;
93 interrupts[ArmISA::INT_IRQ] = phys_irq;
94 interrupts[ArmISA::INT_FIQ] = phys_fiq;
96 interrupts[ArmISA::INT_VIRT_IRQ] = virt_irq;
97 interrupts[ArmISA::INT_VIRT_FIQ] = virt_fiq;
98
99 for (int i = 0; i < NumInterruptTypes; i++) {
100 if (interrupts[i])
101 intStatus |= (0x1ULL << i);
102 }
103
105 SERIALIZE_SCALAR(intStatus);
106}
107
108void
112
113} // namespace gem5
ThreadContext * tc
Definition interrupts.hh:44
void unserialize(CheckpointIn &cp) override
Unserialize an object.
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition interrupts.cc:41
virtual RegVal readMiscReg(RegIndex misc_reg)=0
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition bitfield.hh:79
#define SERIALIZE_ARRAY(member, size)
Definition serialize.hh:610
Bitfield< 7 > i
Definition misc_types.hh:67
@ MISCREG_SCR_EL3
Definition misc.hh:604
@ MISCREG_CPSR
Definition misc.hh:67
@ MISCREG_SEV_MAILBOX
Definition misc.hh:97
@ MISCREG_SCR
Definition misc.hh:249
@ MISCREG_HCR_EL2
Definition misc.hh:595
@ MISCREG_ISR_EL1
Definition misc.hh:799
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t RegVal
Definition types.hh:173
std::ostream CheckpointOut
Definition serialize.hh:66
#define SERIALIZE_SCALAR(scalar)
Definition serialize.hh:568

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