interrupts.hh

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#ifndef __ARCH_ARM_INTERRUPT_HH__
#define __ARCH_ARM_INTERRUPT_HH__
 
#include "arch/arm/faults.hh"
#include "arch/arm/regs/misc.hh"
#include "arch/arm/utility.hh"
#include "arch/generic/interrupts.hh"
#include "cpu/thread_context.hh"
#include "debug/Interrupt.hh"
#include "enums/ArmExtension.hh"
#include "params/ArmInterrupts.hh"
 
namespace gem5
{
 
namespace ArmISA
{
 
enum InterruptTypes
{
    INT_RST,
    INT_ABT,
    INT_IRQ,
    INT_FIQ,
    INT_SEV, // Special interrupt for recieving SEV's
    INT_VIRT_IRQ,
    INT_VIRT_FIQ,
    NumInterruptTypes,
    // Cannot be raised by an external signal
    // (for now) from the IC so we don't instantiate a
    // interrupt entry in the state array
    INT_VIRT_ABT
};
 
class Interrupts : public BaseInterrupts
{
  private:
    bool interrupts[NumInterruptTypes];
    uint64_t intStatus;
 
  public:
    using Params = ArmInterruptsParams;
 
    Interrupts(const Params &p) : BaseInterrupts(p)
    {
        clearAll();
    }
 
 
    void
    post(int int_num, int index) override
    {
        DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
 
        if (int_num < 0 || int_num >= NumInterruptTypes)
            panic("int_num out of bounds\n");
 
        if (index != 0)
            panic("No support for other interrupt indexes\n");
 
        interrupts[int_num] = true;
        intStatus |= 1ULL << int_num;
    }
 
    void
    clear(int int_num, int index) override
    {
        DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
 
        if (int_num < 0 || int_num >= NumInterruptTypes)
            panic("int_num out of bounds\n");
 
        if (index != 0)
            panic("No support for other interrupt indexes\n");
 
        interrupts[int_num] = false;
        intStatus &= ~(1ULL << int_num);
    }
 
    void
    clearAll() override
    {
        DPRINTF(Interrupt, "Interrupts all cleared\n");
        intStatus = 0;
        memset(interrupts, 0, sizeof(interrupts));
    }
 
    enum InterruptMask
    {
        INT_MASK_M, // masked (subject to PSTATE.{A,I,F} mask bit
        INT_MASK_T, // taken regardless of mask
        INT_MASK_P  // pending
    };
 
    bool takeInt(InterruptTypes int_type) const;
    bool takeInt32(InterruptTypes int_type) const;
    bool takeInt64(InterruptTypes int_type) const;
 
    bool takeVirtualInt(InterruptTypes int_type) const;
    bool takeVirtualInt32(InterruptTypes int_type) const;
    bool takeVirtualInt64(InterruptTypes int_type) const;
 
    bool
    checkInterrupts() const override
    {
        HCR  hcr  = tc->readMiscReg(MISCREG_HCR_EL2);
 
        if (!(intStatus || hcr.va || hcr.vi || hcr.vf))
            return false;
 
        return ((interrupts[INT_IRQ] && takeInt(INT_IRQ)) ||
                (interrupts[INT_FIQ] && takeInt(INT_FIQ)) ||
                (interrupts[INT_ABT] && takeInt(INT_ABT)) ||
                ((interrupts[INT_VIRT_IRQ] || hcr.vi) &&
                    takeVirtualInt(INT_VIRT_IRQ)) ||
                ((interrupts[INT_VIRT_FIQ] || hcr.vf) &&
                    takeVirtualInt(INT_VIRT_FIQ)) ||
                (hcr.va && takeVirtualInt(INT_VIRT_ABT)) ||
                (interrupts[INT_RST]) ||
                (interrupts[INT_SEV])
               );
    }
 
    bool
    checkWfiWake(HCR hcr, CPSR cpsr, SCR scr) const
    {
        uint64_t masked_int_status;
        bool     virt_wake;
 
        masked_int_status = intStatus & ~((1 << INT_VIRT_IRQ) |
                                          (1 << INT_VIRT_FIQ));
        virt_wake  = (hcr.vi || interrupts[INT_VIRT_IRQ]) && hcr.imo;
        virt_wake |= (hcr.vf || interrupts[INT_VIRT_FIQ]) && hcr.fmo;
        virt_wake |=  hcr.va                              && hcr.amo;
        virt_wake &= currEL(cpsr) < EL2 && EL2Enabled(tc);
        return masked_int_status || virt_wake;
    }
 
    uint32_t
    getISR(HCR hcr, CPSR cpsr, SCR scr)
    {
        bool use_hcr_mux = currEL(cpsr) < EL2 && EL2Enabled(tc);
        ISR isr = 0;
 
        isr.i = (use_hcr_mux & hcr.imo) ? (interrupts[INT_VIRT_IRQ] || hcr.vi)
                                        :  interrupts[INT_IRQ];
        isr.f = (use_hcr_mux & hcr.fmo) ? (interrupts[INT_VIRT_FIQ] || hcr.vf)
                                        :  interrupts[INT_FIQ];
        isr.a = (use_hcr_mux & hcr.amo) ?  hcr.va : interrupts[INT_ABT];
        return isr;
    }
 
    bool
    checkRaw(InterruptTypes interrupt) const
    {
        if (interrupt >= NumInterruptTypes)
            panic("Interrupt number out of range.\n");
 
        return interrupts[interrupt];
    }
 
    Fault
    getInterrupt() override
    {
        assert(checkInterrupts());
 
        HCR  hcr  = tc->readMiscReg(MISCREG_HCR_EL2);
 
        if (interrupts[INT_IRQ] && takeInt(INT_IRQ))
            return std::make_shared<Interrupt>();
        if ((interrupts[INT_VIRT_IRQ] || hcr.vi) &&
            takeVirtualInt(INT_VIRT_IRQ))
            return std::make_shared<VirtualInterrupt>();
        if (interrupts[INT_FIQ] && takeInt(INT_FIQ))
            return std::make_shared<FastInterrupt>();
        if ((interrupts[INT_VIRT_FIQ] || hcr.vf) &&
            takeVirtualInt(INT_VIRT_FIQ))
            return std::make_shared<VirtualFastInterrupt>();
        if (interrupts[INT_ABT] && takeInt(INT_ABT))
            return std::make_shared<SystemError>();
        if (hcr.va && takeVirtualInt(INT_VIRT_ABT))
            return std::make_shared<VirtualDataAbort>(
                0, TlbEntry::DomainType::NoAccess, false,
                ArmFault::AsynchronousExternalAbort);
        if (interrupts[INT_RST])
            return std::make_shared<Reset>();
        if (interrupts[INT_SEV])
            return std::make_shared<ArmSev>();
 
        panic("intStatus and interrupts not in sync\n");
    }
 
    void updateIntrInfo() override {} // nothing to do
 
    void
    serialize(CheckpointOut &cp) const override
    {
        SERIALIZE_ARRAY(interrupts, NumInterruptTypes);
        SERIALIZE_SCALAR(intStatus);
    }
 
    void
    unserialize(CheckpointIn &cp) override
    {
        UNSERIALIZE_ARRAY(interrupts, NumInterruptTypes);
        UNSERIALIZE_SCALAR(intStatus);
    }
};
 
} // namespace ARM_ISA
} // namespace gem5
 
#endif // __ARCH_ARM_INTERRUPT_HH__