56 bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit;
61 cpsr_mask_bit = cpsr.f;
62 scr_routing_bit = scr.fiq;
63 scr_fwaw_bit = scr.fw;
64 hcr_mask_override_bit = hcr.fmo;
67 cpsr_mask_bit = cpsr.i;
68 scr_routing_bit = scr.irq;
70 hcr_mask_override_bit = hcr.imo;
73 cpsr_mask_bit = cpsr.a;
74 scr_routing_bit = scr.ea;
75 scr_fwaw_bit = scr.aw;
76 hcr_mask_override_bit = hcr.amo;
79 panic(
"Unhandled interrupt type!");
83 hcr_mask_override_bit = 1;
85 if (!highest_el_is_64) {
87 if (!scr_routing_bit) {
89 if (!hcr_mask_override_bit)
100 (hcr_mask_override_bit ||
101 (!scr_fwaw_bit && !hcr_mask_override_bit)))
108 if (!scr_routing_bit) {
112 if (!hcr_mask_override_bit) {
120 else if (is_secure ||
el ==
EL2)
127 if (!hcr_mask_override_bit) {
135 else if (is_secure ||
el ==
EL2)
bool takeInt(InterruptTypes int_type) const
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
virtual RegVal readMiscReg(RegIndex misc_reg)=0
#define panic(...)
This implements a cprintf based panic() function.
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
bool isSecure(ThreadContext *tc)
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....