gem5  v21.1.0.2
interrupts.cc
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37 
38 #include "arch/arm/interrupts.hh"
39 
40 #include "arch/arm/system.hh"
41 
42 namespace gem5
43 {
44 
45 bool
47 {
48  // Table G1-17~19 of ARM V8 ARM
50  bool highest_el_is_64 = ArmSystem::highestELIs64(tc);
51 
52  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
53  SCR scr;
54  HCR hcr;
55  hcr = tc->readMiscReg(MISCREG_HCR);
57  bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit;
58 
59  if (!highest_el_is_64)
60  scr = tc->readMiscReg(MISCREG_SCR);
61  else
63 
64  bool is_secure = isSecure(tc);
65 
66  switch(int_type) {
67  case INT_FIQ:
68  cpsr_mask_bit = cpsr.f;
69  scr_routing_bit = scr.fiq;
70  scr_fwaw_bit = scr.fw;
71  hcr_mask_override_bit = hcr.fmo;
72  break;
73  case INT_IRQ:
74  cpsr_mask_bit = cpsr.i;
75  scr_routing_bit = scr.irq;
76  scr_fwaw_bit = 1;
77  hcr_mask_override_bit = hcr.imo;
78  break;
79  case INT_ABT:
80  cpsr_mask_bit = cpsr.a;
81  scr_routing_bit = scr.ea;
82  scr_fwaw_bit = scr.aw;
83  hcr_mask_override_bit = hcr.amo;
84  break;
85  default:
86  panic("Unhandled interrupt type!");
87  }
88 
89  if (hcr.tge)
90  hcr_mask_override_bit = 1;
91 
92  if (!highest_el_is_64) {
93  // AArch32
94  if (!scr_routing_bit) {
95  // SCR IRQ == 0
96  if (!hcr_mask_override_bit)
97  mask = INT_MASK_M;
98  else {
99  if (!is_secure && (el == EL0 || el == EL1))
100  mask = INT_MASK_T;
101  else
102  mask = INT_MASK_M;
103  }
104  } else {
105  // SCR IRQ == 1
106  if ((!is_secure) &&
107  (hcr_mask_override_bit ||
108  (!scr_fwaw_bit && !hcr_mask_override_bit)))
109  mask = INT_MASK_T;
110  else
111  mask = INT_MASK_M;
112  }
113  } else {
114  // AArch64
115  if (!scr_routing_bit) {
116  // SCR IRQ == 0
117  if (!scr.rw) {
118  // SCR RW == 0
119  if (!hcr_mask_override_bit) {
120  if (el == EL3)
121  mask = INT_MASK_P;
122  else
123  mask = INT_MASK_M;
124  } else {
125  if (el == EL3)
126  mask = INT_MASK_T;
127  else if (is_secure || el == EL2)
128  mask = INT_MASK_M;
129  else
130  mask = INT_MASK_T;
131  }
132  } else {
133  // SCR RW == 1
134  if (!hcr_mask_override_bit) {
135  if (el == EL3 || el == EL2)
136  mask = INT_MASK_P;
137  else
138  mask = INT_MASK_M;
139  } else {
140  if (el == EL3)
141  mask = INT_MASK_P;
142  else if (is_secure || el == EL2)
143  mask = INT_MASK_M;
144  else
145  mask = INT_MASK_T;
146  }
147  }
148  } else {
149  // SCR IRQ == 1
150  if (el == EL3)
151  mask = INT_MASK_M;
152  else
153  mask = INT_MASK_T;
154  }
155  }
156 
157  return ((mask == INT_MASK_T) ||
158  ((mask == INT_MASK_M) && !cpsr_mask_bit)) &&
159  (mask != INT_MASK_P);
160 }
161 
162 } // namespace gem5
gem5::ArmISA::Interrupts::INT_MASK_M
@ INT_MASK_M
Definition: interrupts.hh:125
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:205
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:72
gem5::BaseInterrupts::tc
ThreadContext * tc
Definition: interrupts.hh:44
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:593
sc_dt::int_type
int64 int_type
Definition: sc_nbdefs.hh:240
gem5::ArmISA::currEL
static ExceptionLevel currEL(const ThreadContext *tc)
Definition: utility.hh:119
gem5::ArmISA::INT_FIQ
@ INT_FIQ
Definition: interrupts.hh:63
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
system.hh
gem5::ArmISA::Interrupts::InterruptMask
InterruptMask
Definition: interrupts.hh:123
gem5::ArmISA::INT_ABT
@ INT_ABT
Definition: interrupts.hh:61
interrupts.hh
gem5::ArmISA::Interrupts::INT_MASK_P
@ INT_MASK_P
Definition: interrupts.hh:127
gem5::ArmISA::Interrupts::takeInt
bool takeInt(InterruptTypes int_type) const
Definition: interrupts.cc:46
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::InterruptTypes
InterruptTypes
Definition: interrupts.hh:58
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:72
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: misc.hh:248
gem5::ArmISA::INT_IRQ
@ INT_IRQ
Definition: interrupts.hh:62
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:243
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::Interrupts::INT_MASK_T
@ INT_MASK_T
Definition: interrupts.hh:126
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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