gem5::ArmSystem Class Reference

#include <system.hh>

Inheritance diagram for gem5::ArmSystem:

Public Member Functions
	PARAMS (ArmSystem)
	ArmSystem (const Params &p)
const ArmRelease *	releaseFS () const
bool	has (ArmExtension ext) const
void	setGenericTimer (GenericTimer *generic_timer)
	Sets the pointer to the Generic Timer.
void	setGIC (BaseGic *gic)
	Sets the pointer to the GIC.
void	setPowerController (FVPBasePwrCtrl *pwr_ctrl)
	Sets the pointer to the Power Controller.
GenericTimer *	getGenericTimer () const
	Get a pointer to the system's generic timer model.
BaseGic *	getGIC () const
	Get a pointer to the system's GIC.
FVPBasePwrCtrl *	getPowerController () const
	Get a pointer to the system's power controller.
bool	highestELIs64 () const
	Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
ArmISA::ExceptionLevel	highestEL () const
	Returns the highest implemented exception level.
Addr	resetAddr () const
	Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
void	setResetAddr (Addr addr)
bool	haveLargeAsid64 () const
	Returns true if ASID is 16 bits in AArch64 (ARMv8)
unsigned	sveVL () const
	Returns the SVE vector length at reset, in quadwords.
unsigned	smeVL () const
	Returns the SME vector length at reset, in quadwords.
uint8_t	physAddrRange64 () const
	Returns the supported physical address range in bits if the highest implemented exception level is 64 bits (ARMv8)
uint8_t	physAddrRange () const
	Returns the supported physical address range in bits.
Addr	physAddrMask () const
	Returns the physical address mask.
bool	haveSemihosting () const
	Is Arm Semihosting support enabled?
Public Member Functions inherited from gem5::System
RequestPort &	getSystemPort ()
	Get a reference to the system port that can be used by non-structural simulation objects like processes or threads, or external entities like loaders and debuggers, etc, to access the memory system.
Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Additional function to return the Port of a memory object.
Addr	cacheLineSize () const
	Get the cache line size of the system.
bool	schedule (PCEvent *event) override
bool	remove (PCEvent *event) override
KvmVM *	getKvmVM () const
	Get a pointer to the Kernel Virtual Machine (KVM) SimObject, if present.
void	setKvmVM (KvmVM *const vm)
	Set the pointer to the Kernel Virtual Machine (KVM) SimObject.
memory::PhysicalMemory &	getPhysMem ()
	Get a pointer to access the physical memory of the system.
const memory::PhysicalMemory &	getPhysMem () const
Addr	memSize () const
	Amount of physical memory that exists.
bool	isMemAddr (Addr addr) const
	Check if a physical address is within a range of a memory that is part of the global address map.
void	addDeviceMemory (RequestorID requestorId, memory::AbstractMemory *deviceMemory)
	Add a physical memory range for a device.
bool	isDeviceMemAddr (const PacketPtr &pkt) const
	Similar to isMemAddr but for devices.
memory::AbstractMemory *	getDeviceMemory (const PacketPtr &pkt) const
	Return a pointer to the device memory.
AddrRangeList	getShadowRomRanges () const
ByteOrder	getGuestByteOrder () const
	Get the guest byte order.
ThermalModel *	getThermalModel () const
	The thermal model used for this system (if any).
RequestorID	getRequestorId (const SimObject *requestor, std::string subrequestor={})
	Request an id used to create a request object in the system.
RequestorID	getGlobalRequestorId (const std::string &requestor_name)
	Registers a GLOBAL RequestorID, which is a RequestorID not related to any particular SimObject; since no SimObject is passed, the requestor gets registered by providing the full requestor name.
std::string	getRequestorName (RequestorID requestor_id)
	Get the name of an object for a given request id.
RequestorID	lookupRequestorId (const SimObject *obj) const
	Looks up the RequestorID for a given SimObject returns an invalid RequestorID (invldRequestorId) if not found.
RequestorID	lookupRequestorId (const std::string &name) const
	Looks up the RequestorID for a given object name string returns an invalid RequestorID (invldRequestorId) if not found.
RequestorID	maxRequestors ()
	Get the number of requestors registered in the system.
void	regStats () override
	Callback to set stat parameters.
uint64_t	incWorkItemsBegin ()
	Called by pseudo_inst to track the number of work items started by this system.
uint64_t	incWorkItemsEnd ()
	Called by pseudo_inst to track the number of work items completed by this system.
int	markWorkItem (int index)
	Called by pseudo_inst to mark the cpus actively executing work items.
void	workItemBegin (uint32_t tid, uint32_t workid)
void	workItemEnd (uint32_t tid, uint32_t workid)
bool	trapToGdb (GDBSignal signal, ContextID ctx_id) const
	PARAMS (System)
	System (const Params &p)
	~System ()
const AddrRange &	m5opRange () const
	Range used by memory-mapped m5 pseudo-ops if enabled.
void	registerThreadContext (ThreadContext *tc)
void	replaceThreadContext (ThreadContext *tc, ContextID context_id)
void	serialize (CheckpointOut &cp) const override
	Serialize an object.
void	unserialize (CheckpointIn &cp) override
	Unserialize an object.
bool	isAtomicMode () const
	Is the system in atomic mode?
bool	isTimingMode () const
	Is the system in timing mode?
bool	bypassCaches () const
	Should caches be bypassed?
enums::MemoryMode	getMemoryMode () const
	Get the memory mode of the system.
void	setMemoryMode (enums::MemoryMode mode)
	Change the memory mode of the system.
Public Member Functions inherited from gem5::SimObject
const Params &	params () const
	SimObject (const Params &p)
virtual	~SimObject ()
virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected.
virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint.
virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint.
virtual void	regProbePoints ()
	Register probe points for this object.
virtual void	regProbeListeners ()
	Register probe listeners for this object.
ProbeManager *	getProbeManager ()
	Get the probe manager for this object.
virtual void	startup ()
	startup() is the final initialization call before simulation.
DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining.
virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes.
virtual void	memInvalidate ()
	Invalidate the contents of memory buffers.
Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const
void	schedule (Event &event, Tick when)
void	deschedule (Event &event)
void	reschedule (Event &event, Tick when, bool always=false)
void	schedule (Event *event, Tick when)
void	deschedule (Event *event)
void	reschedule (Event *event, Tick when, bool always=false)
void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers.
void	setCurTick (Tick newVal)
	EventManager (EventManager &em)
	Event manger manages events in the event queue.
	EventManager (EventManager *em)
	EventManager (EventQueue *eq)
Public Member Functions inherited from gem5::Serializable
	Serializable ()
virtual	~Serializable ()
void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section.
void	serializeSection (CheckpointOut &cp, const std::string &name) const
void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object.
void	unserializeSection (CheckpointIn &cp, const std::string &name)
Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object.
virtual void	notifyFork ()
	Notify a child process of a fork.
Public Member Functions inherited from gem5::statistics::Group
	Group (Group *parent, const char *name=nullptr)
	Construct a new statistics group.
virtual	~Group ()
virtual void	resetStats ()
	Callback to reset stats.
virtual void	preDumpStats ()
	Callback before stats are dumped.
void	addStat (statistics::Info *info)
	Register a stat with this group.
const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object.
const std::vector< Info * > &	getStats () const
	Get all stats associated with this object.
void	addStatGroup (const char *name, Group *block)
	Add a stat block as a child of this block.
const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group.
void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block.
	Group ()=delete
	Group (const Group &)=delete
Group &	operator= (const Group &)=delete
Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)
virtual	~Named ()=default
virtual std::string	name () const

Static Public Member Functions
static ArmSystem *	getArmSystem (ThreadContext *tc)
	Returns a valid ArmSystem pointer if using ARM ISA, it fails otherwise.
static bool	has (ArmExtension ext, ThreadContext *tc)
static bool	highestELIs64 (ThreadContext *tc)
static ArmISA::ExceptionLevel	highestEL (ThreadContext *tc)
	Returns the highest implemented exception level for the system of a specific thread context.
static bool	haveEL (ThreadContext *tc, ArmISA::ExceptionLevel el)
	Return true if the system implements a specific exception level.
static Addr	resetAddr (ThreadContext *tc)
	Returns the reset address if the highest implemented exception level for the system of a specific thread context is 64 bits (ARMv8)
static uint8_t	physAddrRange (ThreadContext *tc)
	Returns the supported physical address range in bits for the system of a specific thread context.
static Addr	physAddrMask (ThreadContext *tc)
	Returns the physical address mask for the system of a specific thread context.
static bool	haveLargeAsid64 (ThreadContext *tc)
	Returns true if ASID is 16 bits for the system of a specific thread context while in AArch64 (ARMv8)
static bool	haveSemihosting (ThreadContext *tc)
	Is Arm Semihosting support enabled?
static bool	callSemihosting64 (ThreadContext *tc, bool gem5_ops=false)
	Make a Semihosting call from aarch64.
static bool	callSemihosting32 (ThreadContext *tc, bool gem5_ops=false)
	Make a Semihosting call from aarch32.
static bool	callSemihosting (ThreadContext *tc, bool gem5_ops=false)
	Make a Semihosting call from either aarch64 or aarch32.
static void	callSetStandByWfi (ThreadContext *tc)
	Make a call to notify the power controller of STANDBYWFI assertion.
static void	callClearStandByWfi (ThreadContext *tc)
	Make a call to notify the power controller of STANDBYWFI deassertion.
static bool	callSetWakeRequest (ThreadContext *tc)
	Notify the power controller of WAKEREQUEST assertion.
static void	callClearWakeRequest (ThreadContext *tc)
	Notify the power controller of WAKEREQUEST deassertion.
Static Public Member Functions inherited from gem5::System
static void	printSystems ()
Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system.
static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it.
static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.
static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.
Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section.
static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it.

Public Attributes
bool	multiProc
	true if this a multiprocessor system
Public Attributes inherited from gem5::System
Threads	threads
const bool	multiThread
uint64_t	init_param
PortProxy	physProxy
	Port to physical memory used for writing object files into ram at boot.
Workload *	workload = nullptr
	OS kernel.
std::map< std::pair< uint32_t, uint32_t >, Tick >	lastWorkItemStarted
std::map< uint32_t, statistics::Histogram * >	workItemStats
FutexMap	futexMap
std::set< int >	PIDs
	Process set to track which PIDs have already been allocated.
std::list< BasicSignal >	signalList
std::vector< RedirectPath * >	redirectPaths

Static Public Attributes
static constexpr Addr	PageBytes = ArmISA::PageBytes
static constexpr Addr	PageShift = ArmISA::PageShift
Static Public Attributes inherited from gem5::System
static std::vector< System * >	systemList
static int	numSystemsRunning = 0
static const int	maxPID = 32768

Protected Attributes
GenericTimer *	_genericTimer
	Pointer to the Generic Timer wrapper.
BaseGic *	_gic
FVPBasePwrCtrl *	_pwrCtrl
	Pointer to the Power Controller (if any)
Addr	_resetAddr
	Reset address (ARMv8)
bool	_highestELIs64
	True if the register width of the highest implemented exception level is 64 bits (ARMv8)
const uint8_t	_physAddrRange64
	Supported physical address range in bits if the highest implemented exception level is 64 bits (ARMv8)
const bool	_haveLargeAsid64
	True if ASID is 16 bits in AArch64 (ARMv8)
const unsigned	_sveVL
	SVE vector length at reset, in quadwords.
const unsigned	_smeVL
	SME vector length at reset, in quadwords.
ArmSemihosting *const	semihosting
	True if the Semihosting interface is enabled.
const ArmRelease *	release
	Arm Release object: contains a list of implemented features.
Protected Attributes inherited from gem5::System
KvmVM *	kvmVM = nullptr
memory::PhysicalMemory	physmem
AddrRangeList	ShadowRomRanges
enums::MemoryMode	memoryMode
const Addr	_cacheLineSize
uint64_t	workItemsBegin = 0
uint64_t	workItemsEnd = 0
uint32_t	numWorkIds
std::vector< RequestorInfo >	requestors
	This array is a per-system list of all devices capable of issuing a memory system request and an associated string for each requestor id.
ThermalModel *	thermalModel
const AddrRange	_m5opRange
	Range for memory-mapped m5 pseudo ops.
Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters.
Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue.

Additional Inherited Members
Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params
Protected Member Functions inherited from gem5::System
std::string	stripSystemName (const std::string &requestor_name) const
	Strips off the system name from a requestor name.
RequestorID	_getRequestorId (const SimObject *requestor, const std::string &requestor_name)
	helper function for getRequestorId
std::string	leafRequestorName (const SimObject *requestor, const std::string &subrequestor)
	Helper function for constructing the full (sub)requestor name by providing the root requestor and the relative subrequestor name.
Protected Member Functions inherited from gem5::Drainable
	Drainable ()
virtual	~Drainable ()
virtual void	drainResume ()
	Resume execution after a successful drain.
void	signalDrainDone () const
	Signal that an object is drained.

Detailed Description

Definition at line 92 of file system.hh.

Constructor & Destructor Documentation

ArmSystem()

gem5::ArmSystem::ArmSystem

(

const Params &

p

)

Definition at line 72 of file system.cc.

References _highestELIs64, _physAddrRange64, _resetAddr, gem5::loader::Arm64, fatal, gem5::Workload::getArch(), gem5::Workload::getEntry(), gem5::ArmRelease::has(), gem5::ArmISA::MaxPhysAddrRange, gem5::MipsISA::p, release, warn, warn_if, and gem5::System::workload.

Member Function Documentation

callClearStandByWfi()

void gem5::ArmSystem::callClearStandByWfi ( ThreadContext * tc )

static

Make a call to notify the power controller of STANDBYWFI deassertion.

Definition at line 207 of file system.cc.

References getArmSystem(), and getPowerController().

Referenced by gem5::Gicv3::postInt().

callClearWakeRequest()

void gem5::ArmSystem::callClearWakeRequest ( ThreadContext * tc )

static

Notify the power controller of WAKEREQUEST deassertion.

Definition at line 223 of file system.cc.

References getArmSystem(), and getPowerController().

Referenced by gem5::Gicv3CPUInterface::deassertWakeRequest().

callSemihosting()

bool gem5::ArmSystem::callSemihosting ( ThreadContext * tc, bool gem5_ops = false )

static

Make a Semihosting call from either aarch64 or aarch32.

Definition at line 191 of file system.cc.

References callSemihosting32(), callSemihosting64(), and gem5::ArmISA::inAArch64().

Referenced by gem5::Iris::ThreadContext::semihostingEvent().

callSemihosting32()

bool gem5::ArmSystem::callSemihosting32 ( ThreadContext * tc, bool gem5_ops = false )

static

Make a Semihosting call from aarch32.

Definition at line 185 of file system.cc.

References gem5::ArmSemihosting::call32(), getArmSystem(), and semihosting.

Referenced by callSemihosting().

callSemihosting64()

bool gem5::ArmSystem::callSemihosting64 ( ThreadContext * tc, bool gem5_ops = false )

static

Make a Semihosting call from aarch64.

Definition at line 179 of file system.cc.

References gem5::ArmSemihosting::call64(), getArmSystem(), and semihosting.

Referenced by callSemihosting().

callSetStandByWfi()

void gem5::ArmSystem::callSetStandByWfi ( ThreadContext * tc )

static

Make a call to notify the power controller of STANDBYWFI assertion.

Definition at line 200 of file system.cc.

References getArmSystem(), and getPowerController().

callSetWakeRequest()

bool gem5::ArmSystem::callSetWakeRequest ( ThreadContext * tc )

static

Notify the power controller of WAKEREQUEST assertion.

Returns true if WAKEREQUEST is enabled as a power-on mechanism, and the core is now powered, false otherwise

Definition at line 214 of file system.cc.

References getArmSystem(), and getPowerController().

Referenced by gem5::Gicv3CPUInterface::assertWakeRequest().

getArmSystem()

static ArmSystem * gem5::ArmSystem::getArmSystem ( ThreadContext * tc )

inlinestatic

Returns a valid ArmSystem pointer if using ARM ISA, it fails otherwise.

Definition at line 240 of file system.hh.

References gem5::FullSystem, and gem5::ThreadContext::getSystemPtr().

Referenced by callClearStandByWfi(), callClearWakeRequest(), callSemihosting32(), callSemihosting64(), callSetStandByWfi(), callSetWakeRequest(), has(), haveLargeAsid64(), haveSemihosting(), highestEL(), highestELIs64(), physAddrMask(), physAddrRange(), and resetAddr().

getGenericTimer()

GenericTimer * gem5::ArmSystem::getGenericTimer ( ) const

inline

Get a pointer to the system's generic timer model.

Definition at line 177 of file system.hh.

References _genericTimer.

Referenced by gem5::ArmISA::ISA::getGenericTimer().

getGIC()

BaseGic * gem5::ArmSystem::getGIC ( ) const

inline

Get a pointer to the system's GIC.

Definition at line 180 of file system.hh.

References _gic.

Referenced by gem5::ArmISA::ISA::getGICv3CPUInterface(), and gem5::ArmISA::FsWorkload::initState().

getPowerController()

FVPBasePwrCtrl * gem5::ArmSystem::getPowerController ( ) const

inline

Get a pointer to the system's power controller.

Definition at line 183 of file system.hh.

References _pwrCtrl.

Referenced by callClearStandByWfi(), callClearWakeRequest(), callSetStandByWfi(), and callSetWakeRequest().

has() [1/2]

bool gem5::ArmSystem::has ( ArmExtension ext ) const

inline

Definition at line 158 of file system.hh.

References gem5::ArmISA::ext, gem5::ArmRelease::has(), and release.

Referenced by gem5::Gicv3Distributor::Gicv3Distributor(), has(), haveEL(), gem5::Gicv3CPUInterface::haveEL(), highestEL(), gem5::ArmISA::isHcrxEL2Enabled(), gem5::ArmISA::longDescFormatInUse(), and physAddrRange().

has() [2/2]

bool gem5::ArmSystem::has ( ArmExtension ext, ThreadContext * tc )

static

Definition at line 114 of file system.cc.

References gem5::ArmISA::ext, gem5::FullSystem, getArmSystem(), and has().

haveEL()

bool gem5::ArmSystem::haveEL ( ThreadContext * tc, ArmISA::ExceptionLevel el )

static

Return true if the system implements a specific exception level.

Definition at line 132 of file system.cc.

References gem5::ArmISA::el, gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, has(), and warn.

Referenced by gem5::ArmISA::AbortFault< T >::abortDisable(), gem5::ArmISA::FastInterrupt::abortDisable(), gem5::ArmISA::Interrupt::abortDisable(), gem5::ArmISA::addPAC(), gem5::ArmISA::addPACDA(), gem5::ArmISA::addPACDB(), gem5::ArmISA::addPACGA(), gem5::ArmISA::addPACIA(), gem5::ArmISA::addPACIB(), gem5::ArmISA::authDA(), gem5::ArmISA::authDB(), gem5::ArmISA::authIA(), gem5::ArmISA::authIB(), gem5::ArmISA::badMode(), gem5::ArmISA::badMode32(), gem5::ArmISA::calculateBottomPACBit(), gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), gem5::ArmISA::ArmStaticInst::checkForWFxTrap32(), gem5::ArmISA::ArmStaticInst::checkForWFxTrap64(), gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64(), gem5::ArmISA::ArmStaticInst::checkSmeAccess(), gem5::ArmISA::ArmStaticInst::checkSmeEnabled(), gem5::ArmISA::ArmStaticInst::checkSveEnabled(), gem5::ArmISA::ArmStaticInst::cpsrWriteByInstr(), gem5::ArmISA::debugTargetFrom(), gem5::ArmISA::EL2Enabled(), gem5::ArmISA::ELIsInHost(), gem5::ArmISA::ELStateUsingAArch32K(), gem5::ArmISA::fgtEnabled(), gem5::ArmISA::FastInterrupt::fiqDisable(), gem5::ArmISA::ArmStaticInst::generalExceptionsToAArch64(), gem5::ArmISA::ArmFault::getVector(), gem5::ArmISA::Reset::getVector(), gem5::ArmISA::ArmFault::getVector64(), gem5::ArmISA::haveAArch32EL(), gem5::ArmISA::illegalExceptionReturn(), gem5::ArmISA::HardwareBreakpoint::invoke(), gem5::ArmISA::Reset::invoke(), gem5::ArmISA::ArmFault::invoke32(), gem5::ArmISA::ArmFault::invoke64(), gem5::ArmISA::SelfDebug::isDebugEnabledForEL32(), gem5::ArmISA::SelfDebug::isDebugEnabledForEL64(), gem5::ArmISA::BrkPoint::isEnabled(), gem5::ArmISA::WatchPoint::isEnabled(), gem5::ArmISA::isHcrxEL2Enabled(), gem5::ArmISA::isSecure(), gem5::ArmISA::isSecureAtEL(), gem5::ArmISA::isSecureBelowEL3(), gem5::ArmISA::IsSecureEL2Enabled(), gem5::ArmISA::isUnpriviledgeAccess(), gem5::ArmISA::PrefetchAbort::routeToHyp(), gem5::ArmISA::FastInterrupt::routeToMonitor(), gem5::ArmISA::Interrupt::routeToMonitor(), gem5::ArmISA::SystemError::routeToMonitor(), gem5::ArmISA::MMU::s1PermBits64(), gem5::ArmISA::s1TranslationRegime(), gem5::ArmISA::MMU::s2PermBits64(), gem5::ArmISA::snsBankedIndex(), gem5::ArmISA::trapPACUse(), gem5::ArmISA::ArmStaticInst::trapWFx(), and gem5::ArmISA::ArmFault::update().

haveLargeAsid64() [1/2]

bool gem5::ArmSystem::haveLargeAsid64 ( ) const

inline

Returns true if ASID is 16 bits in AArch64 (ARMv8)

Definition at line 206 of file system.hh.

References _haveLargeAsid64.

Referenced by haveLargeAsid64(), gem5::ArmISA::ISA::ISA(), gem5::ArmISA::MMU::MMU(), gem5::TlbiOp64::tlbiAsid(), gem5::TlbiOp64::tlbiRva(), and gem5::TlbiOp64::tlbiVa().

haveLargeAsid64() [2/2]

bool gem5::ArmSystem::haveLargeAsid64 ( ThreadContext * tc )

static

Returns true if ASID is 16 bits for the system of a specific thread context while in AArch64 (ARMv8)

Definition at line 167 of file system.cc.

References getArmSystem(), and haveLargeAsid64().

haveSemihosting() [1/2]

bool gem5::ArmSystem::haveSemihosting ( ) const

inline

Is Arm Semihosting support enabled?

Definition at line 233 of file system.hh.

References semihosting.

Referenced by haveSemihosting().

haveSemihosting() [2/2]

bool gem5::ArmSystem::haveSemihosting ( ThreadContext * tc )

static

Is Arm Semihosting support enabled?

Definition at line 173 of file system.cc.

References gem5::FullSystem, getArmSystem(), and haveSemihosting().

highestEL() [1/2]

ArmISA::ExceptionLevel gem5::ArmSystem::highestEL ( ) const

inline

Returns the highest implemented exception level.

Definition at line 191 of file system.hh.

References gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, and has().

Referenced by gem5::ArmISA::ELStateUsingAArch32K(), gem5::ArmISA::haveAArch32EL(), gem5::ArmISA::MiscRegLUTEntryInitializer::highest(), highestEL(), and gem5::ArmISA::ISA::ISA().

highestEL() [2/2]

ExceptionLevel gem5::ArmSystem::highestEL ( ThreadContext * tc )

static

Returns the highest implemented exception level for the system of a specific thread context.

Definition at line 126 of file system.cc.

References gem5::ArmISA::EL1, gem5::FullSystem, getArmSystem(), and highestEL().

highestELIs64() [1/2]

bool gem5::ArmSystem::highestELIs64 ( ) const

inline

Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)

Definition at line 187 of file system.hh.

References _highestELIs64.

Referenced by gem5::ArmISA::debugTargetFrom(), gem5::ArmISA::ELStateUsingAArch32K(), gem5::trace::TarmacTracer::getInstRecord(), gem5::ArmISA::haveAArch32EL(), highestELIs64(), gem5::ArmISA::illegalExceptionReturn(), gem5::ArmISA::Reset::invoke(), gem5::ArmISA::ISA::ISA(), gem5::ArmISA::ArmFault::setSyndrome(), gem5::ArmISA::snsBankedIndex(), gem5::ArmISA::Interrupts::takeInt(), and gem5::ArmISA::Interrupts::takeVirtualInt().

highestELIs64() [2/2]

bool gem5::ArmSystem::highestELIs64 ( ThreadContext * tc )

static

Definition at line 120 of file system.cc.

References gem5::FullSystem, getArmSystem(), and highestELIs64().

PARAMS()

gem5::ArmSystem::PARAMS

(

ArmSystem

)

physAddrMask() [1/2]

Addr gem5::ArmSystem::physAddrMask ( ) const

inline

Returns the physical address mask.

Definition at line 230 of file system.hh.

References gem5::ArmISA::mask, and physAddrRange().

Referenced by physAddrMask().

physAddrMask() [2/2]

Addr gem5::ArmSystem::physAddrMask ( ThreadContext * tc )

static

Returns the physical address mask for the system of a specific thread context.

Definition at line 161 of file system.cc.

References getArmSystem(), and physAddrMask().

physAddrRange() [1/2]

uint8_t gem5::ArmSystem::physAddrRange ( ) const

inline

Returns the supported physical address range in bits.

Definition at line 220 of file system.hh.

References _highestELIs64, _physAddrRange64, and has().

Referenced by gem5::ArmISA::ISA::ISA(), gem5::ArmISA::MMU::MMU(), physAddrMask(), physAddrRange(), and gem5::TlbiOp64::tlbiIpaS2().

physAddrRange() [2/2]

uint8_t gem5::ArmSystem::physAddrRange ( ThreadContext * tc )

static

Returns the supported physical address range in bits for the system of a specific thread context.

Definition at line 155 of file system.cc.

References getArmSystem(), and physAddrRange().

physAddrRange64()

uint8_t gem5::ArmSystem::physAddrRange64 ( ) const

inline

Returns the supported physical address range in bits if the highest implemented exception level is 64 bits (ARMv8)

Definition at line 216 of file system.hh.

References _physAddrRange64.

releaseFS()

const ArmRelease * gem5::ArmSystem::releaseFS ( ) const

inline

Definition at line 156 of file system.hh.

References release.

Referenced by gem5::ArmISA::ISA::ISA(), and gem5::ArmISA::MMU::MMU().

resetAddr() [1/2]

Addr gem5::ArmSystem::resetAddr ( ) const

inline

Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)

Definition at line 202 of file system.hh.

References _resetAddr.

Referenced by gem5::ArmISA::Reset::invoke(), and resetAddr().

resetAddr() [2/2]

Addr gem5::ArmSystem::resetAddr ( ThreadContext * tc )

static

Returns the reset address if the highest implemented exception level for the system of a specific thread context is 64 bits (ARMv8)

Definition at line 149 of file system.cc.

References getArmSystem(), and resetAddr().

setGenericTimer()

void gem5::ArmSystem::setGenericTimer ( GenericTimer * generic_timer )

inline

Sets the pointer to the Generic Timer.

Definition at line 162 of file system.hh.

References _genericTimer.

Referenced by gem5::GenericTimer::GenericTimer().

setGIC()

void gem5::ArmSystem::setGIC ( BaseGic * gic )

inline

Sets the pointer to the GIC.

Definition at line 168 of file system.hh.

References _gic, and gem5::ArmISA::gic.

Referenced by gem5::BaseGic::init(), and gem5::Gicv3::unserialize().

setPowerController()

void gem5::ArmSystem::setPowerController ( FVPBasePwrCtrl * pwr_ctrl )

inline

Sets the pointer to the Power Controller.

Definition at line 171 of file system.hh.

References _pwrCtrl.

Referenced by gem5::FVPBasePwrCtrl::FVPBasePwrCtrl().

setResetAddr()

void gem5::ArmSystem::setResetAddr ( Addr addr )

inline

Definition at line 203 of file system.hh.

References _resetAddr, and gem5::X86ISA::addr.

smeVL()

unsigned gem5::ArmSystem::smeVL ( ) const

inline

Returns the SME vector length at reset, in quadwords.

Definition at line 212 of file system.hh.

References _smeVL.

Referenced by gem5::ArmISA::ISA::ISA().

sveVL()

unsigned gem5::ArmSystem::sveVL ( ) const

inline

Returns the SVE vector length at reset, in quadwords.

Definition at line 209 of file system.hh.

References _sveVL.

Referenced by gem5::ArmISA::ISA::ISA().

Member Data Documentation

_genericTimer

GenericTimer* gem5::ArmSystem::_genericTimer

protected

Pointer to the Generic Timer wrapper.

Definition at line 98 of file system.hh.

Referenced by getGenericTimer(), and setGenericTimer().

_gic

BaseGic* gem5::ArmSystem::_gic

protected

Definition at line 99 of file system.hh.

Referenced by getGIC(), and setGIC().

_haveLargeAsid64

const bool gem5::ArmSystem::_haveLargeAsid64

protected

True if ASID is 16 bits in AArch64 (ARMv8)

Definition at line 126 of file system.hh.

Referenced by haveLargeAsid64().

_highestELIs64

bool gem5::ArmSystem::_highestELIs64

protected

True if the register width of the highest implemented exception level is 64 bits (ARMv8)

Definition at line 115 of file system.hh.

Referenced by ArmSystem(), highestELIs64(), and physAddrRange().

_physAddrRange64

const uint8_t gem5::ArmSystem::_physAddrRange64

protected

Supported physical address range in bits if the highest implemented exception level is 64 bits (ARMv8)

Definition at line 121 of file system.hh.

Referenced by ArmSystem(), physAddrRange(), and physAddrRange64().

_pwrCtrl

FVPBasePwrCtrl* gem5::ArmSystem::_pwrCtrl

protected

Pointer to the Power Controller (if any)

Definition at line 104 of file system.hh.

Referenced by getPowerController(), and setPowerController().

_resetAddr

Addr gem5::ArmSystem::_resetAddr

protected

Reset address (ARMv8)

Definition at line 109 of file system.hh.

Referenced by ArmSystem(), resetAddr(), and setResetAddr().

_smeVL

const unsigned gem5::ArmSystem::_smeVL

protected

SME vector length at reset, in quadwords.

Definition at line 132 of file system.hh.

Referenced by smeVL().

_sveVL

const unsigned gem5::ArmSystem::_sveVL

protected

SVE vector length at reset, in quadwords.

Definition at line 129 of file system.hh.

Referenced by sveVL().

multiProc

bool gem5::ArmSystem::multiProc

true if this a multiprocessor system

Definition at line 154 of file system.hh.

Referenced by gem5::ArmISA::getMPIDR().

PageBytes

Addr gem5::ArmSystem::PageBytes = ArmISA::PageBytes

staticconstexpr

Definition at line 146 of file system.hh.

Referenced by gem5::GenericTimerMem::validateFrameRange().

PageShift

Addr gem5::ArmSystem::PageShift = ArmISA::PageShift

staticconstexpr

Definition at line 147 of file system.hh.

release

const ArmRelease* gem5::ArmSystem::release

protected

Arm Release object: contains a list of implemented features.

Definition at line 143 of file system.hh.

Referenced by ArmSystem(), has(), and releaseFS().

semihosting

ArmSemihosting* const gem5::ArmSystem::semihosting

protected

True if the Semihosting interface is enabled.

Definition at line 137 of file system.hh.

Referenced by callSemihosting32(), callSemihosting64(), and haveSemihosting().

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The documentation for this class was generated from the following files:

• arch/arm/system.hh
• arch/arm/system.cc