#include <system.hh>
Public Member Functions | |
| PARAMS (ArmSystem) | |
| ArmSystem (const Params &p) | |
| const ArmRelease * | releaseFS () const |
| bool | has (ArmExtension ext) const |
| void | setGenericTimer (GenericTimer *generic_timer) |
| Sets the pointer to the Generic Timer. More... | |
| void | setGIC (BaseGic *gic) |
| Sets the pointer to the GIC. More... | |
| void | setPowerController (FVPBasePwrCtrl *pwr_ctrl) |
| Sets the pointer to the Power Controller. More... | |
| GenericTimer * | getGenericTimer () const |
| Get a pointer to the system's generic timer model. More... | |
| BaseGic * | getGIC () const |
| Get a pointer to the system's GIC. More... | |
| FVPBasePwrCtrl * | getPowerController () const |
| Get a pointer to the system's power controller. More... | |
| bool | highestELIs64 () const |
| Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8) More... | |
| ArmISA::ExceptionLevel | highestEL () const |
| Returns the highest implemented exception level. More... | |
| Addr | resetAddr () const |
| Returns the reset address if the highest implemented exception level is 64 bits (ARMv8) More... | |
| void | setResetAddr (Addr addr) |
| bool | haveLargeAsid64 () const |
| Returns true if ASID is 16 bits in AArch64 (ARMv8) More... | |
| unsigned | sveVL () const |
| Returns the SVE vector length at reset, in quadwords. More... | |
| uint8_t | physAddrRange64 () const |
| Returns the supported physical address range in bits if the highest implemented exception level is 64 bits (ARMv8) More... | |
| uint8_t | physAddrRange () const |
| Returns the supported physical address range in bits. More... | |
| Addr | physAddrMask () const |
| Returns the physical address mask. More... | |
| bool | haveSemihosting () const |
| Is Arm Semihosting support enabled? More... | |
 Public Member Functions inherited from gem5::System | |
| RequestPort & | getSystemPort () |
| Get a reference to the system port that can be used by non-structural simulation objects like processes or threads, or external entities like loaders and debuggers, etc, to access the memory system. More... | |
| Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) override |
| Additional function to return the Port of a memory object. More... | |
| unsigned int | cacheLineSize () const |
| Get the cache line size of the system. More... | |
| bool | schedule (PCEvent *event) override |
| bool | remove (PCEvent *event) override |
| KvmVM * | getKvmVM () const |
| Get a pointer to the Kernel Virtual Machine (KVM) SimObject, if present. More... | |
| void | setKvmVM (KvmVM *const vm) |
| Set the pointer to the Kernel Virtual Machine (KVM) SimObject. More... | |
| memory::PhysicalMemory & | getPhysMem () |
| Get a pointer to access the physical memory of the system. More... | |
| const memory::PhysicalMemory & | getPhysMem () const |
| Addr | memSize () const |
| Amount of physical memory that exists. More... | |
| bool | isMemAddr (Addr addr) const |
| Check if a physical address is within a range of a memory that is part of the global address map. More... | |
| void | addDeviceMemory (RequestorID requestorId, memory::AbstractMemory *deviceMemory) |
| Add a physical memory range for a device. More... | |
| bool | isDeviceMemAddr (const PacketPtr &pkt) const |
| Similar to isMemAddr but for devices. More... | |
| memory::AbstractMemory * | getDeviceMemory (const PacketPtr &pkt) const |
| Return a pointer to the device memory. More... | |
| AddrRangeList | getShadowRomRanges () const |
| ByteOrder | getGuestByteOrder () const |
| Get the guest byte order. More... | |
| ThermalModel * | getThermalModel () const |
| The thermal model used for this system (if any). More... | |
| RequestorID | getRequestorId (const SimObject *requestor, std::string subrequestor={}) |
| Request an id used to create a request object in the system. More... | |
| RequestorID | getGlobalRequestorId (const std::string &requestor_name) |
| Registers a GLOBAL RequestorID, which is a RequestorID not related to any particular SimObject; since no SimObject is passed, the requestor gets registered by providing the full requestor name. More... | |
| std::string | getRequestorName (RequestorID requestor_id) |
| Get the name of an object for a given request id. More... | |
| RequestorID | lookupRequestorId (const SimObject *obj) const |
| Looks up the RequestorID for a given SimObject returns an invalid RequestorID (invldRequestorId) if not found. More... | |
| RequestorID | lookupRequestorId (const std::string &name) const |
| Looks up the RequestorID for a given object name string returns an invalid RequestorID (invldRequestorId) if not found. More... | |
| RequestorID | maxRequestors () |
| Get the number of requestors registered in the system. More... | |
| void | regStats () override |
| Callback to set stat parameters. More... | |
| uint64_t | incWorkItemsBegin () |
| Called by pseudo_inst to track the number of work items started by this system. More... | |
| uint64_t | incWorkItemsEnd () |
| Called by pseudo_inst to track the number of work items completed by this system. More... | |
| int | markWorkItem (int index) |
| Called by pseudo_inst to mark the cpus actively executing work items. More... | |
| void | workItemBegin (uint32_t tid, uint32_t workid) |
| void | workItemEnd (uint32_t tid, uint32_t workid) |
| bool | trapToGdb (int signal, ContextID ctx_id) const |
| PARAMS (System) | |
| System (const Params &p) | |
| ~System () | |
| const AddrRange & | m5opRange () const |
| Range used by memory-mapped m5 pseudo-ops if enabled. More... | |
| void | registerThreadContext (ThreadContext *tc) |
| void | replaceThreadContext (ThreadContext *tc, ContextID context_id) |
| void | serialize (CheckpointOut &cp) const override |
| Serialize an object. More... | |
| void | unserialize (CheckpointIn &cp) override |
| Unserialize an object. More... | |
| bool | isAtomicMode () const |
| Is the system in atomic mode? More... | |
| bool | isTimingMode () const |
| Is the system in timing mode? More... | |
| bool | bypassCaches () const |
| Should caches be bypassed? More... | |
| enums::MemoryMode | getMemoryMode () const |
| Get the memory mode of the system. More... | |
| void | setMemoryMode (enums::MemoryMode mode) |
| Change the memory mode of the system. More... | |
| Public Member Functions inherited from gem5::SimObject | |
| const Params & | params () const |
| SimObject (const Params &p) | |
| virtual | ~SimObject () |
| virtual void | init () |
| init() is called after all C++ SimObjects have been created and all ports are connected. More... | |
| virtual void | loadState (CheckpointIn &cp) |
| loadState() is called on each SimObject when restoring from a checkpoint. More... | |
| virtual void | initState () |
| initState() is called on each SimObject when not restoring from a checkpoint. More... | |
| virtual void | regProbePoints () |
| Register probe points for this object. More... | |
| virtual void | regProbeListeners () |
| Register probe listeners for this object. More... | |
| ProbeManager * | getProbeManager () |
| Get the probe manager for this object. More... | |
| virtual void | startup () |
| startup() is the final initialization call before simulation. More... | |
| DrainState | drain () override |
| Provide a default implementation of the drain interface for objects that don't need draining. More... | |
| virtual void | memWriteback () |
| Write back dirty buffers to memory using functional writes. More... | |
| virtual void | memInvalidate () |
| Invalidate the contents of memory buffers. More... | |
| Public Member Functions inherited from gem5::EventManager | |
| EventQueue * | eventQueue () const |
| void | schedule (Event &event, Tick when) |
| void | deschedule (Event &event) |
| void | reschedule (Event &event, Tick when, bool always=false) |
| void | schedule (Event *event, Tick when) |
| void | deschedule (Event *event) |
| void | reschedule (Event *event, Tick when, bool always=false) |
| void | wakeupEventQueue (Tick when=(Tick) -1) |
| This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More... | |
| void | setCurTick (Tick newVal) |
| EventManager (EventManager &em) | |
| Event manger manages events in the event queue. More... | |
| EventManager (EventManager *em) | |
| EventManager (EventQueue *eq) | |
| Public Member Functions inherited from gem5::Serializable | |
| Serializable () | |
| virtual | ~Serializable () |
| void | serializeSection (CheckpointOut &cp, const char *name) const |
| Serialize an object into a new section. More... | |
| void | serializeSection (CheckpointOut &cp, const std::string &name) const |
| void | unserializeSection (CheckpointIn &cp, const char *name) |
| Unserialize an a child object. More... | |
| void | unserializeSection (CheckpointIn &cp, const std::string &name) |
| Public Member Functions inherited from gem5::Drainable | |
| DrainState | drainState () const |
| Return the current drain state of an object. More... | |
| virtual void | notifyFork () |
| Notify a child process of a fork. More... | |
| Public Member Functions inherited from gem5::statistics::Group | |
| Group (Group *parent, const char *name=nullptr) | |
| Construct a new statistics group. More... | |
| virtual | ~Group () |
| virtual void | resetStats () |
| Callback to reset stats. More... | |
| virtual void | preDumpStats () |
| Callback before stats are dumped. More... | |
| void | addStat (statistics::Info *info) |
| Register a stat with this group. More... | |
| const std::map< std::string, Group * > & | getStatGroups () const |
| Get all child groups associated with this object. More... | |
| const std::vector< Info * > & | getStats () const |
| Get all stats associated with this object. More... | |
| void | addStatGroup (const char *name, Group *block) |
| Add a stat block as a child of this block. More... | |
| const Info * | resolveStat (std::string name) const |
| Resolve a stat by its name within this group. More... | |
| void | mergeStatGroup (Group *block) |
| Merge the contents (stats & children) of a block to this block. More... | |
| Group ()=delete | |
| Group (const Group &)=delete | |
| Group & | operator= (const Group &)=delete |
| Public Member Functions inherited from gem5::Named | |
| Named (const std::string &name_) | |
| virtual | ~Named ()=default |
| virtual std::string | name () const |
Static Public Member Functions | |
| static ArmSystem * | getArmSystem (ThreadContext *tc) |
| Returns a valid ArmSystem pointer if using ARM ISA, it fails otherwise. More... | |
| static bool | has (ArmExtension ext, ThreadContext *tc) |
| static bool | highestELIs64 (ThreadContext *tc) |
| static ArmISA::ExceptionLevel | highestEL (ThreadContext *tc) |
| Returns the highest implemented exception level for the system of a specific thread context. More... | |
| static bool | haveEL (ThreadContext *tc, ArmISA::ExceptionLevel el) |
| Return true if the system implements a specific exception level. More... | |
| static Addr | resetAddr (ThreadContext *tc) |
| Returns the reset address if the highest implemented exception level for the system of a specific thread context is 64 bits (ARMv8) More... | |
| static uint8_t | physAddrRange (ThreadContext *tc) |
| Returns the supported physical address range in bits for the system of a specific thread context. More... | |
| static Addr | physAddrMask (ThreadContext *tc) |
| Returns the physical address mask for the system of a specific thread context. More... | |
| static bool | haveLargeAsid64 (ThreadContext *tc) |
| Returns true if ASID is 16 bits for the system of a specific thread context while in AArch64 (ARMv8) More... | |
| static bool | haveSemihosting (ThreadContext *tc) |
| Is Arm Semihosting support enabled? More... | |
| static bool | callSemihosting64 (ThreadContext *tc, bool gem5_ops=false) |
| Make a Semihosting call from aarch64. More... | |
| static bool | callSemihosting32 (ThreadContext *tc, bool gem5_ops=false) |
| Make a Semihosting call from aarch32. More... | |
| static bool | callSemihosting (ThreadContext *tc, bool gem5_ops=false) |
| Make a Semihosting call from either aarch64 or aarch32. More... | |
| static void | callSetStandByWfi (ThreadContext *tc) |
| Make a call to notify the power controller of STANDBYWFI assertion. More... | |
| static void | callClearStandByWfi (ThreadContext *tc) |
| Make a call to notify the power controller of STANDBYWFI deassertion. More... | |
| static bool | callSetWakeRequest (ThreadContext *tc) |
| Notify the power controller of WAKEREQUEST assertion. More... | |
| static void | callClearWakeRequest (ThreadContext *tc) |
| Notify the power controller of WAKEREQUEST deassertion. More... | |
| Static Public Member Functions inherited from gem5::System | |
| static void | printSystems () |
| Static Public Member Functions inherited from gem5::SimObject | |
| static void | serializeAll (const std::string &cpt_dir) |
| Create a checkpoint by serializing all SimObjects in the system. More... | |
| static SimObject * | find (const char *name) |
| Find the SimObject with the given name and return a pointer to it. More... | |
| static void | setSimObjectResolver (SimObjectResolver *resolver) |
| There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More... | |
| static SimObjectResolver * | getSimObjectResolver () |
| There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More... | |
| Static Public Member Functions inherited from gem5::Serializable | |
| static const std::string & | currentSection () |
| Gets the fully-qualified name of the active section. More... | |
| static void | generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream) |
| Generate a checkpoint file so that the serialization can be routed to it. More... | |
Public Attributes | |
| bool | multiProc |
| true if this a multiprocessor system More... | |
| Public Attributes inherited from gem5::System | |
| Threads | threads |
| const bool | multiThread |
| uint64_t | init_param |
| PortProxy | physProxy |
| Port to physical memory used for writing object files into ram at boot. More... | |
| Workload * | workload = nullptr |
| OS kernel. More... | |
| std::map< std::pair< uint32_t, uint32_t >, Tick > | lastWorkItemStarted |
| std::map< uint32_t, statistics::Histogram * > | workItemStats |
| FutexMap | futexMap |
| std::set< int > | PIDs |
| Process set to track which PIDs have already been allocated. More... | |
| std::list< BasicSignal > | signalList |
| std::vector< RedirectPath * > | redirectPaths |
Static Public Attributes | |
| static constexpr Addr | PageBytes = ArmISA::PageBytes |
| static constexpr Addr | PageShift = ArmISA::PageShift |
| Static Public Attributes inherited from gem5::System | |
| static std::vector< System * > | systemList |
| static int | numSystemsRunning = 0 |
| static const int | maxPID = 32768 |
Protected Attributes | |
| GenericTimer * | _genericTimer |
| Pointer to the Generic Timer wrapper. More... | |
| BaseGic * | _gic |
| FVPBasePwrCtrl * | _pwrCtrl |
| Pointer to the Power Controller (if any) More... | |
| Addr | _resetAddr |
| Reset address (ARMv8) More... | |
| bool | _highestELIs64 |
| True if the register width of the highest implemented exception level is 64 bits (ARMv8) More... | |
| const uint8_t | _physAddrRange64 |
| Supported physical address range in bits if the highest implemented exception level is 64 bits (ARMv8) More... | |
| const bool | _haveLargeAsid64 |
| True if ASID is 16 bits in AArch64 (ARMv8) More... | |
| const unsigned | _sveVL |
| SVE vector length at reset, in quadwords. More... | |
| ArmSemihosting *const | semihosting |
| True if the Semihosting interface is enabled. More... | |
| const ArmRelease * | release |
| Arm Release object: contains a list of implemented features. More... | |
| Protected Attributes inherited from gem5::System | |
| KvmVM * | kvmVM = nullptr |
| memory::PhysicalMemory | physmem |
| AddrRangeList | ShadowRomRanges |
| enums::MemoryMode | memoryMode |
| const unsigned int | _cacheLineSize |
| uint64_t | workItemsBegin = 0 |
| uint64_t | workItemsEnd = 0 |
| uint32_t | numWorkIds |
| std::vector< RequestorInfo > | requestors |
| This array is a per-system list of all devices capable of issuing a memory system request and an associated string for each requestor id. More... | |
| ThermalModel * | thermalModel |
| const AddrRange | _m5opRange |
| Range for memory-mapped m5 pseudo ops. More... | |
| Protected Attributes inherited from gem5::SimObject | |
| const SimObjectParams & | _params |
| Cached copy of the object parameters. More... | |
| Protected Attributes inherited from gem5::EventManager | |
| EventQueue * | eventq |
| A pointer to this object's event queue. More... | |
Additional Inherited Members | |
| Public Types inherited from gem5::SimObject | |
| typedef SimObjectParams | Params |
| Protected Member Functions inherited from gem5::System | |
| std::string | stripSystemName (const std::string &requestor_name) const |
| Strips off the system name from a requestor name. More... | |
| RequestorID | _getRequestorId (const SimObject *requestor, const std::string &requestor_name) |
| helper function for getRequestorId More... | |
| std::string | leafRequestorName (const SimObject *requestor, const std::string &subrequestor) |
| Helper function for constructing the full (sub)requestor name by providing the root requestor and the relative subrequestor name. More... | |
| Protected Member Functions inherited from gem5::Drainable | |
| Drainable () | |
| virtual | ~Drainable () |
| virtual void | drainResume () |
| Resume execution after a successful drain. More... | |
| void | signalDrainDone () const |
| Signal that an object is drained. More... | |
Detailed Description
Constructor & Destructor Documentation
◆ ArmSystem()
| gem5::ArmSystem::ArmSystem | ( | const Params & | p | ) |
Definition at line 72 of file system.cc.
References _highestELIs64, _physAddrRange64, _resetAddr, gem5::loader::Arm64, fatal, gem5::Workload::getArch(), gem5::Workload::getEntry(), gem5::ArmRelease::has(), gem5::ArmISA::MaxPhysAddrRange, gem5::VegaISA::p, release, warn, warn_if, and gem5::System::workload.
Member Function Documentation
◆ callClearStandByWfi()
|
static |
Make a call to notify the power controller of STANDBYWFI deassertion.
Definition at line 206 of file system.cc.
References getArmSystem(), and getPowerController().
Referenced by gem5::Gicv3::postInt().
◆ callClearWakeRequest()
|
static |
Notify the power controller of WAKEREQUEST deassertion.
Definition at line 222 of file system.cc.
References getArmSystem(), and getPowerController().
Referenced by gem5::Gicv3CPUInterface::deassertWakeRequest().
◆ callSemihosting()
|
static |
Make a Semihosting call from either aarch64 or aarch32.
Definition at line 190 of file system.cc.
References callSemihosting32(), callSemihosting64(), and gem5::ArmISA::inAArch64().
Referenced by gem5::Iris::ThreadContext::semihostingEvent().
◆ callSemihosting32()
|
static |
Make a Semihosting call from aarch32.
Definition at line 184 of file system.cc.
References gem5::ArmSemihosting::call32(), getArmSystem(), and semihosting.
Referenced by callSemihosting().
◆ callSemihosting64()
|
static |
Make a Semihosting call from aarch64.
Definition at line 178 of file system.cc.
References gem5::ArmSemihosting::call64(), getArmSystem(), and semihosting.
Referenced by callSemihosting().
◆ callSetStandByWfi()
|
static |
Make a call to notify the power controller of STANDBYWFI assertion.
Definition at line 199 of file system.cc.
References getArmSystem(), and getPowerController().
◆ callSetWakeRequest()
|
static |
Notify the power controller of WAKEREQUEST assertion.
Returns true if WAKEREQUEST is enabled as a power-on mechanism, and the core is now powered, false otherwise
Definition at line 213 of file system.cc.
References getArmSystem(), and getPowerController().
Referenced by gem5::Gicv3CPUInterface::assertWakeRequest().
◆ getArmSystem()
|
inlinestatic |
Returns a valid ArmSystem pointer if using ARM ISA, it fails otherwise.
Definition at line 234 of file system.hh.
References gem5::FullSystem, and gem5::ThreadContext::getSystemPtr().
Referenced by callClearStandByWfi(), callClearWakeRequest(), callSemihosting32(), callSemihosting64(), callSetStandByWfi(), callSetWakeRequest(), has(), haveLargeAsid64(), haveSemihosting(), highestEL(), highestELIs64(), physAddrMask(), physAddrRange(), and resetAddr().
◆ getGenericTimer()
|
inline |
Get a pointer to the system's generic timer model.
Definition at line 174 of file system.hh.
References _genericTimer.
Referenced by gem5::ArmISA::ISA::getGenericTimer(), and gem5::ArmISA::ISA::readMiscReg().
◆ getGIC()
|
inline |
Get a pointer to the system's GIC.
Definition at line 177 of file system.hh.
References _gic.
Referenced by gem5::ArmISA::ISA::getGICv3CPUInterface(), and gem5::ArmISA::FsWorkload::initState().
◆ getPowerController()
|
inline |
Get a pointer to the system's power controller.
Definition at line 180 of file system.hh.
References _pwrCtrl.
Referenced by callClearStandByWfi(), callClearWakeRequest(), callSetStandByWfi(), and callSetWakeRequest().
◆ has() [1/2]
|
inline |
Definition at line 155 of file system.hh.
References gem5::ArmISA::ext, gem5::ArmRelease::has(), and release.
Referenced by gem5::Gicv3Distributor::Gicv3Distributor(), has(), gem5::Gicv3CPUInterface::haveEL(), haveEL(), highestEL(), gem5::ArmISA::longDescFormatInUse(), and physAddrRange().
◆ has() [2/2]
|
static |
Definition at line 113 of file system.cc.
References gem5::ArmISA::ext, gem5::FullSystem, getArmSystem(), and has().
◆ haveEL()
|
static |
Return true if the system implements a specific exception level.
Definition at line 131 of file system.cc.
References gem5::ArmISA::el, gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, has(), and warn.
Referenced by gem5::ArmISA::AbortFault< T >::abortDisable(), gem5::ArmISA::Interrupt::abortDisable(), gem5::ArmISA::FastInterrupt::abortDisable(), gem5::ArmISA::addPAC(), gem5::ArmISA::addPACDA(), gem5::ArmISA::addPACDB(), gem5::ArmISA::addPACGA(), gem5::ArmISA::addPACIA(), gem5::ArmISA::addPACIB(), gem5::ArmISA::VectorCatch::addressMatching(), gem5::ArmISA::authDA(), gem5::ArmISA::authDB(), gem5::ArmISA::authIA(), gem5::ArmISA::authIB(), gem5::ArmISA::badMode(), gem5::ArmISA::badMode32(), gem5::ArmISA::calculateBottomPACBit(), gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), gem5::ArmISA::ArmStaticInst::checkForWFxTrap32(), gem5::ArmISA::ArmStaticInst::checkForWFxTrap64(), gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64(), gem5::ArmISA::ArmStaticInst::checkSveEnabled(), gem5::ArmISA::ArmStaticInst::cpsrWriteByInstr(), gem5::ArmISA::debugTargetFrom(), gem5::ArmISA::EL2Enabled(), gem5::ArmISA::ELIsInHost(), gem5::ArmISA::ELStateUsingAArch32K(), gem5::ArmISA::VectorCatch::exceptionTrapping(), gem5::ArmISA::FastInterrupt::fiqDisable(), gem5::ArmISA::ArmStaticInst::generalExceptionsToAArch64(), gem5::ArmISA::ArmFault::getVector(), gem5::ArmISA::Reset::getVector(), gem5::ArmISA::ArmFault::getVector64(), gem5::ArmISA::haveAArch32EL(), gem5::ArmISA::illegalExceptionReturn(), gem5::ArmISA::Reset::invoke(), gem5::ArmISA::HardwareBreakpoint::invoke(), gem5::ArmISA::ArmFault::invoke64(), gem5::ArmISA::SelfDebug::isDebugEnabledForEL32(), gem5::ArmISA::SelfDebug::isDebugEnabledForEL64(), gem5::ArmISA::WatchPoint::isEnabled(), gem5::ArmISA::BrkPoint::isEnabled(), gem5::ArmISA::isSecure(), gem5::ArmISA::isSecureBelowEL3(), gem5::ArmISA::IsSecureEL2Enabled(), gem5::ArmISA::isUnpriviledgeAccess(), gem5::ArmISA::readMPIDR(), gem5::ArmISA::PrefetchAbort::routeToHyp(), gem5::ArmISA::Interrupt::routeToMonitor(), gem5::ArmISA::FastInterrupt::routeToMonitor(), gem5::ArmISA::SystemError::routeToMonitor(), gem5::ArmISA::MMU::s1PermBits64(), gem5::ArmISA::s1TranslationRegime(), gem5::ArmISA::MMU::s2PermBits64(), gem5::ArmISA::snsBankedIndex(), gem5::ArmISA::trapPACUse(), gem5::ArmISA::ArmStaticInst::trapWFx(), and gem5::ArmISA::ArmFault::update().
◆ haveLargeAsid64() [1/2]
|
inline |
Returns true if ASID is 16 bits in AArch64 (ARMv8)
Definition at line 203 of file system.hh.
References _haveLargeAsid64.
Referenced by haveLargeAsid64(), gem5::ArmISA::ISA::ISA(), gem5::ArmISA::MMU::MMU(), and gem5::TlbiOp64::performTlbi().
◆ haveLargeAsid64() [2/2]
|
static |
Returns true if ASID is 16 bits for the system of a specific thread context while in AArch64 (ARMv8)
Definition at line 166 of file system.cc.
References getArmSystem(), and haveLargeAsid64().
◆ haveSemihosting() [1/2]
|
inline |
Is Arm Semihosting support enabled?
Definition at line 227 of file system.hh.
References semihosting.
Referenced by haveSemihosting().
◆ haveSemihosting() [2/2]
|
static |
Is Arm Semihosting support enabled?
Definition at line 172 of file system.cc.
References gem5::FullSystem, getArmSystem(), and haveSemihosting().
◆ highestEL() [1/2]
|
inline |
Returns the highest implemented exception level.
Definition at line 188 of file system.hh.
References gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, and has().
Referenced by gem5::ArmISA::ISA::clear64(), gem5::ArmISA::ELStateUsingAArch32K(), gem5::ArmISA::haveAArch32EL(), gem5::ArmISA::MiscRegLUTEntryInitializer::highest(), highestEL(), and gem5::ArmISA::ISA::initializeMiscRegMetadata().
◆ highestEL() [2/2]
|
static |
Returns the highest implemented exception level for the system of a specific thread context.
Definition at line 125 of file system.cc.
References gem5::ArmISA::EL1, gem5::FullSystem, getArmSystem(), and highestEL().
◆ highestELIs64() [1/2]
|
inline |
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition at line 184 of file system.hh.
References _highestELIs64.
Referenced by gem5::ArmISA::ISA::clear(), gem5::ArmISA::debugTargetFrom(), gem5::ArmISA::ELStateUsingAArch32K(), gem5::trace::TarmacTracer::getInstRecord(), gem5::ArmISA::haveAArch32EL(), highestELIs64(), gem5::ArmISA::illegalExceptionReturn(), gem5::ArmISA::Reset::invoke(), gem5::ArmISA::ISA::ISA(), gem5::ArmISA::ArmFault::setSyndrome(), gem5::ArmISA::snsBankedIndex(), and gem5::ArmISA::Interrupts::takeInt().
◆ highestELIs64() [2/2]
|
static |
Definition at line 119 of file system.cc.
References gem5::FullSystem, getArmSystem(), and highestELIs64().
◆ PARAMS()
| gem5::ArmSystem::PARAMS | ( | ArmSystem | ) |
◆ physAddrMask() [1/2]
|
inline |
Returns the physical address mask.
Definition at line 224 of file system.hh.
References gem5::mask(), and physAddrRange().
Referenced by physAddrMask().
◆ physAddrMask() [2/2]
|
static |
Returns the physical address mask for the system of a specific thread context.
Definition at line 160 of file system.cc.
References getArmSystem(), and physAddrMask().
◆ physAddrRange() [1/2]
|
inline |
Returns the supported physical address range in bits.
Definition at line 214 of file system.hh.
References _highestELIs64, _physAddrRange64, and has().
Referenced by gem5::ArmISA::ISA::ISA(), gem5::ArmISA::MMU::MMU(), gem5::TlbiOp64::performTlbi(), physAddrMask(), and physAddrRange().
◆ physAddrRange() [2/2]
|
static |
Returns the supported physical address range in bits for the system of a specific thread context.
Definition at line 154 of file system.cc.
References getArmSystem(), and physAddrRange().
◆ physAddrRange64()
|
inline |
Returns the supported physical address range in bits if the highest implemented exception level is 64 bits (ARMv8)
Definition at line 210 of file system.hh.
References _physAddrRange64.
◆ releaseFS()
|
inline |
Definition at line 153 of file system.hh.
References release.
Referenced by gem5::ArmISA::ISA::ISA(), and gem5::ArmISA::MMU::MMU().
◆ resetAddr() [1/2]
|
inline |
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
Definition at line 199 of file system.hh.
References _resetAddr.
Referenced by gem5::ArmISA::ISA::clear32(), gem5::ArmISA::ISA::clear64(), gem5::ArmISA::Reset::invoke(), and resetAddr().
◆ resetAddr() [2/2]
|
static |
Returns the reset address if the highest implemented exception level for the system of a specific thread context is 64 bits (ARMv8)
Definition at line 148 of file system.cc.
References getArmSystem(), and resetAddr().
◆ setGenericTimer()
|
inline |
Sets the pointer to the Generic Timer.
Definition at line 159 of file system.hh.
References _genericTimer.
Referenced by gem5::GenericTimer::GenericTimer().
◆ setGIC()
|
inline |
Sets the pointer to the GIC.
Definition at line 165 of file system.hh.
References _gic, and gem5::ArmISA::gic.
Referenced by gem5::BaseGic::init(), and gem5::Gicv3::unserialize().
◆ setPowerController()
|
inline |
Sets the pointer to the Power Controller.
Definition at line 168 of file system.hh.
References _pwrCtrl.
Referenced by gem5::FVPBasePwrCtrl::FVPBasePwrCtrl().
◆ setResetAddr()
|
inline |
Definition at line 200 of file system.hh.
References _resetAddr, and gem5::X86ISA::addr.
◆ sveVL()
|
inline |
Returns the SVE vector length at reset, in quadwords.
Definition at line 206 of file system.hh.
References _sveVL.
Referenced by gem5::ArmISA::ISA::ISA().
Member Data Documentation
◆ _genericTimer
|
protected |
Pointer to the Generic Timer wrapper.
Definition at line 98 of file system.hh.
Referenced by getGenericTimer(), and setGenericTimer().
◆ _gic
|
protected |
◆ _haveLargeAsid64
|
protected |
True if ASID is 16 bits in AArch64 (ARMv8)
Definition at line 126 of file system.hh.
Referenced by haveLargeAsid64().
◆ _highestELIs64
|
protected |
True if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition at line 115 of file system.hh.
Referenced by ArmSystem(), highestELIs64(), and physAddrRange().
◆ _physAddrRange64
|
protected |
Supported physical address range in bits if the highest implemented exception level is 64 bits (ARMv8)
Definition at line 121 of file system.hh.
Referenced by ArmSystem(), physAddrRange(), and physAddrRange64().
◆ _pwrCtrl
|
protected |
Pointer to the Power Controller (if any)
Definition at line 104 of file system.hh.
Referenced by getPowerController(), and setPowerController().
◆ _resetAddr
|
protected |
Reset address (ARMv8)
Definition at line 109 of file system.hh.
Referenced by ArmSystem(), resetAddr(), and setResetAddr().
◆ _sveVL
|
protected |
◆ multiProc
| bool gem5::ArmSystem::multiProc |
true if this a multiprocessor system
Definition at line 151 of file system.hh.
Referenced by gem5::ArmISA::getMPIDR().
◆ PageBytes
|
staticconstexpr |
Definition at line 143 of file system.hh.
Referenced by gem5::GenericTimerMem::validateFrameRange().
◆ PageShift
|
staticconstexpr |
◆ release
|
protected |
Arm Release object: contains a list of implemented features.
Definition at line 140 of file system.hh.
Referenced by ArmSystem(), has(), and releaseFS().
◆ semihosting
|
protected |
True if the Semihosting interface is enabled.
Definition at line 134 of file system.hh.
Referenced by callSemihosting32(), callSemihosting64(), and haveSemihosting().
The documentation for this class was generated from the following files: