gem5  v22.0.0.2
gem5::ArmISA::ISA Member List

This is the complete list of members for gem5::ArmISA::ISA, including all inherited members.

_decoderFlavorgem5::ArmISA::ISAprotected
_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
_regClassesgem5::BaseISAprotected
addressTranslation(MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)gem5::ArmISA::ISAprotected
addressTranslation64(MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)gem5::ArmISA::ISAprotected
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
afterStartupgem5::ArmISA::ISAprotected
clear()gem5::ArmISA::ISA
clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)gem5::ArmISA::ISAprotected
clear64(const ArmISAParams &p)gem5::ArmISA::ISAprotected
copyRegsFrom(ThreadContext *src) overridegem5::ArmISA::ISAvirtual
currEL() constgem5::ArmISA::ISA
currentSection()gem5::Serializablestatic
decoderFlavor() constgem5::ArmISA::ISAinline
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
drain() overridegem5::SimObjectinlinevirtual
Drainable()gem5::Drainableprotected
drainResume()gem5::Drainableinlineprotectedvirtual
drainState() constgem5::Drainableinline
dummyDevicegem5::ArmISA::ISAprotected
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
find(const char *name)gem5::SimObjectstatic
flattenCCIndex(int reg) constgem5::ArmISA::ISAinline
flattenFloatIndex(int reg) constgem5::ArmISA::ISAinline
flattenIntIndex(int reg) constgem5::ArmISA::ISAinline
flattenMiscIndex(int reg) constgem5::ArmISA::ISAinline
flattenRegId(const RegId &regId) constgem5::ArmISA::ISAinline
flattenVecElemIndex(int reg) constgem5::ArmISA::ISAinline
flattenVecIndex(int reg) constgem5::ArmISA::ISAinline
flattenVecPredIndex(int reg) constgem5::ArmISA::ISAinline
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
getCurSveVecLenInBits() constgem5::ArmISA::ISA
getCurSveVecLenInBitsAtReset() constgem5::ArmISA::ISAinline
getExecutingAsid() const overridegem5::ArmISA::ISAinlinevirtual
getGenericTimer()gem5::ArmISA::ISAprotected
getGICv3CPUInterface()gem5::ArmISA::ISAprotected
getMiscIndices(int misc_reg) constgem5::ArmISA::ISAinline
getPort(const std::string &if_name, PortID idx=InvalidPortID)gem5::SimObjectvirtual
getProbeManager()gem5::SimObject
getRelease() constgem5::ArmISA::ISAinline
getSelfDebug() constgem5::ArmISA::ISAinline
getSelfDebug(ThreadContext *tc)gem5::ArmISA::ISAinlinestatic
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
gicv3CpuInterfacegem5::ArmISA::ISAprotected
globalClearExclusive() overridegem5::ArmISA::ISAvirtual
globalClearExclusive(ExecContext *xc) overridegem5::ArmISA::ISAvirtual
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
handleLockedRead(const RequestPtr &req) overridegem5::ArmISA::ISAvirtual
handleLockedRead(ExecContext *xc, const RequestPtr &req) overridegem5::ArmISA::ISAvirtual
handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) overridegem5::ArmISA::ISAvirtual
handleLockedSnoop(ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask) overridegem5::ArmISA::ISAvirtual
handleLockedSnoopHit() overridegem5::ArmISA::ISAvirtual
handleLockedSnoopHit(ExecContext *xc) overridegem5::ArmISA::ISAvirtual
handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask) overridegem5::ArmISA::ISAvirtual
handleLockedWrite(ExecContext *xc, const RequestPtr &req, Addr cacheBlockMask) overridegem5::ArmISA::ISAvirtual
haveGICv3CpuIfc() constgem5::ArmISA::ISAinline
haveLargeAsid64gem5::ArmISA::ISAprotected
highestELIs64gem5::ArmISA::ISAprotected
impdefAsNopgem5::ArmISA::ISAprotected
init()gem5::SimObjectvirtual
initializeMiscRegMetadata()gem5::ArmISA::ISAprotected
initID32(const ArmISAParams &p)gem5::ArmISA::ISAprotected
initID64(const ArmISAParams &p)gem5::ArmISA::ISAprotected
InitReg(uint32_t reg)gem5::ArmISA::ISAinlineprotected
initState()gem5::SimObjectvirtual
inSecureState() constgem5::ArmISA::ISA
intRegMapgem5::ArmISA::ISAprotected
inUserMode() const overridegem5::ArmISA::ISAinlinevirtual
ISA(const Params &p)gem5::ArmISA::ISA
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
lookUpMiscReggem5::ArmISA::ISAprotectedstatic
memInvalidate()gem5::SimObjectinlinevirtual
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
miscRegsgem5::ArmISA::ISAprotected
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
newPCState(Addr new_inst_addr=0) const overridegem5::ArmISA::ISAinlinevirtual
notifyFork()gem5::Drainableinlinevirtual
operator=(const Group &)=deletegem5::statistics::Group
Params typedefgem5::SimObject
params() constgem5::SimObjectinline
PARAMS(ArmISA)gem5::ArmISA::ISA
pathgem5::Serializableprivatestatic
physAddrRangegem5::ArmISA::ISAprotected
pmugem5::ArmISA::ISAprotected
preDumpStats()gem5::statistics::Groupvirtual
probeManagergem5::SimObjectprivate
readMiscReg(int misc_reg)gem5::ArmISA::ISA
readMiscRegNoEffect(int misc_reg) constgem5::ArmISA::ISA
redirectRegVHE(int misc_reg)gem5::ArmISA::ISA
regClasses() constgem5::BaseISAinline
RegClasses typedefgem5::BaseISA
regProbeListeners()gem5::SimObjectvirtual
regProbePoints()gem5::SimObjectvirtual
regStats()gem5::statistics::Groupvirtual
releasegem5::ArmISA::ISAprotected
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
selfDebuggem5::ArmISA::ISAprotected
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::ArmISA::ISAvirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setCurTick(Tick newVal)gem5::EventManagerinline
setMiscReg(int misc_reg, RegVal val)gem5::ArmISA::ISA
setMiscRegNoEffect(int misc_reg, RegVal val)gem5::ArmISA::ISA
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
setThreadContext(ThreadContext *_tc)gem5::BaseISAinlinevirtual
setupThreadContext()gem5::ArmISA::ISA
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::BaseISAprotected
gem5::SimObject::SimObject(const Params &p)gem5::SimObject
simObjectListgem5::SimObjectprivatestatic
SimObjectList typedefgem5::SimObjectprivate
snsBankedIndex64(MiscRegIndex reg, bool ns) constgem5::ArmISA::ISAinline
startup() overridegem5::ArmISA::ISAvirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::statistics::Groupprivate
sveVLgem5::ArmISA::ISAprotected
systemgem5::ArmISA::ISAprotected
takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) overridegem5::ArmISA::ISAvirtual
tcgem5::BaseISAprotected
timergem5::ArmISA::ISAprotected
unserialize(CheckpointIn &cp) overridegem5::ArmISA::ISAvirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
updateRegMap(CPSR cpsr)gem5::ArmISA::ISAinlineprotected
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
zeroSveVecRegUpperPart(Elem *v, unsigned eCount)gem5::ArmISA::ISAinlinestatic
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual

Generated on Thu Jul 28 2022 13:33:21 for gem5 by doxygen 1.8.17