gem5  v21.1.0.2
gem5::ArmISA::MMU Member List

This is the complete list of members for gem5::ArmISA::MMU, including all inherited members.

_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
ALL_TLBS enum valuegem5::ArmISA::MMU
BaseMMU(const Params &p)gem5::BaseMMUinlineprotected
currentSection()gem5::Serializablestatic
D_TLBS enum valuegem5::ArmISA::MMU
demapPage(Addr vaddr, uint64_t asn)gem5::BaseMMU
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
dflush(const OP &tlbi_op)gem5::ArmISA::MMUinline
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
dportgem5::ArmISA::MMUprotected
drain() overridegem5::SimObjectinlinevirtual
Drainable()gem5::Drainableprotected
drainResume()gem5::Drainableinlineprotectedvirtual
drainState() constgem5::Drainableinline
dtbgem5::BaseMMU
dtbStage2gem5::ArmISA::MMUprotected
dtbStage2Walkergem5::ArmISA::MMUprotected
dtbWalkergem5::ArmISA::MMUprotected
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
Execute enum valuegem5::BaseMMU
finalizePhysical(const RequestPtr &req, ThreadContext *tc, Mode mode) constgem5::BaseMMU
find(const char *name)gem5::SimObjectstatic
flush(const OP &tlbi_op)gem5::ArmISA::MMUinline
flushAll() overridegem5::ArmISA::MMUinlinevirtual
flushStage1(const OP &tlbi_op)gem5::ArmISA::MMUinline
flushStage2(const OP &tlbi_op)gem5::ArmISA::MMUinline
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
getAttr() constgem5::ArmISA::MMUinline
getDTBPtr() constgem5::ArmISA::MMUinlineprotected
getITBPtr() constgem5::ArmISA::MMUinlineprotected
getPort(const std::string &if_name, PortID idx=InvalidPortID)gem5::SimObjectvirtual
getProbeManager()gem5::SimObject
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
getTlb(BaseMMU::Mode mode, bool stage2) constgem5::ArmISA::MMUprotected
gem5::BaseMMU::getTlb(Mode mode) constgem5::BaseMMUinlineprotected
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
I_TLBS enum valuegem5::ArmISA::MMU
iflush(const OP &tlbi_op)gem5::ArmISA::MMUinline
init() overridegem5::ArmISA::MMUvirtual
initState()gem5::SimObjectvirtual
invalidateMiscReg(TLBType type=ALL_TLBS)gem5::ArmISA::MMU
iportgem5::ArmISA::MMUprotected
itbgem5::BaseMMU
itbStage2gem5::ArmISA::MMUprotected
itbStage2Walkergem5::ArmISA::MMUprotected
itbWalkergem5::ArmISA::MMUprotected
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
memInvalidate()gem5::SimObjectinlinevirtual
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
MMU(const ArmMMUParams &p)gem5::ArmISA::MMU
Mode enum namegem5::BaseMMU
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
notifyFork()gem5::Drainableinlinevirtual
operator=(const Group &)=deletegem5::statistics::Group
params() constgem5::SimObjectinline
Params typedefgem5::BaseMMUprotected
pathgem5::Serializableprivatestatic
preDumpStats()gem5::statistics::Groupvirtual
probeManagergem5::SimObjectprivate
Read enum valuegem5::BaseMMU
regProbeListeners()gem5::SimObjectvirtual
regProbePoints()gem5::SimObjectvirtual
regStats()gem5::statistics::Groupvirtual
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::SimObjectinlinevirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setCurTick(Tick newVal)gem5::EventManagerinline
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::SimObject
SimObjectList typedefgem5::SimObjectprivate
simObjectListgem5::SimObjectprivatestatic
startup()gem5::SimObjectvirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::statistics::Groupprivate
takeOverFrom(BaseMMU *old_mmu)gem5::BaseMMUvirtual
TLBType enum namegem5::ArmISA::MMU
translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, bool stage2)gem5::ArmISA::MMU
translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)gem5::ArmISA::MMU
gem5::BaseMMU::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)gem5::BaseMMU
translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr)gem5::ArmISA::MMU
translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, TLB::ArmTranslationType tran_type)gem5::ArmISA::MMU
translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, TLB::ArmTranslationType tran_type, bool stage2)gem5::ArmISA::MMU
gem5::BaseMMU::translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)gem5::BaseMMU
translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, bool stage2)gem5::ArmISA::MMU
gem5::BaseMMU::translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode)gem5::BaseMMU
unserialize(CheckpointIn &cp) overridegem5::SimObjectinlinevirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
Write enum valuegem5::BaseMMU
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual

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