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gem5 v24.0.0.0
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This is the complete list of members for gem5::ArmISA::MMU, including all inherited members.
| _attr | gem5::ArmISA::MMU | protected |
| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _hasWalkCache | gem5::ArmISA::MMU | protected |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| _release | gem5::ArmISA::MMU | protected |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| AlignByte enum value | gem5::ArmISA::MMU | |
| AlignDoubleWord enum value | gem5::ArmISA::MMU | |
| AlignHalfWord enum value | gem5::ArmISA::MMU | |
| AlignmentMask enum value | gem5::ArmISA::MMU | |
| AlignOctWord enum value | gem5::ArmISA::MMU | |
| AlignQuadWord enum value | gem5::ArmISA::MMU | |
| AlignWord enum value | gem5::ArmISA::MMU | |
| AllowUnaligned enum value | gem5::ArmISA::MMU | |
| ArmFlags enum name | gem5::ArmISA::MMU | |
| ArmTranslationType enum name | gem5::ArmISA::MMU | |
| BaseMMU(const Params &p) | gem5::BaseMMU | inlineprotected |
| checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode, const bool is_priv, CachedState &state) | gem5::ArmISA::MMU | protected |
| checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode, bool stage2) | gem5::ArmISA::MMU | |
| checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode, CachedState &state) | gem5::ArmISA::MMU | |
| checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, bool stage2) | gem5::ArmISA::MMU | |
| checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, CachedState &state) | gem5::ArmISA::MMU | |
| checkWalkCache() const | gem5::ArmISA::MMU | protected |
| currentSection() | gem5::Serializable | static |
| data | gem5::BaseMMU | protected |
| demapPage(Addr vaddr, uint64_t asn) | gem5::BaseMMU | |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| dflush(const OP &tlbi_op) | gem5::ArmISA::MMU | inline |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| drain() override | gem5::SimObject | inlinevirtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() override | gem5::ArmISA::MMU | virtual |
| drainState() const | gem5::Drainable | inline |
| dtb | gem5::BaseMMU | |
| dtbStage2 | gem5::ArmISA::MMU | protected |
| dtbStage2Walker | gem5::ArmISA::MMU | protected |
| dtbWalker | gem5::ArmISA::MMU | protected |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| Execute enum value | gem5::BaseMMU | |
| faultPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode, const bool is_priv, CachedState &state) | gem5::ArmISA::MMU | protected |
| finalizePhysical(const RequestPtr &req, ThreadContext *tc, Mode mode) const override | gem5::ArmISA::MMU | virtual |
| find(const char *name) | gem5::SimObject | static |
| flush(const OP &tlbi_op) | gem5::ArmISA::MMU | inline |
| flushAll() override | gem5::ArmISA::MMU | inlinevirtual |
| flushStage1(const OP &tlbi_op) | gem5::ArmISA::MMU | inline |
| flushStage2(const OP &tlbi_op) | gem5::ArmISA::MMU | inline |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getAttr() const | gem5::ArmISA::MMU | inline |
| getDTBPtr() const | gem5::ArmISA::MMU | inlineprotected |
| getITBPtr() const | gem5::ArmISA::MMU | inlineprotected |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) | gem5::SimObject | virtual |
| getProbeManager() | gem5::SimObject | |
| getResultTe(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, TlbEntry *mergeTe, CachedState &state) | gem5::ArmISA::MMU | |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| getTableWalker(BaseMMU::Mode mode, bool stage2) const | gem5::ArmISA::MMU | protected |
| getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, ArmTranslationType tran_type, bool stage2) | gem5::ArmISA::MMU | |
| getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, ArmTranslationType tran_type, CachedState &state) | gem5::ArmISA::MMU | |
| getTlb(BaseMMU::Mode mode, bool stage2) const | gem5::ArmISA::MMU | protected |
| gem5::BaseMMU::getTlb(Mode mode) const | gem5::BaseMMU | inlineprotected |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| hasUnprivRegime(TranslationRegime regime) | gem5::ArmISA::MMU | static |
| hasWalkCache() const | gem5::ArmISA::MMU | inline |
| haveLargeAsid64 | gem5::ArmISA::MMU | protected |
| HypMode enum value | gem5::ArmISA::MMU | |
| iflush(const OP &tlbi_op) | gem5::ArmISA::MMU | inline |
| init() override | gem5::ArmISA::MMU | virtual |
| initState() | gem5::SimObject | virtual |
| instruction | gem5::BaseMMU | protected |
| invalidateMiscReg() | gem5::ArmISA::MMU | |
| isCompleteTranslation(TlbEntry *te) const | gem5::ArmISA::MMU | protected |
| itb | gem5::BaseMMU | |
| itbStage2 | gem5::ArmISA::MMU | protected |
| itbStage2Walker | gem5::ArmISA::MMU | protected |
| itbWalker | gem5::ArmISA::MMU | protected |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| lookup(Addr vpn, uint16_t asn, vmid_t vmid, bool secure, bool functional, bool ignore_asn, TranslationRegime target_regime, bool stage2, BaseMMU::Mode mode) | gem5::ArmISA::MMU | |
| LookupLevel typedef | gem5::ArmISA::MMU | protected |
| m5opRange | gem5::ArmISA::MMU | protected |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| miscRegContext | gem5::ArmISA::MMU | protected |
| MMU(const ArmMMUParams &p) | gem5::ArmISA::MMU | |
| Mode enum name | gem5::BaseMMU | |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| NormalTran enum value | gem5::ArmISA::MMU | |
| notifyFork() | gem5::Drainable | inlinevirtual |
| operator=(const Group &)=delete | gem5::statistics::Group | |
| Params typedef | gem5::BaseMMU | protected |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| physAddrRange | gem5::ArmISA::MMU | protected |
| preDumpStats() | gem5::statistics::Group | virtual |
| probeManager | gem5::SimObject | private |
| purifyTaggedAddr(Addr vaddr_tainted, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool is_inst, CachedState &state) | gem5::ArmISA::MMU | protected |
| Read enum value | gem5::BaseMMU | |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() | gem5::SimObject | virtual |
| regStats() | gem5::statistics::Group | virtual |
| release() const | gem5::ArmISA::MMU | inline |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| S12E0Tran enum value | gem5::ArmISA::MMU | |
| S12E1Tran enum value | gem5::ArmISA::MMU | |
| S1CTran enum value | gem5::ArmISA::MMU | |
| S1E0Tran enum value | gem5::ArmISA::MMU | |
| S1E1Tran enum value | gem5::ArmISA::MMU | |
| S1E2Tran enum value | gem5::ArmISA::MMU | |
| S1E3Tran enum value | gem5::ArmISA::MMU | |
| s1PermBits64(TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, CachedState &state, bool r, bool w, bool x) | gem5::ArmISA::MMU | protected |
| S1S2NsTran enum value | gem5::ArmISA::MMU | |
| s1State | gem5::ArmISA::MMU | |
| s2PermBits64(TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, CachedState &state, bool r, bool w, bool x) | gem5::ArmISA::MMU | protected |
| s2State | gem5::ArmISA::MMU | |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::SimObject | inlinevirtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setAttr(uint64_t attr) | gem5::ArmISA::MMU | inline |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| setTestInterface(SimObject *ti) | gem5::ArmISA::MMU | |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| SimObjectList typedef | gem5::SimObject | private |
| simObjectList | gem5::SimObject | privatestatic |
| startup() | gem5::SimObject | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::ArmISA::MMU | protected |
| takeOverFrom(BaseMMU *old_mmu) override | gem5::ArmISA::MMU | virtual |
| test | gem5::ArmISA::MMU | |
| testAndFinalize(const RequestPtr &req, ThreadContext *tc, Mode mode, TlbEntry *te, CachedState &state) const | gem5::ArmISA::MMU | protected |
| testTranslation(const RequestPtr &req, Mode mode, TlbEntry::DomainType domain, CachedState &state) const | gem5::ArmISA::MMU | |
| translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) override | gem5::ArmISA::MMU | inlinevirtual |
| translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tran_type, bool stage2) | gem5::ArmISA::MMU | |
| translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode, ArmTranslationType tran_type) | gem5::ArmISA::MMU | |
| translateComplete(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tran_type, bool call_from_s2) | gem5::ArmISA::MMU | |
| translateComplete(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tran_type, bool call_from_s2, CachedState &state) | gem5::ArmISA::MMU | |
| translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, ArmTranslationType tran_type, bool functional, CachedState &state) | gem5::ArmISA::MMU | |
| translateFunctional(Addr start, Addr size, ThreadContext *tc, Mode mode, Request::Flags flags) override | gem5::ArmISA::MMU | inlinevirtual |
| translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr) | gem5::ArmISA::MMU | |
| translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override | gem5::ArmISA::MMU | virtual |
| translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tran_type) | gem5::ArmISA::MMU | |
| translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tran_type, bool stage2) | gem5::ArmISA::MMU | |
| translateMmuOff(ThreadContext *tc, const RequestPtr &req, Mode mode, ArmTranslationType tran_type, Addr vaddr, bool long_desc_format, CachedState &state) | gem5::ArmISA::MMU | |
| translateMmuOn(ThreadContext *tc, const RequestPtr &req, Mode mode, Translation *translation, bool &delay, bool timing, bool functional, Addr vaddr, ArmFault::TranMethod tranMethod, CachedState &state) | gem5::ArmISA::MMU | |
| translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, CachedState &state) | gem5::ArmISA::MMU | |
| translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) override | gem5::ArmISA::MMU | inlinevirtual |
| translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, bool stage2) | gem5::ArmISA::MMU | |
| translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tran_type, bool stage2) | gem5::ArmISA::MMU | |
| tranTypeEL(CPSR cpsr, SCR scr, ArmTranslationType type) | gem5::ArmISA::MMU | static |
| unified | gem5::BaseMMU | protected |
| unserialize(CheckpointIn &cp) override | gem5::SimObject | inlinevirtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| updateMiscReg(ThreadContext *tc, ArmTranslationType tran_type, bool stage2) | gem5::ArmISA::MMU | protected |
| UserMode enum value | gem5::ArmISA::MMU | |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| Write enum value | gem5::BaseMMU | |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |