gem5  v21.1.0.2
gem5::ArmISA::PMU Member List

This is the complete list of members for gem5::ArmISA::PMU, including all inherited members.

_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
addEventProbe(unsigned int id, SimObject *obj, const char *name)gem5::ArmISA::PMU
addSoftwareIncrementEvent(unsigned int id)gem5::ArmISA::PMU
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
BaseISADevice()gem5::ArmISA::BaseISADevice
BitUnion32(PMCR_t) Bitfield< 0 > egem5::ArmISA::PMUprotected
cgem5::ArmISA::PMUprotected
clearInterrupt()gem5::ArmISA::PMUprotected
clock_remaindergem5::ArmISA::PMUprotected
countersgem5::ArmISA::PMUprotected
currentSection()gem5::Serializablestatic
cycleCountergem5::ArmISA::PMUprotected
cycleCounterEventIdgem5::ArmISA::PMUprotected
dgem5::ArmISA::PMUprotected
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
dpgem5::ArmISA::PMUprotected
drain() overridegem5::SimObjectinlinevirtual
Drainable()gem5::Drainableprotected
drainResume() overridegem5::ArmISA::PMUvirtual
drainState() constgem5::Drainableinline
EndBitUnion(PMCR_t) BitUnion32(PMSELR_t) Bitfield< 4gem5::ArmISA::PMUprotected
EndBitUnion(PMSELR_t) BitUnion32(PMEVTYPER_t) Bitfield< 15gem5::ArmISA::PMUprotected
EndBitUnion(PMEVTYPER_t) typedef unsigned int CounterIdgem5::ArmISA::PMUprotected
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventMapgem5::ArmISA::PMUprotected
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
EventTypeId typedefgem5::ArmISA::PMUprotected
evtCountgem5::ArmISA::PMUprotected
find(const char *name)gem5::SimObjectstatic
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
getCounter(CounterId id)gem5::ArmISA::PMUinlineprotected
getCounter(CounterId id) constgem5::ArmISA::PMUinlineprotected
getCounterTypeRegister(CounterId id) constgem5::ArmISA::PMUprotected
getCounterValue(CounterId id) constgem5::ArmISA::PMUinlineprotected
getEvent(uint64_t eventId)gem5::ArmISA::PMUprotected
getPort(const std::string &if_name, PortID idx=InvalidPortID)gem5::SimObjectvirtual
getProbeManager()gem5::SimObject
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
idcodegem5::ArmISA::PMUprotected
impgem5::ArmISA::PMUprotected
init()gem5::SimObjectvirtual
initState()gem5::SimObjectvirtual
interruptgem5::ArmISA::PMUprotected
isagem5::ArmISA::BaseISADeviceprotected
isFiltered(const CounterState &ctr) constgem5::ArmISA::PMUprotected
isValidCounter(CounterId id) constgem5::ArmISA::PMUinlineprotected
lcgem5::ArmISA::PMUprotected
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
mgem5::ArmISA::PMUprotected
maximumCounterCountgem5::ArmISA::PMUprotected
memInvalidate()gem5::SimObjectinlinevirtual
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
ngem5::ArmISA::PMUprotected
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
notifyFork()gem5::Drainableinlinevirtual
nshgem5::ArmISA::PMUprotected
nskgem5::ArmISA::PMUprotected
nsugem5::ArmISA::PMUprotected
operator=(const Group &)=deletegem5::statistics::Group
pgem5::ArmISA::PMUprotected
pgem5::ArmISA::PMUprotected
Params typedefgem5::SimObject
params() constgem5::SimObjectinline
pathgem5::Serializableprivatestatic
PMCCNTRgem5::ArmISA::PMUprotectedstatic
PMU(const ArmPMUParams &p)gem5::ArmISA::PMU
preDumpStats()gem5::statistics::Groupvirtual
probeManagergem5::SimObjectprivate
raiseInterrupt()gem5::ArmISA::PMUprotected
readMiscReg(int misc_reg) overridegem5::ArmISA::PMUvirtual
readMiscRegInt(int misc_reg)gem5::ArmISA::PMUprotected
reg_pmceid0gem5::ArmISA::PMUprotected
reg_pmceid1gem5::ArmISA::PMUprotected
reg_pmcntengem5::ArmISA::PMUprotected
reg_pmcrgem5::ArmISA::PMUprotected
reg_pmcr_confgem5::ArmISA::PMUprotected
reg_pmcr_wr_maskgem5::ArmISA::PMUprotectedstatic
reg_pmintengem5::ArmISA::PMUprotected
reg_pmovsrgem5::ArmISA::PMUprotected
reg_pmselrgem5::ArmISA::PMUprotected
registerEvent(uint32_t id)gem5::ArmISA::PMU
regProbeListeners() overridegem5::ArmISA::PMUvirtual
regProbePoints()gem5::SimObjectvirtual
regStats()gem5::statistics::Groupvirtual
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetEventCounts()gem5::ArmISA::PMUprotected
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
selgem5::ArmISA::PMUprotected
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::ArmISA::PMUvirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setControlReg(PMCR_t val)gem5::ArmISA::PMUprotected
setCounterTypeRegister(CounterId id, PMEVTYPER_t type)gem5::ArmISA::PMUprotected
setCounterValue(CounterId id, uint64_t val)gem5::ArmISA::PMUprotected
setCurTick(Tick newVal)gem5::EventManagerinline
setISA(ISA *isa)gem5::ArmISA::BaseISADevicevirtual
setMiscReg(int misc_reg, RegVal val) overridegem5::ArmISA::PMUvirtual
setOverflowStatus(RegVal new_val)gem5::ArmISA::PMUprotected
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
setThreadContext(ThreadContext *tc) overridegem5::ArmISA::PMUvirtual
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::SimObject
simObjectListgem5::SimObjectprivatestatic
SimObjectList typedefgem5::SimObjectprivate
startup()gem5::SimObjectvirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::statistics::Groupprivate
swIncrementEventgem5::ArmISA::PMUprotected
ugem5::ArmISA::PMUprotected
unserialize(CheckpointIn &cp) overridegem5::ArmISA::PMUvirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
updateAllCounters()gem5::ArmISA::PMUprotected
updateCounter(CounterState &ctr)gem5::ArmISA::PMUprotected
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
xgem5::ArmISA::PMUprotected
~BaseISADevice()gem5::ArmISA::BaseISADeviceinlinevirtual
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~PMU()gem5::ArmISA::PMU
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual

Generated on Tue Sep 21 2021 12:28:37 for gem5 by doxygen 1.8.17