| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| addEventProbe(unsigned int id, SimObject *obj, const char *name) | gem5::ArmISA::PMU | |
| addSoftwareIncrementEvent(unsigned int id) | gem5::ArmISA::PMU | |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| BaseISADevice() | gem5::ArmISA::BaseISADevice | |
| BitUnion32(PMCR_t) Bitfield< 0 > e | gem5::ArmISA::PMU | protected |
| c | gem5::ArmISA::PMU | protected |
| clearInterrupt() | gem5::ArmISA::PMU | protected |
| clock_remainder | gem5::ArmISA::PMU | protected |
| counters | gem5::ArmISA::PMU | protected |
| currentSection() | gem5::Serializable | static |
| cycleCounter | gem5::ArmISA::PMU | protected |
| cycleCounterEventId | gem5::ArmISA::PMU | protected |
| d | gem5::ArmISA::PMU | protected |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| dp | gem5::ArmISA::PMU | protected |
| drain() override | gem5::SimObject | inlinevirtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() override | gem5::ArmISA::PMU | virtual |
| drainState() const | gem5::Drainable | inline |
| EndBitUnion(PMCR_t) BitUnion32(PMSELR_t) Bitfield< 4 | gem5::ArmISA::PMU | protected |
| EndBitUnion(PMSELR_t) BitUnion32(PMEVTYPER_t) Bitfield< 15 | gem5::ArmISA::PMU | protected |
| EndBitUnion(PMEVTYPER_t) typedef unsigned int CounterId | gem5::ArmISA::PMU | protected |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventMap | gem5::ArmISA::PMU | protected |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| EventTypeId typedef | gem5::ArmISA::PMU | protected |
| evtCount | gem5::ArmISA::PMU | protected |
| exitOnPMUControl | gem5::ArmISA::PMU | protected |
| exitOnPMUInterrupt | gem5::ArmISA::PMU | protected |
| find(const char *name) | gem5::SimObject | static |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getCounter(CounterId id) | gem5::ArmISA::PMU | inlineprotected |
| getCounter(CounterId id) const | gem5::ArmISA::PMU | inlineprotected |
| getCounterTypeRegister(CounterId id) const | gem5::ArmISA::PMU | protected |
| getCounterValue(CounterId id) const | gem5::ArmISA::PMU | inlineprotected |
| getEvent(uint64_t eventId) | gem5::ArmISA::PMU | protected |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) | gem5::SimObject | virtual |
| getProbeManager() | gem5::SimObject | |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| idcode | gem5::ArmISA::PMU | protected |
| imp | gem5::ArmISA::PMU | protected |
| init() | gem5::SimObject | virtual |
| initState() | gem5::SimObject | virtual |
| interrupt | gem5::ArmISA::PMU | protected |
| isa | gem5::ArmISA::BaseISADevice | protected |
| isFiltered(const CounterState &ctr) const | gem5::ArmISA::PMU | protected |
| isValidCounter(CounterId id) const | gem5::ArmISA::PMU | inlineprotected |
| lc | gem5::ArmISA::PMU | protected |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| m | gem5::ArmISA::PMU | protected |
| maximumCounterCount | gem5::ArmISA::PMU | protected |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| n | gem5::ArmISA::PMU | protected |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| notifyFork() | gem5::Drainable | inlinevirtual |
| nsh | gem5::ArmISA::PMU | protected |
| nsk | gem5::ArmISA::PMU | protected |
| nsu | gem5::ArmISA::PMU | protected |
| operator=(const Group &)=delete | gem5::statistics::Group | |
| p | gem5::ArmISA::PMU | protected |
| p | gem5::ArmISA::PMU | protected |
| Params typedef | gem5::SimObject | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| PMCCNTR | gem5::ArmISA::PMU | protectedstatic |
| PMU(const ArmPMUParams &p) | gem5::ArmISA::PMU | |
| preDumpStats() | gem5::statistics::Group | virtual |
| probeManager | gem5::SimObject | private |
| raiseInterrupt() | gem5::ArmISA::PMU | protected |
| readMiscReg(int misc_reg) override | gem5::ArmISA::PMU | virtual |
| readMiscRegInt(int misc_reg) | gem5::ArmISA::PMU | protected |
| reg_pmceid0 | gem5::ArmISA::PMU | protected |
| reg_pmceid1 | gem5::ArmISA::PMU | protected |
| reg_pmcnten | gem5::ArmISA::PMU | protected |
| reg_pmcr | gem5::ArmISA::PMU | protected |
| reg_pmcr_conf | gem5::ArmISA::PMU | protected |
| reg_pmcr_wr_mask | gem5::ArmISA::PMU | protectedstatic |
| reg_pminten | gem5::ArmISA::PMU | protected |
| reg_pmovsr | gem5::ArmISA::PMU | protected |
| reg_pmselr | gem5::ArmISA::PMU | protected |
| registerEvent(uint32_t id) | gem5::ArmISA::PMU | |
| regProbeListeners() override | gem5::ArmISA::PMU | virtual |
| regProbePoints() | gem5::SimObject | virtual |
| regStats() | gem5::statistics::Group | virtual |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetEventCounts() | gem5::ArmISA::PMU | protected |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| sel | gem5::ArmISA::PMU | protected |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::ArmISA::PMU | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setControlReg(PMCR_t val) | gem5::ArmISA::PMU | protected |
| setCounterTypeRegister(CounterId id, PMEVTYPER_t type) | gem5::ArmISA::PMU | protected |
| setCounterValue(CounterId id, uint64_t val) | gem5::ArmISA::PMU | protected |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setISA(ISA *isa) | gem5::ArmISA::BaseISADevice | virtual |
| setMiscReg(int misc_reg, RegVal val) override | gem5::ArmISA::PMU | virtual |
| setOverflowStatus(RegVal new_val) | gem5::ArmISA::PMU | protected |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| setThreadContext(ThreadContext *tc) override | gem5::ArmISA::PMU | virtual |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| SimObjectList typedef | gem5::SimObject | private |
| simObjectList | gem5::SimObject | privatestatic |
| startup() | gem5::SimObject | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::statistics::Group | private |
| swIncrementEvent | gem5::ArmISA::PMU | protected |
| u | gem5::ArmISA::PMU | protected |
| unserialize(CheckpointIn &cp) override | gem5::ArmISA::PMU | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| updateAllCounters() | gem5::ArmISA::PMU | protected |
| updateCounter(CounterState &ctr) | gem5::ArmISA::PMU | protected |
| use64bitCounters | gem5::ArmISA::PMU | protected |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| x | gem5::ArmISA::PMU | protected |
| ~BaseISADevice() | gem5::ArmISA::BaseISADevice | inlinevirtual |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~PMU() | gem5::ArmISA::PMU | |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |