gem5  v21.1.0.2
gem5::ArmISA::TLB Member List

This is the complete list of members for gem5::ArmISA::TLB, including all inherited members.

_attrgem5::ArmISA::TLBprotected
_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_flushMva(Addr mva, uint64_t asn, bool secure_lookup, bool ignore_asn, ExceptionLevel target_el, bool in_host)gem5::ArmISA::TLBprivate
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
aarch64gem5::ArmISA::TLBprotected
aarch64ELgem5::ArmISA::TLBprotected
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
AlignByte enum valuegem5::ArmISA::TLB
AlignDoubleWord enum valuegem5::ArmISA::TLB
AlignHalfWord enum valuegem5::ArmISA::TLB
AlignmentMask enum valuegem5::ArmISA::TLB
AlignOctWord enum valuegem5::ArmISA::TLB
AlignQuadWord enum valuegem5::ArmISA::TLB
AlignWord enum valuegem5::ArmISA::TLB
AllowUnaligned enum valuegem5::ArmISA::TLB
ArmFlags enum namegem5::ArmISA::TLB
ArmTranslationType enum namegem5::ArmISA::TLB
asidgem5::ArmISA::TLBprotected
BaseTLB(const Params &p)gem5::BaseTLBinlineprotected
checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, BaseMMU::Mode mode, const bool is_priv)gem5::ArmISA::TLB
checkPermissions(TlbEntry *te, const RequestPtr &req, BaseMMU::Mode mode)gem5::ArmISA::TLB
checkPermissions64(TlbEntry *te, const RequestPtr &req, BaseMMU::Mode mode, ThreadContext *tc)gem5::ArmISA::TLB
cpsrgem5::ArmISA::TLBprotected
currentSection()gem5::Serializablestatic
curTranTypegem5::ArmISA::TLBprotected
dacrgem5::ArmISA::TLBprotected
demapPage(Addr vaddr, uint64_t asn) overridegem5::ArmISA::TLBinlinevirtual
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
directToStage2gem5::ArmISA::TLBprotected
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
drain() overridegem5::SimObjectinlinevirtual
Drainable()gem5::Drainableprotected
drainResume() overridegem5::ArmISA::TLBvirtual
drainState() constgem5::Drainableinline
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const overridegem5::ArmISA::TLBvirtual
find(const char *name)gem5::SimObjectstatic
flush(const TLBIALL &tlbi_op)gem5::ArmISA::TLB
flush(const TLBIALLEL &tlbi_op)gem5::ArmISA::TLB
flush(const TLBIVMALL &tlbi_op)gem5::ArmISA::TLB
flush(const TLBIALLN &tlbi_op)gem5::ArmISA::TLB
flush(const TLBIMVA &tlbi_op)gem5::ArmISA::TLB
flush(const TLBIASID &tlbi_op)gem5::ArmISA::TLB
flush(const TLBIMVAA &tlbi_op)gem5::ArmISA::TLB
flushAll() overridegem5::ArmISA::TLBvirtual
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
getAttr() constgem5::ArmISA::TLBinline
getPort(const std::string &if_name, PortID idx=InvalidPortID)gem5::SimObjectvirtual
getProbeManager()gem5::SimObject
getResultTe(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool timing, bool functional, TlbEntry *mergeTe)gem5::ArmISA::TLB
getSimObjectResolver()gem5::SimObjectstatic
getsize() constgem5::ArmISA::TLBinline
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
getTableWalker()gem5::ArmISA::TLBinline
getTableWalkerPort() overridegem5::ArmISA::TLBvirtual
getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool timing, bool functional, bool is_secure, ArmTranslationType tranType)gem5::ArmISA::TLB
getVMID(ThreadContext *tc) constgem5::ArmISA::TLBprotected
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
haveLargeAsid64gem5::ArmISA::TLBprotected
haveLPAEgem5::ArmISA::TLBprotected
haveVirtualizationgem5::ArmISA::TLBprotected
hcrgem5::ArmISA::TLBprotected
HypMode enum valuegem5::ArmISA::TLB
init()gem5::SimObjectvirtual
initState()gem5::SimObjectvirtual
insert(Addr vaddr, TlbEntry &pte)gem5::ArmISA::TLB
invalidateMiscReg()gem5::ArmISA::TLBinline
isHypgem5::ArmISA::TLBprotected
isPrivgem5::ArmISA::TLBprotected
isSecuregem5::ArmISA::TLBprotected
isStage2gem5::ArmISA::TLBprotected
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
lookup(Addr vpn, uint16_t asn, vmid_t vmid, bool hyp, bool secure, bool functional, bool ignore_asn, ExceptionLevel target_el, bool in_host, BaseMMU::Mode mode)gem5::ArmISA::TLB
m5opRangegem5::ArmISA::TLBprotected
memInvalidate()gem5::BaseTLBinlinevirtual
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
miscRegContextgem5::ArmISA::TLBprotected
miscRegValidgem5::ArmISA::TLBprotected
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
nmrrgem5::ArmISA::TLBprotected
NormalTran enum valuegem5::ArmISA::TLB
notifyFork()gem5::Drainableinlinevirtual
operator=(const Group &)=deletegem5::statistics::Group
Params typedefgem5::ArmISA::TLB
params() constgem5::SimObjectinline
pathgem5::Serializableprivatestatic
physAddrRangegem5::ArmISA::TLBprotected
ppRefillsgem5::ArmISA::TLBprotected
preDumpStats()gem5::statistics::Groupvirtual
printTlb() constgem5::ArmISA::TLB
probeManagergem5::SimObjectprivate
prrrgem5::ArmISA::TLBprotected
rangeMRUgem5::ArmISA::TLBprotected
regProbeListeners()gem5::SimObjectvirtual
regProbePoints() overridegem5::ArmISA::TLBvirtual
regStats()gem5::statistics::Groupvirtual
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
S12E0Tran enum valuegem5::ArmISA::TLB
S12E1Tran enum valuegem5::ArmISA::TLB
S1CTran enum valuegem5::ArmISA::TLB
S1E0Tran enum valuegem5::ArmISA::TLB
S1E1Tran enum valuegem5::ArmISA::TLB
S1E2Tran enum valuegem5::ArmISA::TLB
S1E3Tran enum valuegem5::ArmISA::TLB
S1S2NsTran enum valuegem5::ArmISA::TLB
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
scrgem5::ArmISA::TLBprotected
sctlrgem5::ArmISA::TLBprotected
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::SimObjectinlinevirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setAttr(uint64_t attr)gem5::ArmISA::TLBinline
setCurTick(Tick newVal)gem5::EventManagerinline
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
setStage2Tlb(TLB *stage2_tlb)gem5::ArmISA::TLBinline
setTableWalker(TableWalker *table_walker)gem5::ArmISA::TLB
setTestInterface(SimObject *ti)gem5::ArmISA::TLB
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::SimObject
simObjectListgem5::SimObjectprivatestatic
SimObjectList typedefgem5::SimObjectprivate
sizegem5::ArmISA::TLBprotected
stage2DescReqgem5::ArmISA::TLBprotected
stage2Reqgem5::ArmISA::TLBprotected
stage2Tlbgem5::ArmISA::TLBprotected
startup()gem5::SimObjectvirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::ArmISA::TLBprotected
tablegem5::ArmISA::TLBprotected
tableWalkergem5::ArmISA::TLBprotected
takeOverFrom(BaseTLB *otlb) overridegem5::ArmISA::TLBvirtual
testgem5::ArmISA::TLBprotected
testTranslation(const RequestPtr &req, BaseMMU::Mode mode, TlbEntry::DomainType domain)gem5::ArmISA::TLB
testWalk(Addr pa, Addr size, Addr va, bool is_secure, BaseMMU::Mode mode, TlbEntry::DomainType domain, LookupLevel lookup_level)gem5::ArmISA::TLB
TLB(const Params &p)gem5::ArmISA::TLB
TLB(const Params &p, int _size, TableWalker *_walker)gem5::ArmISA::TLB
translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tranType)gem5::ArmISA::TLB
translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) overridegem5::ArmISA::TLBinlinevirtual
translateComplete(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, ArmTranslationType tranType, bool callFromS2)gem5::ArmISA::TLB
translateFs(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool &delay, bool timing, ArmTranslationType tranType, bool functional=false)gem5::ArmISA::TLB
translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr)gem5::ArmISA::TLB
translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tranType)gem5::ArmISA::TLB
translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) overridegem5::ArmISA::TLBinlinevirtual
translateMmuOff(ThreadContext *tc, const RequestPtr &req, BaseMMU::Mode mode, TLB::ArmTranslationType tranType, Addr vaddr, bool long_desc_format)gem5::ArmISA::TLB
translateMmuOn(ThreadContext *tc, const RequestPtr &req, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool &delay, bool timing, bool functional, Addr vaddr, ArmFault::TranMethod tranMethod)gem5::ArmISA::TLB
translateSe(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool &delay, bool timing)gem5::ArmISA::TLB
translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, ArmTranslationType tranType)gem5::ArmISA::TLB
translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) overridegem5::ArmISA::TLBinlinevirtual
tranTypeEL(CPSR cpsr, ArmTranslationType type)gem5::ArmISA::TLBstatic
trickBoxCheck(const RequestPtr &req, BaseMMU::Mode mode, TlbEntry::DomainType domain)gem5::ArmISA::TLB
ttbcrgem5::ArmISA::TLBprotected
unserialize(CheckpointIn &cp) overridegem5::SimObjectinlinevirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
updateMiscReg(ThreadContext *tc, ArmTranslationType tranType=NormalTran)gem5::ArmISA::TLBprotected
UserMode enum valuegem5::ArmISA::TLB
vmidgem5::ArmISA::TLBprotected
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level)gem5::ArmISA::TLB
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual
~TLB()gem5::ArmISA::TLBvirtual

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