gem5::ArmISA::TLBIASID Class Reference

TLB Invalidate by ASID match. More...

#include <tlbi_op.hh>

Inheritance diagram for gem5::ArmISA::TLBIASID:

Public Member Functions
	TLBIASID (TranslationRegime _target_regime, SecurityState _ss, uint16_t _asid, Attr _attr=Attr::None)
void	operator() (ThreadContext *tc) override
bool	matchEntry (TlbEntry *entry, vmid_t curr_vmid) const override
Public Member Functions inherited from gem5::ArmISA::TLBIOp
	TLBIOp (TranslationRegime _target_regime, SecurityState _ss, Attr _attr)
virtual	~TLBIOp ()
void	broadcast (ThreadContext *tc)
	Broadcast the TLB Invalidate operation to all TLBs in the Arm system.
bool	match (TlbEntry *entry, vmid_t curr_vmid) const
virtual bool	stage1Flush () const
	Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class.
virtual bool	stage2Flush () const
	Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class.

Public Attributes
uint16_t	asid
bool	el2Enabled
Public Attributes inherited from gem5::ArmISA::TLBIOp
SecurityState	ss
TranslationRegime	targetRegime
Attr	attr

Additional Inherited Members
Public Types inherited from gem5::ArmISA::TLBIOp
enum class	Attr { None , ExcludeXS }

Detailed Description

TLB Invalidate by ASID match.

Definition at line 214 of file tlbi_op.hh.

Constructor & Destructor Documentation

TLBIASID()

gem5::ArmISA::TLBIASID::TLBIASID ( TranslationRegime  _target_regime, SecurityState  _ss, uint16_t  _asid, Attr  _attr = Attr::None  )

inline

Definition at line 217 of file tlbi_op.hh.

Member Function Documentation

matchEntry()

bool gem5::ArmISA::TLBIASID::matchEntry ( TlbEntry *  entry, vmid_t  curr_vmid  ) const

overridevirtual

Implements gem5::ArmISA::TLBIOp.

Definition at line 157 of file tlbi_op.cc.

References asid, el2Enabled, gem5::ArmISA::TLBIOp::ss, gem5::ArmISA::TLBIOp::targetRegime, gem5::ArmISA::te, and gem5::ArmISA::useVMID().

Referenced by gem5::ArmISA::ITLBIASID::matchEntry(), and gem5::ArmISA::DTLBIASID::matchEntry().

operator()()

void gem5::ArmISA::TLBIASID::operator() ( ThreadContext *  tc )

overridevirtual

Reimplemented from gem5::ArmISA::TLBIOp.

Definition at line 145 of file tlbi_op.cc.

References el2Enabled, gem5::ArmISA::EL2Enabled(), gem5::ArmISA::MMU::flushStage1(), gem5::ThreadContext::getCheckerCpuPtr(), and gem5::ArmISA::getMMUPtr().

Member Data Documentation

asid

uint16_t gem5::ArmISA::TLBIASID::asid

Definition at line 227 of file tlbi_op.hh.

Referenced by matchEntry().

el2Enabled

bool gem5::ArmISA::TLBIASID::el2Enabled

Definition at line 228 of file tlbi_op.hh.

Referenced by matchEntry(), operator()(), gem5::ArmISA::ITLBIASID::operator()(), and gem5::ArmISA::DTLBIASID::operator()().

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The documentation for this class was generated from the following files:

• arch/arm/tlbi_op.hh
• arch/arm/tlbi_op.cc