gem5 v24.0.0.0
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TLB Invalidate by ASID match. More...
#include <tlbi_op.hh>
Public Member Functions | |
TLBIASID (TranslationRegime _target_regime, bool _secure, uint16_t _asid) | |
void | operator() (ThreadContext *tc) override |
bool | match (TlbEntry *entry, vmid_t curr_vmid) const override |
Public Member Functions inherited from gem5::ArmISA::TLBIOp | |
TLBIOp (TranslationRegime _target_regime, bool _secure) | |
virtual | ~TLBIOp () |
void | broadcast (ThreadContext *tc) |
Broadcast the TLB Invalidate operation to all TLBs in the Arm system. | |
virtual bool | stage1Flush () const |
Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class. | |
virtual bool | stage2Flush () const |
Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class. | |
Public Attributes | |
uint16_t | asid |
bool | el2Enabled |
Public Attributes inherited from gem5::ArmISA::TLBIOp | |
bool | secureLookup |
TranslationRegime | targetRegime |
TLB Invalidate by ASID match.
Definition at line 222 of file tlbi_op.hh.
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inline |
Definition at line 225 of file tlbi_op.hh.
Implements gem5::ArmISA::TLBIOp.
Definition at line 151 of file tlbi_op.cc.
References asid, el2Enabled, gem5::ArmISA::TLBIOp::secureLookup, gem5::ArmISA::TLBIOp::targetRegime, gem5::ArmISA::te, and gem5::ArmISA::useVMID().
Referenced by gem5::ArmISA::DTLBIASID::match(), and gem5::ArmISA::ITLBIASID::match().
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overridevirtual |
Reimplemented from gem5::ArmISA::TLBIOp.
Definition at line 139 of file tlbi_op.cc.
References gem5::ArmISA::EL2Enabled(), el2Enabled, gem5::ArmISA::MMU::flushStage1(), gem5::ThreadContext::getCheckerCpuPtr(), and gem5::ArmISA::getMMUPtr().
uint16_t gem5::ArmISA::TLBIASID::asid |
Definition at line 234 of file tlbi_op.hh.
Referenced by match().
bool gem5::ArmISA::TLBIASID::el2Enabled |
Definition at line 235 of file tlbi_op.hh.
Referenced by match(), gem5::ArmISA::DTLBIASID::operator()(), gem5::ArmISA::ITLBIASID::operator()(), and operator()().