gem5  v21.2.1.1
tlbi_op.cc
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37 
38 #include "arch/arm/tlbi_op.hh"
39 
40 #include "arch/arm/mmu.hh"
41 #include "cpu/checker/cpu.hh"
42 
43 namespace gem5
44 {
45 
46 namespace ArmISA {
47 
48 void
50 {
51  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
52  inHost = (hcr.tge == 1 && hcr.e2h == 1);
53  el2Enabled = EL2Enabled(tc);
54  currentEL = currEL(tc);
55 
56  getMMUPtr(tc)->flush(*this);
57 
58  // If CheckerCPU is connected, need to notify it of a flush
59  CheckerCPU *checker = tc->getCheckerCpuPtr();
60  if (checker) {
61  getMMUPtr(checker)->flush(*this);
62  }
63 }
64 
65 void
67 {
68  el2Enabled = EL2Enabled(tc);
69  getMMUPtr(tc)->iflush(*this);
70 }
71 
72 void
74 {
75  el2Enabled = EL2Enabled(tc);
76  getMMUPtr(tc)->dflush(*this);
77 }
78 
79 void
81 {
82  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
83  inHost = (hcr.tge == 1 && hcr.e2h == 1);
84  getMMUPtr(tc)->flush(*this);
85 
86  // If CheckerCPU is connected, need to notify it of a flush
87  CheckerCPU *checker = tc->getCheckerCpuPtr();
88  if (checker) {
89  getMMUPtr(checker)->flush(*this);
90  }
91 }
92 
93 void
95 {
96  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
97  inHost = (hcr.tge == 1 && hcr.e2h == 1);
98  el2Enabled = EL2Enabled(tc);
99 
100  getMMUPtr(tc)->flush(*this);
101 
102  // If CheckerCPU is connected, need to notify it of a flush
103  CheckerCPU *checker = tc->getCheckerCpuPtr();
104  if (checker) {
105  getMMUPtr(checker)->flush(*this);
106  }
107 }
108 
109 void
111 {
112  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
113  inHost = (hcr.tge == 1 && hcr.e2h == 1);
114  el2Enabled = EL2Enabled(tc);
115 
116  getMMUPtr(tc)->flushStage1(*this);
117  CheckerCPU *checker = tc->getCheckerCpuPtr();
118  if (checker) {
119  getMMUPtr(checker)->flushStage1(*this);
120  }
121 }
122 
123 void
125 {
126  el2Enabled = EL2Enabled(tc);
127  getMMUPtr(tc)->iflush(*this);
128 }
129 
130 void
132 {
133  el2Enabled = EL2Enabled(tc);
134  getMMUPtr(tc)->dflush(*this);
135 }
136 
137 void
139 {
140  getMMUPtr(tc)->flush(*this);
141 
142  CheckerCPU *checker = tc->getCheckerCpuPtr();
143  if (checker) {
144  getMMUPtr(checker)->flush(*this);
145  }
146 }
147 
148 void
150 {
151  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
152  inHost = (hcr.tge == 1 && hcr.e2h == 1);
153  getMMUPtr(tc)->flushStage1(*this);
154 
155  CheckerCPU *checker = tc->getCheckerCpuPtr();
156  if (checker) {
157  getMMUPtr(checker)->flushStage1(*this);
158  }
159 }
160 
161 void
163 {
164  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
165  inHost = (hcr.tge == 1 && hcr.e2h == 1);
166  getMMUPtr(tc)->flushStage1(*this);
167 
168  CheckerCPU *checker = tc->getCheckerCpuPtr();
169  if (checker) {
170  getMMUPtr(checker)->flushStage1(*this);
171  }
172 }
173 
174 void
176 {
177  getMMUPtr(tc)->iflush(*this);
178 }
179 
180 void
182 {
183  getMMUPtr(tc)->dflush(*this);
184 }
185 
186 void
188 {
190 
191  CheckerCPU *checker = tc->getCheckerCpuPtr();
192  if (checker) {
193  getMMUPtr(checker)->flushStage2(makeStage2());
194  }
195 }
196 
197 } // namespace ArmISA
198 } // namespace gem5
gem5::ArmISA::TLBIIPA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:187
gem5::ArmISA::MMU::flush
void flush(const OP &tlbi_op)
Definition: mmu.hh:265
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmISA::DTLBIALL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:73
gem5::ArmISA::DTLBIASID::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:131
gem5::ArmISA::ITLBIASID::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:124
gem5::ArmISA::TLBIALL::inHost
bool inHost
Definition: tlbi_op.hh:130
gem5::ArmISA::TLBIIPA::makeStage2
TLBIMVAA makeStage2() const
TLBIIPA is basically a TLBIMVAA for stage2 TLBs.
Definition: tlbi_op.hh:358
gem5::ArmISA::getMMUPtr
MMU * getMMUPtr(T *tc)
Definition: mmu.hh:470
gem5::ArmISA::ITLBIALL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:66
gem5::ArmISA::TLBIALLN::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:138
gem5::ArmISA::TLBIASID::el2Enabled
bool el2Enabled
Definition: tlbi_op.hh:228
mmu.hh
gem5::ArmISA::TLBIMVA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:162
gem5::ArmISA::TLBIALL::currentEL
ExceptionLevel currentEL
Definition: tlbi_op.hh:132
gem5::ArmISA::MMU::iflush
void iflush(const OP &tlbi_op)
Definition: mmu.hh:301
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::TLBIALLEL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:80
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
cpu.hh
gem5::ArmISA::MMU::flushStage2
void flushStage2(const OP &tlbi_op)
Definition: mmu.hh:293
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:282
tlbi_op.hh
gem5::ArmISA::MMU::dflush
void dflush(const OP &tlbi_op)
Definition: mmu.hh:313
gem5::ArmISA::TLBIASID::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:110
gem5::ArmISA::TLBIALL::el2Enabled
bool el2Enabled
Definition: tlbi_op.hh:131
gem5::ArmISA::TLBIASID::inHost
bool inHost
Definition: tlbi_op.hh:227
gem5::ArmISA::TLBIVMALL::el2Enabled
bool el2Enabled
Definition: tlbi_op.hh:211
gem5::ArmISA::TLBIVMALL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:94
gem5::ArmISA::TLBIMVAA::inHost
bool inHost
Definition: tlbi_op.hh:292
gem5::ArmISA::currEL
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
Definition: utility.cc:128
gem5::ArmISA::TLBIMVA::inHost
bool inHost
Definition: tlbi_op.hh:309
gem5::ArmISA::TLBIALLEL::inHost
bool inHost
Definition: tlbi_op.hh:184
gem5::ArmISA::DTLBIMVA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:181
gem5::ArmISA::ITLBIMVA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:175
gem5::ArmISA::TLBIVMALL::inHost
bool inHost
Definition: tlbi_op.hh:210
gem5::ArmISA::MMU::flushStage1
void flushStage1(const OP &tlbi_op)
Definition: mmu.hh:278
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:586
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ThreadContext::getCheckerCpuPtr
virtual CheckerCPU * getCheckerCpuPtr()=0
gem5::ArmISA::TLBIMVAA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:149
gem5::ArmISA::TLBIALL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:49

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