gem5  v21.1.0.2
tlbi_op.hh
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37 
38 #ifndef __ARCH_ARM_TLBI_HH__
39 #define __ARCH_ARM_TLBI_HH__
40 
41 #include "arch/arm/system.hh"
42 #include "arch/arm/tlb.hh"
43 #include "cpu/thread_context.hh"
44 
52 namespace gem5
53 {
54 
55 namespace ArmISA {
56 
57 class TLBIOp
58 {
59  public:
60  TLBIOp(ExceptionLevel _targetEL, bool _secure)
61  : secureLookup(_secure), targetEL(_targetEL)
62  {}
63 
64  virtual ~TLBIOp() {}
65  virtual void operator()(ThreadContext* tc) {}
66 
72  void
74  {
75  for (auto *oc: tc->getSystemPtr()->threads)
76  (*this)(oc);
77  }
78 
84  virtual bool
85  stage1Flush() const
86  {
87  return true;
88  }
89 
95  virtual bool
96  stage2Flush() const
97  {
98  return false;
99  }
100 
103 };
104 
106 class TLBIALL : public TLBIOp
107 {
108  public:
109  TLBIALL(ExceptionLevel _targetEL, bool _secure)
110  : TLBIOp(_targetEL, _secure), inHost(false), el2Enabled(false),
111  currentEL(EL0)
112  {}
113 
114  void operator()(ThreadContext* tc) override;
115 
116  bool
117  stage2Flush() const override
118  {
119  // TLBIALL (AArch32) flushing stage2 entries if we're currently
120  // in hyp mode
121  return currentEL == EL2;
122  }
123 
124  TLBIALL
125  makeStage2() const
126  {
127  return TLBIALL(EL1, secureLookup);
128  }
129 
130  bool inHost;
133 };
134 
136 class ITLBIALL : public TLBIALL
137 {
138  public:
139  ITLBIALL(ExceptionLevel _targetEL, bool _secure)
140  : TLBIALL(_targetEL, _secure)
141  {}
142 
143  void broadcast(ThreadContext *tc) = delete;
144 
145  void operator()(ThreadContext* tc) override;
146 };
147 
149 class DTLBIALL : public TLBIALL
150 {
151  public:
152  DTLBIALL(ExceptionLevel _targetEL, bool _secure)
153  : TLBIALL(_targetEL, _secure)
154  {}
155 
156  void broadcast(ThreadContext *tc) = delete;
157 
158  void operator()(ThreadContext* tc) override;
159 };
160 
162 class TLBIALLEL : public TLBIOp
163 {
164  public:
165  TLBIALLEL(ExceptionLevel _targetEL, bool _secure)
166  : TLBIOp(_targetEL, _secure), inHost(false)
167  {}
168 
169  void operator()(ThreadContext* tc) override;
170 
171  bool
172  stage2Flush() const override
173  {
174  // If we're targeting EL1 then flush stage2 as well
175  return targetEL == EL1;
176  }
177 
178  TLBIALLEL
179  makeStage2() const
180  {
181  return TLBIALLEL(EL1, secureLookup);
182  }
183 
184  bool inHost;
185 };
186 
188 class TLBIVMALL : public TLBIOp
189 {
190  public:
191  TLBIVMALL(ExceptionLevel _targetEL, bool _secure, bool _stage2)
192  : TLBIOp(_targetEL, _secure), inHost(false), el2Enabled(false),
193  stage2(_stage2)
194  {}
195 
196  void operator()(ThreadContext* tc) override;
197 
198  bool
199  stage2Flush() const override
200  {
201  return stage2;
202  }
203 
204  TLBIVMALL
205  makeStage2() const
206  {
207  return TLBIVMALL(EL1, secureLookup, false);
208  }
209 
210  bool inHost;
212  bool stage2;
213 };
214 
216 class TLBIASID : public TLBIOp
217 {
218  public:
219  TLBIASID(ExceptionLevel _targetEL, bool _secure, uint16_t _asid)
220  : TLBIOp(_targetEL, _secure), asid(_asid), inHost(false),
221  el2Enabled(false)
222  {}
223 
224  void operator()(ThreadContext* tc) override;
225 
226  uint16_t asid;
227  bool inHost;
229 };
230 
232 class ITLBIASID : public TLBIASID
233 {
234  public:
235  ITLBIASID(ExceptionLevel _targetEL, bool _secure, uint16_t _asid)
236  : TLBIASID(_targetEL, _secure, _asid)
237  {}
238 
239  void broadcast(ThreadContext *tc) = delete;
240 
241  void operator()(ThreadContext* tc) override;
242 };
243 
245 class DTLBIASID : public TLBIASID
246 {
247  public:
248  DTLBIASID(ExceptionLevel _targetEL, bool _secure, uint16_t _asid)
249  : TLBIASID(_targetEL, _secure, _asid)
250  {}
251 
252  void broadcast(ThreadContext *tc) = delete;
253 
254  void operator()(ThreadContext* tc) override;
255 };
256 
258 class TLBIALLN : public TLBIOp
259 {
260  public:
262  : TLBIOp(_targetEL, false)
263  {}
264 
265  void operator()(ThreadContext* tc) override;
266 
267  bool
268  stage2Flush() const override
269  {
270  return targetEL != EL2;
271  }
272 
273  TLBIALLN
274  makeStage2() const
275  {
276  return TLBIALLN(EL1);
277  }
278 };
279 
281 class TLBIMVAA : public TLBIOp
282 {
283  public:
284  TLBIMVAA(ExceptionLevel _targetEL, bool _secure,
285  Addr _addr)
286  : TLBIOp(_targetEL, _secure), addr(_addr), inHost(false)
287  {}
288 
289  void operator()(ThreadContext* tc) override;
290 
292  bool inHost;
293 };
294 
296 class TLBIMVA : public TLBIOp
297 {
298  public:
299  TLBIMVA(ExceptionLevel _targetEL, bool _secure,
300  Addr _addr, uint16_t _asid)
301  : TLBIOp(_targetEL, _secure), addr(_addr), asid(_asid),
302  inHost(false)
303  {}
304 
305  void operator()(ThreadContext* tc) override;
306 
308  uint16_t asid;
309  bool inHost;
310 };
311 
313 class ITLBIMVA : public TLBIMVA
314 {
315  public:
316  ITLBIMVA(ExceptionLevel _targetEL, bool _secure,
317  Addr _addr, uint16_t _asid)
318  : TLBIMVA(_targetEL, _secure, _addr, _asid)
319  {}
320 
321  void broadcast(ThreadContext *tc) = delete;
322 
323  void operator()(ThreadContext* tc) override;
324 };
325 
327 class DTLBIMVA : public TLBIMVA
328 {
329  public:
330  DTLBIMVA(ExceptionLevel _targetEL, bool _secure,
331  Addr _addr, uint16_t _asid)
332  : TLBIMVA(_targetEL, _secure, _addr, _asid)
333  {}
334 
335  void broadcast(ThreadContext *tc) = delete;
336 
337  void operator()(ThreadContext* tc) override;
338 };
339 
341 class TLBIIPA : public TLBIOp
342 {
343  public:
344  TLBIIPA(ExceptionLevel _targetEL, bool _secure, Addr _addr)
345  : TLBIOp(_targetEL, _secure), addr(_addr)
346  {}
347 
348  void operator()(ThreadContext* tc) override;
349 
350  bool
351  stage1Flush() const override
352  {
353  return false;
354  }
355 
357  TLBIMVAA
358  makeStage2() const
359  {
360  return TLBIMVAA(EL1, secureLookup, addr);
361  }
362 
364 };
365 
366 } // namespace ArmISA
367 } // namespace gem5
368 
369 #endif //__ARCH_ARM_TLBI_HH__
gem5::ArmISA::DTLBIASID::DTLBIASID
DTLBIASID(ExceptionLevel _targetEL, bool _secure, uint16_t _asid)
Definition: tlbi_op.hh:248
gem5::ArmISA::TLBIIPA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:186
gem5::ArmISA::ITLBIALL
Instruction TLB Invalidate All.
Definition: tlbi_op.hh:136
gem5::ArmISA::TLBIOp::~TLBIOp
virtual ~TLBIOp()
Definition: tlbi_op.hh:64
gem5::ArmISA::TLBIVMALL::TLBIVMALL
TLBIVMALL(ExceptionLevel _targetEL, bool _secure, bool _stage2)
Definition: tlbi_op.hh:191
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::ArmISA::TLBIALLEL
Implementaton of AArch64 TLBI ALLE(1,2,3)(IS) instructions.
Definition: tlbi_op.hh:162
gem5::ArmISA::DTLBIALL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:73
gem5::ArmISA::TLBIASID
TLB Invalidate by ASID match.
Definition: tlbi_op.hh:216
gem5::ArmISA::TLBIALL
TLB Invalidate All.
Definition: tlbi_op.hh:106
gem5::ArmISA::TLBIMVA::asid
uint16_t asid
Definition: tlbi_op.hh:308
gem5::ArmISA::ITLBIASID::ITLBIASID
ITLBIASID(ExceptionLevel _targetEL, bool _secure, uint16_t _asid)
Definition: tlbi_op.hh:235
gem5::ArmISA::TLBIMVA::TLBIMVA
TLBIMVA(ExceptionLevel _targetEL, bool _secure, Addr _addr, uint16_t _asid)
Definition: tlbi_op.hh:299
gem5::ArmISA::DTLBIALL::broadcast
void broadcast(ThreadContext *tc)=delete
gem5::ArmISA::DTLBIASID::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:130
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::ArmISA::ITLBIASID::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:123
tlb.hh
gem5::ArmISA::ITLBIALL::ITLBIALL
ITLBIALL(ExceptionLevel _targetEL, bool _secure)
Definition: tlbi_op.hh:139
system.hh
gem5::ArmISA::TLBIOp::stage1Flush
virtual bool stage1Flush() const
Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract c...
Definition: tlbi_op.hh:85
gem5::ArmISA::DTLBIMVA::DTLBIMVA
DTLBIMVA(ExceptionLevel _targetEL, bool _secure, Addr _addr, uint16_t _asid)
Definition: tlbi_op.hh:330
gem5::ArmISA::TLBIMVAA::TLBIMVAA
TLBIMVAA(ExceptionLevel _targetEL, bool _secure, Addr _addr)
Definition: tlbi_op.hh:284
gem5::ArmISA::TLBIIPA::addr
Addr addr
Definition: tlbi_op.hh:363
gem5::ArmISA::DTLBIASID
Data TLB Invalidate by ASID match.
Definition: tlbi_op.hh:245
gem5::ArmISA::TLBIALL::inHost
bool inHost
Definition: tlbi_op.hh:130
gem5::ArmISA::ITLBIASID
Instruction TLB Invalidate by ASID match.
Definition: tlbi_op.hh:232
gem5::ArmISA::TLBIIPA::makeStage2
TLBIMVAA makeStage2() const
TLBIIPA is basically a TLBIMVAA for stage2 TLBs.
Definition: tlbi_op.hh:358
gem5::ArmISA::TLBIOp::secureLookup
bool secureLookup
Definition: tlbi_op.hh:101
gem5::ArmISA::ITLBIMVA
Instruction TLB Invalidate by VA.
Definition: tlbi_op.hh:313
gem5::ArmISA::TLBIVMALL::stage2Flush
bool stage2Flush() const override
Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract ...
Definition: tlbi_op.hh:199
gem5::ArmISA::TLBIASID::asid
uint16_t asid
Definition: tlbi_op.hh:226
gem5::ArmISA::ITLBIALL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:66
gem5::ArmISA::TLBIALLN::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:137
gem5::ArmISA::TLBIALLN
TLB Invalidate All, Non-Secure.
Definition: tlbi_op.hh:258
gem5::ArmISA::TLBIASID::el2Enabled
bool el2Enabled
Definition: tlbi_op.hh:228
gem5::ArmISA::TLBIMVA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:161
gem5::ArmISA::DTLBIASID::broadcast
void broadcast(ThreadContext *tc)=delete
gem5::ArmISA::TLBIALL::currentEL
ExceptionLevel currentEL
Definition: tlbi_op.hh:132
gem5::ArmISA::TLBIALLN::stage2Flush
bool stage2Flush() const override
Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract ...
Definition: tlbi_op.hh:268
gem5::ArmISA::TLBIOp::operator()
virtual void operator()(ThreadContext *tc)
Definition: tlbi_op.hh:65
gem5::ArmISA::TLBIALL::stage2Flush
bool stage2Flush() const override
Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract ...
Definition: tlbi_op.hh:117
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::TLBIOp::stage2Flush
virtual bool stage2Flush() const
Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract ...
Definition: tlbi_op.hh:96
gem5::ArmISA::TLBIALLEL::stage2Flush
bool stage2Flush() const override
Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract ...
Definition: tlbi_op.hh:172
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::TLBIALLEL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:80
gem5::ArmISA::TLBIMVAA
TLB Invalidate by VA, All ASID.
Definition: tlbi_op.hh:281
gem5::ArmISA::DTLBIMVA::broadcast
void broadcast(ThreadContext *tc)=delete
gem5::ArmISA::TLBIALLN::makeStage2
TLBIALLN makeStage2() const
Definition: tlbi_op.hh:274
gem5::ArmISA::TLBIALL::TLBIALL
TLBIALL(ExceptionLevel _targetEL, bool _secure)
Definition: tlbi_op.hh:109
gem5::ArmISA::TLBIASID::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:109
gem5::ArmISA::TLBIALL::el2Enabled
bool el2Enabled
Definition: tlbi_op.hh:131
gem5::ArmISA::TLBIASID::inHost
bool inHost
Definition: tlbi_op.hh:227
gem5::ArmISA::ITLBIASID::broadcast
void broadcast(ThreadContext *tc)=delete
gem5::ArmISA::TLBIALLN::TLBIALLN
TLBIALLN(ExceptionLevel _targetEL)
Definition: tlbi_op.hh:261
gem5::ArmISA::TLBIVMALL::el2Enabled
bool el2Enabled
Definition: tlbi_op.hh:211
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::DTLBIALL::DTLBIALL
DTLBIALL(ExceptionLevel _targetEL, bool _secure)
Definition: tlbi_op.hh:152
gem5::ArmISA::TLBIVMALL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:94
gem5::ArmISA::TLBIMVAA::inHost
bool inHost
Definition: tlbi_op.hh:292
gem5::ArmISA::TLBIIPA
TLB Invalidate by Intermediate Physical Address.
Definition: tlbi_op.hh:341
gem5::ArmISA::ITLBIALL::broadcast
void broadcast(ThreadContext *tc)=delete
gem5::ArmISA::TLBIMVA::inHost
bool inHost
Definition: tlbi_op.hh:309
gem5::ArmISA::TLBIALLEL::inHost
bool inHost
Definition: tlbi_op.hh:184
gem5::ArmISA::TLBIMVA::addr
Addr addr
Definition: tlbi_op.hh:307
gem5::ArmISA::TLBIALLEL::TLBIALLEL
TLBIALLEL(ExceptionLevel _targetEL, bool _secure)
Definition: tlbi_op.hh:165
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
gem5::ArmISA::TLBIMVAA::addr
Addr addr
Definition: tlbi_op.hh:291
gem5::ArmISA::DTLBIMVA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:180
gem5::ArmISA::ITLBIMVA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:174
gem5::ArmISA::TLBIASID::TLBIASID
TLBIASID(ExceptionLevel _targetEL, bool _secure, uint16_t _asid)
Definition: tlbi_op.hh:219
gem5::System::threads
Threads threads
Definition: system.hh:316
gem5::ArmISA::DTLBIALL
Data TLB Invalidate All.
Definition: tlbi_op.hh:149
gem5::ArmISA::TLBIOp::broadcast
void broadcast(ThreadContext *tc)
Broadcast the TLB Invalidate operation to all TLBs in the Arm system.
Definition: tlbi_op.hh:73
gem5::ArmISA::ITLBIMVA::broadcast
void broadcast(ThreadContext *tc)=delete
gem5::ArmISA::TLBIMVA
TLB Invalidate by VA.
Definition: tlbi_op.hh:296
gem5::ArmISA::TLBIOp::targetEL
ExceptionLevel targetEL
Definition: tlbi_op.hh:102
gem5::ArmISA::TLBIIPA::stage1Flush
bool stage1Flush() const override
Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract c...
Definition: tlbi_op.hh:351
gem5::ArmISA::TLBIVMALL
Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions.
Definition: tlbi_op.hh:188
gem5::ArmISA::TLBIALLEL::makeStage2
TLBIALLEL makeStage2() const
Definition: tlbi_op.hh:179
gem5::ArmISA::TLBIVMALL::inHost
bool inHost
Definition: tlbi_op.hh:210
gem5::ArmISA::TLBIIPA::TLBIIPA
TLBIIPA(ExceptionLevel _targetEL, bool _secure, Addr _addr)
Definition: tlbi_op.hh:344
gem5::ArmISA::ITLBIMVA::ITLBIMVA
ITLBIMVA(ExceptionLevel _targetEL, bool _secure, Addr _addr, uint16_t _asid)
Definition: tlbi_op.hh:316
gem5::ArmISA::TLBIALL::makeStage2
TLBIALL makeStage2() const
Definition: tlbi_op.hh:125
gem5::ArmISA::DTLBIMVA
Data TLB Invalidate by VA.
Definition: tlbi_op.hh:327
gem5::ArmISA::TLBIVMALL::makeStage2
TLBIVMALL makeStage2() const
Definition: tlbi_op.hh:205
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
thread_context.hh
gem5::ArmISA::TLBIMVAA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:148
gem5::ArmISA::TLBIVMALL::stage2
bool stage2
Definition: tlbi_op.hh:212
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
gem5::ArmISA::TLBIOp::TLBIOp
TLBIOp(ExceptionLevel _targetEL, bool _secure)
Definition: tlbi_op.hh:60
gem5::ArmISA::TLBIOp
Definition: tlbi_op.hh:57
gem5::ArmISA::TLBIALL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:49

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