gem5 v24.1.0.1
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gem5::ArmISA::TLBIOp Class Referenceabstract

#include <tlbi_op.hh>

Inheritance diagram for gem5::ArmISA::TLBIOp:
gem5::ArmISA::TLBIALL gem5::ArmISA::TLBIALLEL gem5::ArmISA::TLBIALLN gem5::ArmISA::TLBIASID gem5::ArmISA::TLBIIPA gem5::ArmISA::TLBIMVA gem5::ArmISA::TLBIMVAA gem5::ArmISA::TLBIVMALL

Public Types

enum class  Attr { None , ExcludeXS }
 

Public Member Functions

 TLBIOp (TranslationRegime _target_regime, SecurityState _ss, Attr _attr)
 
virtual ~TLBIOp ()
 
virtual void operator() (ThreadContext *tc)
 
void broadcast (ThreadContext *tc)
 Broadcast the TLB Invalidate operation to all TLBs in the Arm system.
 
bool match (TlbEntry *entry, vmid_t curr_vmid) const
 
virtual bool matchEntry (TlbEntry *entry, vmid_t curr_vmid) const =0
 
virtual bool stage1Flush () const
 Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class.
 
virtual bool stage2Flush () const
 Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class.
 

Public Attributes

SecurityState ss
 
TranslationRegime targetRegime
 
Attr attr
 

Detailed Description

Definition at line 57 of file tlbi_op.hh.

Member Enumeration Documentation

◆ Attr

enum class gem5::ArmISA::TLBIOp::Attr
strong
Enumerator
None 
ExcludeXS 

Definition at line 60 of file tlbi_op.hh.

Constructor & Destructor Documentation

◆ TLBIOp()

gem5::ArmISA::TLBIOp::TLBIOp ( TranslationRegime  _target_regime,
SecurityState  _ss,
Attr  _attr 
)
inline

Definition at line 66 of file tlbi_op.hh.

◆ ~TLBIOp()

virtual gem5::ArmISA::TLBIOp::~TLBIOp ( )
inlinevirtual

Definition at line 70 of file tlbi_op.hh.

Member Function Documentation

◆ broadcast()

void gem5::ArmISA::TLBIOp::broadcast ( ThreadContext tc)
inline

◆ match()

bool gem5::ArmISA::TLBIOp::match ( TlbEntry entry,
vmid_t  curr_vmid 
) const

Definition at line 49 of file tlbi_op.cc.

References attr, ExcludeXS, matchEntry(), and gem5::ArmISA::te.

Referenced by gem5::ArmISA::TLB::flush().

◆ matchEntry()

virtual bool gem5::ArmISA::TLBIOp::matchEntry ( TlbEntry entry,
vmid_t  curr_vmid 
) const
pure virtual

◆ operator()()

virtual void gem5::ArmISA::TLBIOp::operator() ( ThreadContext tc)
inlinevirtual

◆ stage1Flush()

virtual bool gem5::ArmISA::TLBIOp::stage1Flush ( ) const
inlinevirtual

Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class.

Reimplemented in gem5::ArmISA::TLBIIPA.

Definition at line 95 of file tlbi_op.hh.

Referenced by gem5::ArmISA::MMU::flush().

◆ stage2Flush()

virtual bool gem5::ArmISA::TLBIOp::stage2Flush ( ) const
inlinevirtual

Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class.

Reimplemented in gem5::ArmISA::TLBIALL, gem5::ArmISA::TLBIALLEL, gem5::ArmISA::TLBIVMALL, and gem5::ArmISA::TLBIALLN.

Definition at line 106 of file tlbi_op.hh.

Referenced by gem5::ArmISA::MMU::flush().

Member Data Documentation

◆ attr

Attr gem5::ArmISA::TLBIOp::attr

Definition at line 113 of file tlbi_op.hh.

Referenced by match().

◆ ss

SecurityState gem5::ArmISA::TLBIOp::ss

◆ targetRegime

TranslationRegime gem5::ArmISA::TLBIOp::targetRegime

The documentation for this class was generated from the following files:

Generated on Mon Jan 13 2025 04:29:04 for gem5 by doxygen 1.9.8