gem5  v21.1.0.2
utility.hh
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41 
42 #ifndef __ARCH_ARM_UTILITY_HH__
43 #define __ARCH_ARM_UTILITY_HH__
44 
45 #include "arch/arm/regs/cc.hh"
46 #include "arch/arm/regs/int.hh"
47 #include "arch/arm/regs/misc.hh"
48 #include "arch/arm/types.hh"
49 #include "base/logging.hh"
50 #include "base/trace.hh"
51 #include "base/types.hh"
52 #include "cpu/static_inst.hh"
53 #include "cpu/thread_context.hh"
54 
55 namespace gem5
56 {
57 
58 class ArmSystem;
59 
60 namespace ArmISA {
61 
62 inline bool
63 testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
64 {
65  bool n = (nz & 0x2);
66  bool z = (nz & 0x1);
67 
68  switch (code)
69  {
70  case COND_EQ: return z;
71  case COND_NE: return !z;
72  case COND_CS: return c;
73  case COND_CC: return !c;
74  case COND_MI: return n;
75  case COND_PL: return !n;
76  case COND_VS: return v;
77  case COND_VC: return !v;
78  case COND_HI: return (c && !z);
79  case COND_LS: return !(c && !z);
80  case COND_GE: return !(n ^ v);
81  case COND_LT: return (n ^ v);
82  case COND_GT: return !(n ^ v || z);
83  case COND_LE: return (n ^ v || z);
84  case COND_AL: return true;
85  case COND_UC: return true;
86  default:
87  panic("Unhandled predicate condition: %d\n", code);
88  }
89 }
90 
93 void sendEvent(ThreadContext *tc);
94 
95 static inline bool
96 inUserMode(CPSR cpsr)
97 {
98  return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T;
99 }
100 
101 static inline bool
103 {
104  return !inUserMode(cpsr);
105 }
106 
107 bool isSecure(ThreadContext *tc);
108 
109 bool inAArch64(ThreadContext *tc);
110 
111 static inline OperatingMode
113 {
114  CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
115  return (OperatingMode) (uint8_t) cpsr.mode;
116 }
117 
118 static inline ExceptionLevel
120 {
121  return opModeToEL(currOpMode(tc));
122 }
123 
124 inline ExceptionLevel
125 currEL(CPSR cpsr)
126 {
127  return opModeToEL((OperatingMode) (uint8_t)cpsr.mode);
128 }
129 
130 bool HavePACExt(ThreadContext *tc);
132 bool HaveLVA(ThreadContext *tc);
135 bool EL2Enabled(ThreadContext *tc);
136 
154 
157 
158 bool
160 
162 
164 
170 
172 
173 bool isBigEndian64(const ThreadContext *tc);
174 
175 
185 
195 
196 static inline uint8_t
197 itState(CPSR psr)
198 {
199  ITSTATE it = 0;
200  it.top6 = psr.it2;
201  it.bottom2 = psr.it1;
202 
203  return (uint8_t)it;
204 }
205 
207 
216  TCR tcr, bool isInstr);
218  bool isInstr);
219 int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr,
220  TCR tcr, ExceptionLevel el);
221 
222 static inline bool
223 inSecureState(SCR scr, CPSR cpsr)
224 {
225  switch ((OperatingMode) (uint8_t) cpsr.mode) {
226  case MODE_MON:
227  case MODE_EL3T:
228  case MODE_EL3H:
229  return true;
230  case MODE_HYP:
231  case MODE_EL2T:
232  case MODE_EL2H:
233  return false;
234  default:
235  return !scr.ns;
236  }
237 }
238 
240 
242 
246 RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
247 
249 RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
250 
253 
254 static inline uint32_t
255 mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn,
256  uint32_t opc1, uint32_t opc2)
257 {
258  return (isRead << 0) |
259  (crm << 1) |
260  (rt << 5) |
261  (crn << 10) |
262  (opc1 << 14) |
263  (opc2 << 17);
264 }
265 
266 static inline void
267 mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt,
268  uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
269 {
270  isRead = (iss >> 0) & 0x1;
271  crm = (iss >> 1) & 0xF;
272  rt = (IntRegIndex) ((iss >> 5) & 0xF);
273  crn = (iss >> 10) & 0xF;
274  opc1 = (iss >> 14) & 0x7;
275  opc2 = (iss >> 17) & 0x7;
276 }
277 
278 static inline uint32_t
279 mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2,
280  uint32_t opc1)
281 {
282  return (isRead << 0) |
283  (crm << 1) |
284  (rt << 5) |
285  (rt2 << 10) |
286  (opc1 << 16);
287 }
288 
289 static inline uint32_t
290 msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn,
291  uint32_t crm, uint32_t op2, IntRegIndex rt)
292 {
293  return isRead |
294  (crm << 1) |
295  (rt << 5) |
296  (crn << 10) |
297  (op1 << 14) |
298  (op2 << 17) |
299  (op0 << 20);
300 }
301 
302 Fault
303 mcrMrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
304  ThreadContext *tc, uint32_t imm);
305 bool
306 mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss,
307  ExceptionClass *ec = nullptr);
308 
309 bool
310 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
311  HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
312 
313 Fault
314 mcrrMrrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
315  ThreadContext *tc, uint32_t imm);
316 bool
318  uint32_t iss, ExceptionClass *ec = nullptr);
319 
320 Fault
322  ExtMachInst machInst, ThreadContext *tc,
323  uint32_t imm, ExceptionClass ec);
324 bool
326  ThreadContext *tc);
327 bool
329  ThreadContext *tc);
330 bool
332  ExceptionClass *ec);
333 bool condGenericTimerPhysHypTrap(const MiscRegIndex miscReg,
334  ThreadContext *tc);
335 bool
337  ExceptionClass *ec);
338 bool
340  ExceptionClass *ec);
341 bool
343 bool
345  ThreadContext *tc);
346 bool
348  ThreadContext *tc);
349 bool
351  ThreadContext *tc);
352 bool
354  ThreadContext *tc);
355 bool
357  ThreadContext *tc);
358 bool
360  ThreadContext *tc);
361 bool
363  ThreadContext *tc);
364 bool
366  ThreadContext *tc);
367 bool
369  ThreadContext *tc);
370 bool
372  ThreadContext *tc);
373 bool
375  ThreadContext *tc);
376 
378 
381 
382 // Decodes the register index to access based on the fields used in a MSR
383 // or MRS instruction
384 bool
385 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
386  CPSR cpsr, SCR scr, NSACR nsacr,
387  bool checkSecurity = true);
388 
389 // This wrapper function is used to turn the register index into a source
390 // parameter for the instruction. See Operands.isa
391 static inline int
392 decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
393 {
394  int regIdx;
395  bool isIntReg;
396  bool validReg;
397 
398  validReg = decodeMrsMsrBankedReg(sysM, r, isIntReg, regIdx, 0, 0, 0, false);
399  return (validReg && isIntReg) ? regIdx : INTREG_DUMMY;
400 }
401 
405 int decodePhysAddrRange64(uint8_t pa_enc);
406 
410 uint8_t encodePhysAddrRange64(int pa_size);
411 
412 inline ByteOrder byteOrder(const ThreadContext *tc)
413 {
414  return isBigEndian64(tc) ? ByteOrder::big : ByteOrder::little;
415 };
416 
418 
419 } // namespace ArmISA
420 } // namespace gem5
421 
422 #endif
gem5::ArmISA::AArch64AArch32SystemAccessTrap
Fault AArch64AArch32SystemAccessTrap(const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm, ExceptionClass ec)
Definition: utility.cc:790
gem5::ArmISA::MODE_EL2H
@ MODE_EL2H
Definition: types.hh:278
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::condGenericTimerCommonEL0SystemAccessTrapEL2
bool condGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1043
gem5::ArmISA::COND_HI
@ COND_HI
Definition: cc.hh:77
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::ArmISA::ELIs64
bool ELIs64(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:282
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:72
gem5::ArmISA::COND_NE
@ COND_NE
Definition: cc.hh:70
gem5::ArmISA::MODE_EL2T
@ MODE_EL2T
Definition: types.hh:277
gem5::ArmISA::testPredicate
bool testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
Definition: utility.hh:63
gem5::ArmISA::decodePhysAddrRange64
int decodePhysAddrRange64(uint8_t pa_enc)
Returns the n.
Definition: utility.cc:1288
gem5::ArmISA::isGenericTimerVirtSystemAccessTrapEL2
bool isGenericTimerVirtSystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1034
gem5::ArmISA::encodePhysAddrRange64
uint8_t encodePhysAddrRange64(int pa_size)
Returns the encoding corresponding to the specified n.
Definition: utility.cc:1311
gem5::ArmISA::isSecureBelowEL3
bool isSecureBelowEL3(ThreadContext *tc)
Definition: utility.cc:84
gem5::ArmISA::currEL
static ExceptionLevel currEL(const ThreadContext *tc)
Definition: utility.hh:119
gem5::ArmISA::condGenericTimerPhysHypTrap
bool condGenericTimerPhysHypTrap(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:867
gem5::ArmISA::mcrMrc15TrapToHyp
bool mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Definition: utility.cc:512
gem5::ArmISA::mcrMrc15Trap
Fault mcrMrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm)
Definition: utility.cc:502
gem5::ArmISA::byteOrder
ByteOrder byteOrder(const ThreadContext *tc)
Definition: utility.hh:412
gem5::ArmISA::opModeToEL
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:383
gem5::ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:297
gem5::ArmISA::mcrrMrrc15Trap
Fault mcrrMrrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm)
Definition: utility.cc:719
gem5::ArmISA::inAArch64
bool inAArch64(ThreadContext *tc)
Definition: utility.cc:120
gem5::ArmISA::mcrrMrrc15TrapToHyp
bool mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Definition: utility.cc:729
gem5::ArmISA::COND_PL
@ COND_PL
Definition: cc.hh:74
gem5::ArmISA::opc2
Bitfield< 7, 5 > opc2
Definition: types.hh:106
gem5::ArmISA::badMode
bool badMode(ThreadContext *tc, OperatingMode mode)
badMode is checking if the execution mode provided as an argument is valid and implemented.
Definition: utility.cc:412
gem5::ArmISA::MODE_EL3H
@ MODE_EL3H
Definition: types.hh:280
types.hh
cc.hh
gem5::ArmISA::truncPage
Addr truncPage(Addr addr)
Definition: utility.cc:490
gem5::ArmISA::isGenericTimerSystemAccessTrapEL3
bool isGenericTimerSystemAccessTrapEL3(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1112
gem5::ArmISA::condGenericTimerSystemAccessTrapEL1
bool condGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:901
gem5::ArmISA::ELUsingAArch32K
std::pair< bool, bool > ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
This function checks whether selected EL provided as an argument is using the AArch32 ISA.
Definition: utility.cc:307
gem5::ArmISA::HaveLVA
bool HaveLVA(ThreadContext *tc)
Definition: utility.cc:231
gem5::ArmISA::ec
ec
Definition: misc_types.hh:669
gem5::ArmISA::purifyTaggedAddr
Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool isInstr)
Removes the tag from tagged addresses if that mode is enabled.
Definition: utility.cc:463
gem5::ArmISA::HavePACExt
bool HavePACExt(ThreadContext *tc)
Definition: utility.cc:216
gem5::ArmISA::COND_CS
@ COND_CS
Definition: cc.hh:71
gem5::ArmISA::COND_LT
@ COND_LT
Definition: cc.hh:80
gem5::ArmISA::MODE_EL3T
@ MODE_EL3T
Definition: types.hh:279
gem5::ArmISA::mcrMrcIssBuild
static uint32_t mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn, uint32_t opc1, uint32_t opc2)
Definition: utility.hh:255
gem5::ArmISA::z
Bitfield< 11 > z
Definition: misc_types.hh:374
gem5::ArmISA::nz
nz
Definition: misc_types.hh:52
gem5::ArmISA::isGenericTimerPhysEL0SystemAccessTrapEL2
bool isGenericTimerPhysEL0SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:989
gem5::ArmISA::isGenericTimerHypTrap
bool isGenericTimerHypTrap(const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:818
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:287
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::HaveVirtHostExt
bool HaveVirtHostExt(ThreadContext *tc)
Definition: utility.cc:224
gem5::ArmISA::roundPage
Addr roundPage(Addr addr)
Definition: utility.cc:496
gem5::ArmISA::COND_VC
@ COND_VC
Definition: cc.hh:76
gem5::ArmISA::rt
Bitfield< 15, 12 > rt
Definition: types.hh:115
gem5::ArmISA::COND_UC
@ COND_UC
Definition: cc.hh:84
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:288
gem5::ArmISA::computeAddrTop
int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr, TCR tcr, ExceptionLevel el)
Definition: utility.cc:418
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::ArmISA::condGenericTimerCommonEL1SystemAccessTrapEL2
bool condGenericTimerCommonEL1SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1070
gem5::ArmISA::isGenericTimerPhysEL1SystemAccessTrapEL2
bool isGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1012
gem5::ArmISA::getAffinity
RegVal getAffinity(ArmSystem *arm_sys, ThreadContext *tc)
Retrieves MPIDR_EL1.
Definition: utility.cc:210
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:274
gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL1
bool isAArch64AArch32SystemAccessTrapEL1(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:804
gem5::ArmISA::msrMrs64IssBuild
static uint32_t msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, IntRegIndex rt)
Definition: utility.hh:290
gem5::ArmISA::SPAlignmentCheckEnabled
bool SPAlignmentCheckEnabled(ThreadContext *tc)
Definition: utility.cc:1264
static_inst.hh
gem5::ArmISA::COND_EQ
@ COND_EQ
Definition: cc.hh:69
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:281
gem5::ArmISA::COND_VS
@ COND_VS
Definition: cc.hh:75
std::pair
STL pair class.
Definition: stl.hh:58
gem5::ArmISA::c
Bitfield< 29 > c
Definition: misc_types.hh:53
gem5::ArmISA::s1TranslationRegime
ExceptionLevel s1TranslationRegime(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:238
gem5::ArmISA::isGenericTimerSystemAccessTrapEL1
bool isGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:882
gem5::ArmISA::debugTargetFrom
ExceptionLevel debugTargetFrom(ThreadContext *tc, bool secure)
Definition: utility.cc:91
gem5::ArmISA::COND_AL
@ COND_AL
Definition: cc.hh:83
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::inPrivilegedMode
static bool inPrivilegedMode(CPSR cpsr)
Definition: utility.hh:102
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:72
gem5::ArmISA::ELStateUsingAArch32K
std::pair< bool, bool > ELStateUsingAArch32K(ThreadContext *tc, ExceptionLevel el, bool secure)
Definition: utility.cc:328
gem5::ArmISA::COND_MI
@ COND_MI
Definition: cc.hh:73
gem5::ArmISA::COND_LS
@ COND_LS
Definition: cc.hh:78
gem5::ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:293
gem5::ArmISA::currOpMode
static OperatingMode currOpMode(const ThreadContext *tc)
Definition: utility.hh:112
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::IsSecureEL2Enabled
bool IsSecureEL2Enabled(ThreadContext *tc)
Definition: utility.cc:260
gem5::ArmSystem
Definition: system.hh:62
gem5::ArmISA::decodeMrsMsrBankedIntRegIndex
static int decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
Definition: utility.hh:392
gem5::ArmISA::COND_LE
@ COND_LE
Definition: cc.hh:82
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::decodeMrsMsrBankedReg
bool decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
Definition: utility.cc:1128
gem5::ArmISA::MODE_EL0T
@ MODE_EL0T
Definition: types.hh:274
gem5::ArmISA::isUnpriviledgeAccess
bool isUnpriviledgeAccess(ThreadContext *tc)
Definition: utility.cc:1247
gem5::ArmISA::n
Bitfield< 31 > n
Definition: misc_types.hh:455
types.hh
gem5::ArmISA::isGenericTimerCommonEL0SystemAccessTrapEL2
bool isGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:976
misc.hh
gem5::ArmISA::sendEvent
void sendEvent(ThreadContext *tc)
Send an event (SEV) to a specific PE if there isn't already a pending event.
Definition: utility.cc:63
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:67
gem5::ArmISA::ELStateUsingAArch32
bool ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure)
Definition: utility.cc:378
gem5::ArmISA::longDescFormatInUse
bool longDescFormatInUse(ThreadContext *tc)
Definition: utility.cc:127
gem5::ArmISA::inUserMode
static bool inUserMode(CPSR cpsr)
Definition: utility.hh:96
logging.hh
gem5::ArmISA::inSecureState
static bool inSecureState(SCR scr, CPSR cpsr)
Definition: utility.hh:223
gem5::ArmISA::mcrMrc14TrapToHyp
bool mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
Definition: utility.cc:669
gem5::ArmISA::HaveSecureEL2Ext
bool HaveSecureEL2Ext(ThreadContext *tc)
Definition: utility.cc:253
gem5::ArmISA::COND_GE
@ COND_GE
Definition: cc.hh:79
gem5::ArmISA::badMode32
bool badMode32(ThreadContext *tc, OperatingMode mode)
badMode is checking if the execution mode provided as an argument is valid and implemented for AArch3...
Definition: utility.cc:406
gem5::ArmISA::isGenericTimerPhysHypTrap
bool isGenericTimerPhysHypTrap(const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:860
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL2
bool isAArch64AArch32SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:928
trace.hh
gem5::ArmISA::isGenericTimerCommonEL0HypTrap
bool isGenericTimerCommonEL0HypTrap(const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:844
gem5::ArmISA::itState
static uint8_t itState(CPSR psr)
Definition: utility.hh:197
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::condGenericTimerPhysEL1SystemAccessTrapEL2
bool condGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1104
gem5::ArmISA::isBigEndian64
bool isBigEndian64(const ThreadContext *tc)
Definition: utility.cc:388
int.hh
gem5::ArmISA::COND_GT
@ COND_GT
Definition: cc.hh:81
gem5::ArmISA::isGenericTimerSystemAccessTrapEL2
bool isGenericTimerSystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:942
thread_context.hh
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::ArmISA::readMPIDR
RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR),...
Definition: utility.cc:134
gem5::ArmISA::mcrrMrrcIssBuild
static uint32_t mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2, uint32_t opc1)
Definition: utility.hh:279
gem5::ArmISA::getMPIDR
RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is returning the value of MPIDR_EL1.
Definition: utility.cc:162
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::COND_CC
@ COND_CC
Definition: cc.hh:72
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ArmISA::mcrMrcIssExtract
static void mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt, uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
Definition: utility.hh:267

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