gem5  v21.2.1.1
utility.hh
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41 
42 #ifndef __ARCH_ARM_UTILITY_HH__
43 #define __ARCH_ARM_UTILITY_HH__
44 
45 #include "arch/arm/regs/cc.hh"
46 #include "arch/arm/regs/int.hh"
47 #include "arch/arm/regs/misc.hh"
48 #include "arch/arm/types.hh"
49 #include "base/logging.hh"
50 #include "base/trace.hh"
51 #include "base/types.hh"
52 #include "cpu/static_inst.hh"
53 #include "cpu/thread_context.hh"
54 
55 namespace gem5
56 {
57 
58 class ArmSystem;
59 
60 namespace ArmISA
61 {
62 
63 inline bool
64 testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
65 {
66  bool n = (nz & 0x2);
67  bool z = (nz & 0x1);
68 
69  switch (code) {
70  case COND_EQ: return z;
71  case COND_NE: return !z;
72  case COND_CS: return c;
73  case COND_CC: return !c;
74  case COND_MI: return n;
75  case COND_PL: return !n;
76  case COND_VS: return v;
77  case COND_VC: return !v;
78  case COND_HI: return (c && !z);
79  case COND_LS: return !(c && !z);
80  case COND_GE: return !(n ^ v);
81  case COND_LT: return (n ^ v);
82  case COND_GT: return !(n ^ v || z);
83  case COND_LE: return (n ^ v || z);
84  case COND_AL: return true;
85  case COND_UC: return true;
86  default:
87  panic("Unhandled predicate condition: %d\n", code);
88  }
89 }
90 
93 void sendEvent(ThreadContext *tc);
94 
95 static inline bool
96 inUserMode(CPSR cpsr)
97 {
98  return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T;
99 }
100 
101 static inline bool
103 {
104  return !inUserMode(cpsr);
105 }
106 
107 bool isSecure(ThreadContext *tc);
108 
109 bool inAArch64(ThreadContext *tc);
110 
116 
117 inline ExceptionLevel
118 currEL(CPSR cpsr)
119 {
120  return opModeToEL((OperatingMode) (uint8_t)cpsr.mode);
121 }
122 
123 bool HavePACExt(ThreadContext *tc);
125 bool HaveLVA(ThreadContext *tc);
128 bool EL2Enabled(ThreadContext *tc);
129 
146 
148  ExceptionLevel el, bool secure);
149 
150 bool ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure);
151 
153 
155 
161 
163 
164 bool isBigEndian64(const ThreadContext *tc);
165 
166 
176 
186 
187 static inline uint8_t
188 itState(CPSR psr)
189 {
190  ITSTATE it = 0;
191  it.top6 = psr.it2;
192  it.bottom2 = psr.it1;
193 
194  return (uint8_t)it;
195 }
196 
198 
207  TCR tcr, bool isInstr);
209  bool isInstr);
210 int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr,
211  TCR tcr, ExceptionLevel el);
212 
214 
216 
220 RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
221 
223 RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
224 
227 
228 static inline uint32_t
229 mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn,
230  uint32_t opc1, uint32_t opc2)
231 {
232  return (isRead << 0) |
233  (crm << 1) |
234  (rt << 5) |
235  (crn << 10) |
236  (opc1 << 14) |
237  (opc2 << 17);
238 }
239 
240 static inline void
241 mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt,
242  uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
243 {
244  isRead = (iss >> 0) & 0x1;
245  crm = (iss >> 1) & 0xF;
246  rt = (IntRegIndex)((iss >> 5) & 0xF);
247  crn = (iss >> 10) & 0xF;
248  opc1 = (iss >> 14) & 0x7;
249  opc2 = (iss >> 17) & 0x7;
250 }
251 
252 static inline uint32_t
253 mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2,
254  uint32_t opc1)
255 {
256  return (isRead << 0) |
257  (crm << 1) |
258  (rt << 5) |
259  (rt2 << 10) |
260  (opc1 << 16);
261 }
262 
263 static inline uint32_t
264 msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn,
265  uint32_t crm, uint32_t op2, IntRegIndex rt)
266 {
267  return isRead |
268  (crm << 1) |
269  (rt << 5) |
270  (crn << 10) |
271  (op1 << 14) |
272  (op2 << 17) |
273  (op0 << 20);
274 }
275 
276 Fault mcrMrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
277  ThreadContext *tc, uint32_t imm);
278 bool mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
279  uint32_t iss, ExceptionClass *ec=nullptr);
280 
281 bool mcrMrc14TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
282  uint32_t iss);
283 
284 Fault mcrrMrrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
285  ThreadContext *tc, uint32_t imm);
286 bool mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
287  uint32_t iss, ExceptionClass *ec=nullptr);
288 
290  ExtMachInst machInst, ThreadContext *tc,
291  uint32_t imm, ExceptionClass ec);
293  ThreadContext *tc);
295  ThreadContext *tc);
296 bool isGenericTimerHypTrap(const MiscRegIndex miscReg, ThreadContext *tc,
297  ExceptionClass *ec);
298 bool condGenericTimerPhysHypTrap(const MiscRegIndex miscReg,
299  ThreadContext *tc);
303  ExceptionClass *ec);
304 bool condGenericTimerPhysHypTrap(const MiscRegIndex miscReg,
305  ThreadContext *tc);
307  ThreadContext *tc);
309  ThreadContext *tc);
311  ThreadContext *tc);
313  ThreadContext *tc);
315  ThreadContext *tc);
317  ThreadContext *tc);
319  ThreadContext *tc);
321  ThreadContext *tc);
323  ThreadContext *tc);
325  ThreadContext *tc);
327  ThreadContext *tc);
328 
330 
333 
334 // Decodes the register index to access based on the fields used in a MSR
335 // or MRS instruction
336 bool decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
337  CPSR cpsr, SCR scr, NSACR nsacr,
338  bool checkSecurity=true);
339 
340 // This wrapper function is used to turn the register index into a source
341 // parameter for the instruction. See Operands.isa
342 static inline int
343 decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
344 {
345  int regIdx;
346  bool isIntReg;
347  bool validReg;
348 
349  validReg = decodeMrsMsrBankedReg(
350  sysM, r, isIntReg, regIdx, 0, 0, 0, false);
351  return (validReg && isIntReg) ? regIdx : INTREG_ZERO;
352 }
353 
357 int decodePhysAddrRange64(uint8_t pa_enc);
358 
362 uint8_t encodePhysAddrRange64(int pa_size);
363 
364 inline ByteOrder
366 {
367  return isBigEndian64(tc) ? ByteOrder::big : ByteOrder::little;
368 };
369 
371 
374 
375 } // namespace ArmISA
376 } // namespace gem5
377 
378 #endif
gem5::ArmISA::COND_HI
@ COND_HI
Definition: cc.hh:77
gem5::ArmISA::ELIs64
bool ELIs64(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:290
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmISA::COND_NE
@ COND_NE
Definition: cc.hh:70
gem5::ArmISA::isGenericTimerPhysEL1SystemAccessTrapEL2
bool isGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1022
gem5::ArmISA::isGenericTimerHypTrap
bool isGenericTimerHypTrap(const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:826
gem5::ArmISA::testPredicate
bool testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
Definition: utility.hh:64
gem5::ArmISA::decodePhysAddrRange64
int decodePhysAddrRange64(uint8_t pa_enc)
Returns the n.
Definition: utility.cc:1299
gem5::ArmISA::isGenericTimerSystemAccessTrapEL1
bool isGenericTimerSystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:890
gem5::ArmISA::isGenericTimerCommonEL0HypTrap
bool isGenericTimerCommonEL0HypTrap(const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:852
gem5::ArmISA::encodePhysAddrRange64
uint8_t encodePhysAddrRange64(int pa_size)
Returns the encoding corresponding to the specified n.
Definition: utility.cc:1322
gem5::ArmISA::isSecureBelowEL3
bool isSecureBelowEL3(ThreadContext *tc)
Definition: utility.cc:85
gem5::ArmISA::isGenericTimerSystemAccessTrapEL2
bool isGenericTimerSystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:950
gem5::ArmISA::mcrrMrrc15TrapToHyp
bool mcrrMrrc15TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Definition: utility.cc:738
gem5::ArmISA::byteOrder
ByteOrder byteOrder(const ThreadContext *tc)
Definition: utility.hh:365
gem5::ArmISA::opModeToEL
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:383
gem5::ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:304
gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL2
bool isAArch64AArch32SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:936
gem5::ArmISA::inAArch64
bool inAArch64(ThreadContext *tc)
Definition: utility.cc:121
gem5::ArmISA::COND_PL
@ COND_PL
Definition: cc.hh:74
gem5::ArmISA::opc2
Bitfield< 7, 5 > opc2
Definition: types.hh:106
gem5::ArmISA::badMode
bool badMode(ThreadContext *tc, OperatingMode mode)
badMode is checking if the execution mode provided as an argument is valid and implemented.
Definition: utility.cc:418
types.hh
cc.hh
gem5::ArmISA::AArch64AArch32SystemAccessTrap
Fault AArch64AArch32SystemAccessTrap(const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm, ExceptionClass ec)
Definition: utility.cc:798
gem5::ArmISA::truncPage
Addr truncPage(Addr addr)
Definition: utility.cc:496
gem5::ArmISA::ELUsingAArch32K
std::pair< bool, bool > ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
This function checks whether selected EL provided as an argument is using the AArch32 ISA.
Definition: utility.cc:314
gem5::ArmISA::condGenericTimerCommonEL0SystemAccessTrapEL2
bool condGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1056
gem5::ArmISA::condGenericTimerSystemAccessTrapEL1
bool condGenericTimerSystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:909
gem5::ArmISA::mcrMrc14TrapToHyp
bool mcrMrc14TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss)
Definition: utility.cc:673
gem5::ArmISA::HaveLVA
bool HaveLVA(ThreadContext *tc)
Definition: utility.cc:239
gem5::ArmISA::ec
ec
Definition: misc_types.hh:670
gem5::ArmISA::mcrMrc15Trap
Fault mcrMrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm)
Definition: utility.cc:508
gem5::ArmISA::purifyTaggedAddr
Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool is_instr)
Removes the tag from tagged addresses if that mode is enabled.
Definition: utility.cc:469
gem5::ArmISA::HavePACExt
bool HavePACExt(ThreadContext *tc)
Definition: utility.cc:224
gem5::ArmISA::isGenericTimerCommonEL0SystemAccessTrapEL2
bool isGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:984
gem5::ArmISA::COND_CS
@ COND_CS
Definition: cc.hh:71
gem5::ArmISA::COND_LT
@ COND_LT
Definition: cc.hh:80
gem5::ArmISA::mcrMrcIssBuild
static uint32_t mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn, uint32_t opc1, uint32_t opc2)
Definition: utility.hh:229
gem5::ArmISA::z
Bitfield< 11 > z
Definition: misc_types.hh:375
gem5::ArmISA::nz
nz
Definition: misc_types.hh:52
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::mcrrMrrc15Trap
Fault mcrrMrrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm)
Definition: utility.cc:728
gem5::ArmISA::condGenericTimerPhysHypTrap
bool condGenericTimerPhysHypTrap(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:875
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::HaveVirtHostExt
bool HaveVirtHostExt(ThreadContext *tc)
Definition: utility.cc:232
gem5::ArmISA::roundPage
Addr roundPage(Addr addr)
Definition: utility.cc:502
gem5::ArmISA::COND_VC
@ COND_VC
Definition: cc.hh:76
gem5::ArmISA::rt
Bitfield< 15, 12 > rt
Definition: types.hh:115
gem5::ArmISA::COND_UC
@ COND_UC
Definition: cc.hh:84
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:296
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::ArmISA::syncVecElemsToRegs
void syncVecElemsToRegs(ThreadContext *tc)
Definition: utility.cc:1358
gem5::ArmISA::getAffinity
RegVal getAffinity(ArmSystem *arm_sys, ThreadContext *tc)
Retrieves MPIDR_EL1.
Definition: utility.cc:218
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:282
gem5::ArmISA::msrMrs64IssBuild
static uint32_t msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, IntRegIndex rt)
Definition: utility.hh:264
gem5::ArmISA::SPAlignmentCheckEnabled
bool SPAlignmentCheckEnabled(ThreadContext *tc)
Definition: utility.cc:1275
static_inst.hh
gem5::ArmISA::COND_EQ
@ COND_EQ
Definition: cc.hh:69
gem5::ArmISA::mcrMrc15TrapToHyp
bool mcrMrc15TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Definition: utility.cc:518
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:281
gem5::ArmISA::COND_VS
@ COND_VS
Definition: cc.hh:75
std::pair
STL pair class.
Definition: stl.hh:58
gem5::ArmISA::c
Bitfield< 29 > c
Definition: misc_types.hh:53
gem5::ArmISA::s1TranslationRegime
ExceptionLevel s1TranslationRegime(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:246
gem5::ArmISA::debugTargetFrom
ExceptionLevel debugTargetFrom(ThreadContext *tc, bool secure)
Definition: utility.cc:92
gem5::ArmISA::COND_AL
@ COND_AL
Definition: cc.hh:83
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::inPrivilegedMode
static bool inPrivilegedMode(CPSR cpsr)
Definition: utility.hh:102
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:73
gem5::ArmISA::ELStateUsingAArch32K
std::pair< bool, bool > ELStateUsingAArch32K(ThreadContext *tc, ExceptionLevel el, bool secure)
Definition: utility.cc:335
gem5::ArmISA::COND_MI
@ COND_MI
Definition: cc.hh:73
gem5::ArmISA::COND_LS
@ COND_LS
Definition: cc.hh:78
gem5::ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:293
gem5::ArmISA::currEL
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
Definition: utility.cc:128
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::IsSecureEL2Enabled
bool IsSecureEL2Enabled(ThreadContext *tc)
Definition: utility.cc:268
gem5::ArmSystem
Definition: system.hh:91
gem5::ArmISA::decodeMrsMsrBankedIntRegIndex
static int decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
Definition: utility.hh:343
gem5::ArmISA::COND_LE
@ COND_LE
Definition: cc.hh:82
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::syncVecRegsToElems
void syncVecRegsToElems(ThreadContext *tc)
Definition: utility.cc:1345
gem5::ArmISA::decodeMrsMsrBankedReg
bool decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
Definition: utility.cc:1141
gem5::ArmISA::MODE_EL0T
@ MODE_EL0T
Definition: types.hh:274
gem5::ArmISA::isUnpriviledgeAccess
bool isUnpriviledgeAccess(ThreadContext *tc)
Definition: utility.cc:1258
gem5::ArmISA::n
Bitfield< 31 > n
Definition: misc_types.hh:456
types.hh
gem5::ArmISA::isGenericTimerSystemAccessTrapEL3
bool isGenericTimerSystemAccessTrapEL3(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1125
misc.hh
gem5::ArmISA::sendEvent
void sendEvent(ThreadContext *tc)
Send an event (SEV) to a specific PE if there isn't already a pending event.
Definition: utility.cc:64
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:67
gem5::ArmISA::ELStateUsingAArch32
bool ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure)
Definition: utility.cc:386
gem5::ArmISA::longDescFormatInUse
bool longDescFormatInUse(ThreadContext *tc)
Definition: utility.cc:135
gem5::ArmISA::inUserMode
static bool inUserMode(CPSR cpsr)
Definition: utility.hh:96
logging.hh
gem5::ArmISA::HaveSecureEL2Ext
bool HaveSecureEL2Ext(ThreadContext *tc)
Definition: utility.cc:261
gem5::ArmISA::COND_GE
@ COND_GE
Definition: cc.hh:79
gem5::ArmISA::badMode32
bool badMode32(ThreadContext *tc, OperatingMode mode)
badMode is checking if the execution mode provided as an argument is valid and implemented for AArch3...
Definition: utility.cc:412
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::ArmISA::isGenericTimerVirtSystemAccessTrapEL2
bool isGenericTimerVirtSystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1046
trace.hh
gem5::ArmISA::condGenericTimerPhysEL1SystemAccessTrapEL2
bool condGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1117
gem5::ArmISA::condGenericTimerCommonEL1SystemAccessTrapEL2
bool condGenericTimerCommonEL1SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1083
gem5::ArmISA::itState
static uint8_t itState(CPSR psr)
Definition: utility.hh:188
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::computeAddrTop
int computeAddrTop(ThreadContext *tc, bool selbit, bool is_instr, TCR tcr, ExceptionLevel el)
Definition: utility.cc:424
gem5::ArmISA::isGenericTimerPhysHypTrap
bool isGenericTimerPhysHypTrap(const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:868
gem5::ArmISA::isBigEndian64
bool isBigEndian64(const ThreadContext *tc)
Definition: utility.cc:394
gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL1
bool isAArch64AArch32SystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:812
int.hh
gem5::ArmISA::COND_GT
@ COND_GT
Definition: cc.hh:81
gem5::ArmISA::isGenericTimerPhysEL0SystemAccessTrapEL2
bool isGenericTimerPhysEL0SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:997
thread_context.hh
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::ArmISA::readMPIDR
RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR),...
Definition: utility.cc:142
gem5::ArmISA::mcrrMrrcIssBuild
static uint32_t mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2, uint32_t opc1)
Definition: utility.hh:253
gem5::ArmISA::getMPIDR
RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is returning the value of MPIDR_EL1.
Definition: utility.cc:170
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::COND_CC
@ COND_CC
Definition: cc.hh:72
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ArmISA::mcrMrcIssExtract
static void mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt, uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
Definition: utility.hh:241

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