gem5  v22.0.0.2
utility.hh
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41 
42 #ifndef __ARCH_ARM_UTILITY_HH__
43 #define __ARCH_ARM_UTILITY_HH__
44 
45 #include "arch/arm/regs/cc.hh"
46 #include "arch/arm/regs/int.hh"
47 #include "arch/arm/regs/misc.hh"
48 #include "arch/arm/types.hh"
49 #include "base/logging.hh"
50 #include "base/trace.hh"
51 #include "base/types.hh"
52 #include "cpu/static_inst.hh"
53 #include "cpu/thread_context.hh"
54 #include "enums/ArmExtension.hh"
55 
56 namespace gem5
57 {
58 
59 class ArmSystem;
60 
61 namespace ArmISA
62 {
63 
64 inline bool
65 testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
66 {
67  bool n = (nz & 0x2);
68  bool z = (nz & 0x1);
69 
70  switch (code) {
71  case COND_EQ: return z;
72  case COND_NE: return !z;
73  case COND_CS: return c;
74  case COND_CC: return !c;
75  case COND_MI: return n;
76  case COND_PL: return !n;
77  case COND_VS: return v;
78  case COND_VC: return !v;
79  case COND_HI: return (c && !z);
80  case COND_LS: return !(c && !z);
81  case COND_GE: return !(n ^ v);
82  case COND_LT: return (n ^ v);
83  case COND_GT: return !(n ^ v || z);
84  case COND_LE: return (n ^ v || z);
85  case COND_AL: return true;
86  case COND_UC: return true;
87  default:
88  panic("Unhandled predicate condition: %d\n", code);
89  }
90 }
91 
94 void sendEvent(ThreadContext *tc);
95 
96 static inline bool
97 inUserMode(CPSR cpsr)
98 {
99  return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T;
100 }
101 
102 static inline bool
104 {
105  return !inUserMode(cpsr);
106 }
107 
108 bool isSecure(ThreadContext *tc);
109 
110 bool inAArch64(ThreadContext *tc);
111 
117 
118 inline ExceptionLevel
119 currEL(CPSR cpsr)
120 {
121  return opModeToEL((OperatingMode) (uint8_t)cpsr.mode);
122 }
123 
128 bool HaveExt(ThreadContext *tc, ArmExtension ext);
129 
131 bool EL2Enabled(ThreadContext *tc);
132 
149 
151  ExceptionLevel el, bool secure);
152 
153 bool ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure);
154 
156 
158 
164 
166 
167 bool isBigEndian64(const ThreadContext *tc);
168 
169 
179 
189 
190 static inline uint8_t
191 itState(CPSR psr)
192 {
193  ITSTATE it = 0;
194  it.top6 = psr.it2;
195  it.bottom2 = psr.it1;
196 
197  return (uint8_t)it;
198 }
199 
201 
210  TCR tcr, bool isInstr);
212  bool isInstr);
214  int topbit);
215 int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr,
216  TCR tcr, ExceptionLevel el);
217 
219 
221 
225 RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
226 
228 RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
229 
231 Affinity getAffinity(ArmSystem *arm_sys, ThreadContext *tc);
232 
233 static inline uint32_t
234 mcrMrcIssBuild(bool isRead, uint32_t crm, RegIndex rt, uint32_t crn,
235  uint32_t opc1, uint32_t opc2)
236 {
237  return (isRead << 0) |
238  (crm << 1) |
239  (rt << 5) |
240  (crn << 10) |
241  (opc1 << 14) |
242  (opc2 << 17);
243 }
244 
245 static inline void
246 mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, RegIndex &rt,
247  uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
248 {
249  isRead = (iss >> 0) & 0x1;
250  crm = (iss >> 1) & 0xF;
251  rt = (RegIndex)((iss >> 5) & 0xF);
252  crn = (iss >> 10) & 0xF;
253  opc1 = (iss >> 14) & 0x7;
254  opc2 = (iss >> 17) & 0x7;
255 }
256 
257 static inline uint32_t
258 mcrrMrrcIssBuild(bool isRead, uint32_t crm, RegIndex rt, RegIndex rt2,
259  uint32_t opc1)
260 {
261  return (isRead << 0) |
262  (crm << 1) |
263  (rt << 5) |
264  (rt2 << 10) |
265  (opc1 << 16);
266 }
267 
268 static inline uint32_t
269 msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn,
270  uint32_t crm, uint32_t op2, RegIndex rt)
271 {
272  return isRead |
273  (crm << 1) |
274  (rt << 5) |
275  (crn << 10) |
276  (op1 << 14) |
277  (op2 << 17) |
278  (op0 << 20);
279 }
280 
281 Fault mcrMrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
282  ThreadContext *tc, uint32_t imm);
283 bool mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
284  uint32_t iss, ExceptionClass *ec=nullptr);
285 
286 bool mcrMrc14TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
287  uint32_t iss);
288 
289 Fault mcrrMrrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
290  ThreadContext *tc, uint32_t imm);
291 bool mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
292  uint32_t iss, ExceptionClass *ec=nullptr);
293 
295  ExtMachInst machInst, ThreadContext *tc,
296  uint32_t imm, ExceptionClass ec);
298  ThreadContext *tc);
300  ThreadContext *tc);
301 bool isGenericTimerHypTrap(const MiscRegIndex miscReg, ThreadContext *tc,
302  ExceptionClass *ec);
303 bool condGenericTimerPhysHypTrap(const MiscRegIndex miscReg,
304  ThreadContext *tc);
308  ExceptionClass *ec);
309 bool condGenericTimerPhysHypTrap(const MiscRegIndex miscReg,
310  ThreadContext *tc);
312  ThreadContext *tc);
314  ThreadContext *tc);
316  ThreadContext *tc);
318  ThreadContext *tc);
320  ThreadContext *tc);
322  ThreadContext *tc);
324  ThreadContext *tc);
326  ThreadContext *tc);
328  ThreadContext *tc);
330  ThreadContext *tc);
332  ThreadContext *tc);
333 
335 
338 
339 // Decodes the register index to access based on the fields used in a MSR
340 // or MRS instruction
341 bool decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
342  CPSR cpsr, SCR scr, NSACR nsacr,
343  bool checkSecurity=true);
344 
345 // This wrapper function is used to turn the register index into a source
346 // parameter for the instruction. See Operands.isa
347 static inline int
348 decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
349 {
350  int regIdx;
351  bool isIntReg;
352  bool validReg;
353 
354  validReg = decodeMrsMsrBankedReg(
355  sysM, r, isIntReg, regIdx, 0, 0, 0, false);
356  return (validReg && isIntReg) ? regIdx : int_reg::Zero;
357 }
358 
362 int decodePhysAddrRange64(uint8_t pa_enc);
363 
367 uint8_t encodePhysAddrRange64(int pa_size);
368 
369 inline ByteOrder
371 {
372  return isBigEndian64(tc) ? ByteOrder::big : ByteOrder::little;
373 };
374 
376 
379 
380 } // namespace ArmISA
381 } // namespace gem5
382 
383 #endif
gem5::ArmISA::mcrMrcIssExtract
static void mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, RegIndex &rt, uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
Definition: utility.hh:246
gem5::ArmISA::COND_HI
@ COND_HI
Definition: cc.hh:92
gem5::ArmISA::maskTaggedAddr
Addr maskTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, int topbit)
Definition: utility.cc:455
gem5::ArmISA::ELIs64
bool ELIs64(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:273
gem5::ArmISA::getAffinity
Affinity getAffinity(ArmSystem *arm_sys, ThreadContext *tc)
Retrieves MPIDR_EL1.
Definition: utility.cc:219
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmISA::COND_NE
@ COND_NE
Definition: cc.hh:85
gem5::ArmISA::isGenericTimerPhysEL1SystemAccessTrapEL2
bool isGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1015
gem5::ArmISA::isGenericTimerHypTrap
bool isGenericTimerHypTrap(const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:819
gem5::ArmISA::testPredicate
bool testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
Definition: utility.hh:65
gem5::ArmISA::decodePhysAddrRange64
int decodePhysAddrRange64(uint8_t pa_enc)
Returns the n.
Definition: utility.cc:1293
gem5::ArmISA::iss
Bitfield< 24, 0 > iss
Definition: misc_types.hh:672
gem5::ArmISA::isGenericTimerSystemAccessTrapEL1
bool isGenericTimerSystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:883
gem5::ArmISA::isGenericTimerCommonEL0HypTrap
bool isGenericTimerCommonEL0HypTrap(const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:845
gem5::ArmISA::encodePhysAddrRange64
uint8_t encodePhysAddrRange64(int pa_size)
Returns the encoding corresponding to the specified n.
Definition: utility.cc:1316
gem5::ArmISA::isSecureBelowEL3
bool isSecureBelowEL3(ThreadContext *tc)
Definition: utility.cc:85
gem5::ArmISA::isGenericTimerSystemAccessTrapEL2
bool isGenericTimerSystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:943
gem5::ArmISA::mcrrMrrc15TrapToHyp
bool mcrrMrrc15TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Definition: utility.cc:731
gem5::ArmISA::byteOrder
ByteOrder byteOrder(const ThreadContext *tc)
Definition: utility.hh:370
gem5::ArmISA::opModeToEL
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:390
gem5::ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:287
gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL2
bool isAArch64AArch32SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:929
gem5::ArmISA::inAArch64
bool inAArch64(ThreadContext *tc)
Definition: utility.cc:122
gem5::VegaISA::r
Bitfield< 5 > r
Definition: pagetable.hh:60
gem5::ArmISA::COND_PL
@ COND_PL
Definition: cc.hh:89
gem5::ArmISA::opc2
Bitfield< 7, 5 > opc2
Definition: types.hh:106
gem5::ArmISA::badMode
bool badMode(ThreadContext *tc, OperatingMode mode)
badMode is checking if the execution mode provided as an argument is valid and implemented.
Definition: utility.cc:403
types.hh
cc.hh
gem5::ArmISA::AArch64AArch32SystemAccessTrap
Fault AArch64AArch32SystemAccessTrap(const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm, ExceptionClass ec)
Definition: utility.cc:791
gem5::ArmISA::truncPage
Addr truncPage(Addr addr)
Definition: utility.cc:489
gem5::ArmISA::ELUsingAArch32K
std::pair< bool, bool > ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
This function checks whether selected EL provided as an argument is using the AArch32 ISA.
Definition: utility.cc:298
gem5::ArmISA::condGenericTimerCommonEL0SystemAccessTrapEL2
bool condGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1049
gem5::ArmISA::condGenericTimerSystemAccessTrapEL1
bool condGenericTimerSystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:902
gem5::ArmISA::mcrMrc14TrapToHyp
bool mcrMrc14TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss)
Definition: utility.cc:666
gem5::ArmISA::ec
ec
Definition: misc_types.hh:670
gem5::ArmISA::mcrMrc15Trap
Fault mcrMrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm)
Definition: utility.cc:501
gem5::ArmISA::purifyTaggedAddr
Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool is_instr)
Removes the tag from tagged addresses if that mode is enabled.
Definition: utility.cc:470
gem5::ArmISA::isGenericTimerCommonEL0SystemAccessTrapEL2
bool isGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:977
gem5::ArmISA::COND_CS
@ COND_CS
Definition: cc.hh:86
gem5::ArmISA::COND_LT
@ COND_LT
Definition: cc.hh:95
gem5::ArmISA::z
Bitfield< 11 > z
Definition: misc_types.hh:375
gem5::ArmISA::nz
nz
Definition: misc_types.hh:52
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::mcrrMrrc15Trap
Fault mcrrMrrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm)
Definition: utility.cc:721
gem5::ArmISA::condGenericTimerPhysHypTrap
bool condGenericTimerPhysHypTrap(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:868
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::ArmISA::roundPage
Addr roundPage(Addr addr)
Definition: utility.cc:495
gem5::ArmISA::COND_VC
@ COND_VC
Definition: cc.hh:91
gem5::ArmISA::rt
Bitfield< 15, 12 > rt
Definition: types.hh:115
gem5::ArmISA::COND_UC
@ COND_UC
Definition: cc.hh:99
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:279
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::ArmISA::syncVecElemsToRegs
void syncVecElemsToRegs(ThreadContext *tc)
Definition: utility.cc:1354
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:264
gem5::ArmISA::SPAlignmentCheckEnabled
bool SPAlignmentCheckEnabled(ThreadContext *tc)
Definition: utility.cc:1269
static_inst.hh
gem5::ArmISA::COND_EQ
@ COND_EQ
Definition: cc.hh:84
gem5::ArmISA::mcrMrc15TrapToHyp
bool mcrMrc15TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Definition: utility.cc:511
gem5::ArmISA::mcrMrcIssBuild
static uint32_t mcrMrcIssBuild(bool isRead, uint32_t crm, RegIndex rt, uint32_t crn, uint32_t opc1, uint32_t opc2)
Definition: utility.hh:234
gem5::ArmISA::ext
Bitfield< 12 > ext
Definition: misc_types.hh:428
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:288
gem5::ArmISA::COND_VS
@ COND_VS
Definition: cc.hh:90
std::pair
STL pair class.
Definition: stl.hh:58
gem5::ArmISA::c
Bitfield< 29 > c
Definition: misc_types.hh:53
gem5::ArmISA::s1TranslationRegime
ExceptionLevel s1TranslationRegime(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:236
gem5::ArmISA::debugTargetFrom
ExceptionLevel debugTargetFrom(ThreadContext *tc, bool secure)
Definition: utility.cc:92
gem5::ArmISA::COND_AL
@ COND_AL
Definition: cc.hh:98
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::inPrivilegedMode
static bool inPrivilegedMode(CPSR cpsr)
Definition: utility.hh:103
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:73
gem5::ArmISA::ELStateUsingAArch32K
std::pair< bool, bool > ELStateUsingAArch32K(ThreadContext *tc, ExceptionLevel el, bool secure)
Definition: utility.cc:319
gem5::ArmISA::COND_MI
@ COND_MI
Definition: cc.hh:88
gem5::ArmISA::COND_LS
@ COND_LS
Definition: cc.hh:93
gem5::ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:300
gem5::ArmISA::currEL
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
Definition: utility.cc:129
gem5::X86ISA::ExtMachInst
Definition: types.hh:212
gem5::ArmISA::IsSecureEL2Enabled
bool IsSecureEL2Enabled(ThreadContext *tc)
Definition: utility.cc:250
gem5::ArmSystem
Definition: system.hh:91
gem5::ArmISA::decodeMrsMsrBankedIntRegIndex
static int decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
Definition: utility.hh:348
gem5::ArmISA::COND_LE
@ COND_LE
Definition: cc.hh:97
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::syncVecRegsToElems
void syncVecRegsToElems(ThreadContext *tc)
Definition: utility.cc:1339
gem5::ArmISA::decodeMrsMsrBankedReg
bool decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
Definition: utility.cc:1134
gem5::ArmISA::MODE_EL0T
@ MODE_EL0T
Definition: types.hh:281
gem5::ArmISA::isUnpriviledgeAccess
bool isUnpriviledgeAccess(ThreadContext *tc)
Definition: utility.cc:1251
gem5::ArmISA::n
Bitfield< 31 > n
Definition: misc_types.hh:456
types.hh
gem5::ArmISA::isGenericTimerSystemAccessTrapEL3
bool isGenericTimerSystemAccessTrapEL3(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1118
misc.hh
gem5::ArmISA::sendEvent
void sendEvent(ThreadContext *tc)
Send an event (SEV) to a specific PE if there isn't already a pending event.
Definition: utility.cc:64
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:82
gem5::ArmISA::ELStateUsingAArch32
bool ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure)
Definition: utility.cc:371
gem5::ArmISA::longDescFormatInUse
bool longDescFormatInUse(ThreadContext *tc)
Definition: utility.cc:136
gem5::ArmISA::inUserMode
static bool inUserMode(CPSR cpsr)
Definition: utility.hh:97
logging.hh
gem5::ArmISA::COND_GE
@ COND_GE
Definition: cc.hh:94
gem5::ArmISA::badMode32
bool badMode32(ThreadContext *tc, OperatingMode mode)
badMode is checking if the execution mode provided as an argument is valid and implemented for AArch3...
Definition: utility.cc:397
gem5::ArmISA::isGenericTimerVirtSystemAccessTrapEL2
bool isGenericTimerVirtSystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1039
trace.hh
gem5::ArmISA::condGenericTimerPhysEL1SystemAccessTrapEL2
bool condGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1110
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::ArmISA::mcrrMrrcIssBuild
static uint32_t mcrrMrrcIssBuild(bool isRead, uint32_t crm, RegIndex rt, RegIndex rt2, uint32_t opc1)
Definition: utility.hh:258
gem5::ArmISA::condGenericTimerCommonEL1SystemAccessTrapEL2
bool condGenericTimerCommonEL1SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1076
gem5::ArmISA::itState
static uint8_t itState(CPSR psr)
Definition: utility.hh:191
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::computeAddrTop
int computeAddrTop(ThreadContext *tc, bool selbit, bool is_instr, TCR tcr, ExceptionLevel el)
Definition: utility.cc:409
gem5::ArmISA::cc_reg::Zero
constexpr RegId Zero(CCRegClass, _ZeroIdx)
gem5::ArmISA::isGenericTimerPhysHypTrap
bool isGenericTimerPhysHypTrap(const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
Definition: utility.cc:861
gem5::ArmISA::isBigEndian64
bool isBigEndian64(const ThreadContext *tc)
Definition: utility.cc:379
gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL1
bool isAArch64AArch32SystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:805
int.hh
gem5::ArmISA::COND_GT
@ COND_GT
Definition: cc.hh:96
gem5::ArmISA::msrMrs64IssBuild
static uint32_t msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, RegIndex rt)
Definition: utility.hh:269
gem5::ArmISA::HaveExt
bool HaveExt(ThreadContext *tc, ArmExtension ext)
Returns true if the provided ThreadContext supports the ArmExtension passed as a second argument.
Definition: utility.cc:229
gem5::ArmISA::isGenericTimerPhysEL0SystemAccessTrapEL2
bool isGenericTimerPhysEL0SystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:990
thread_context.hh
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:279
gem5::ArmISA::readMPIDR
RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR),...
Definition: utility.cc:143
gem5::ArmISA::getMPIDR
RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is returning the value of MPIDR_EL1.
Definition: utility.cc:171
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:271
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::COND_CC
@ COND_CC
Definition: cc.hh:87
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

Generated on Thu Jul 28 2022 13:32:25 for gem5 by doxygen 1.8.17