Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions. More...

#include <tlbi_op.hh>

Inheritance diagram for gem5::ArmISA::TLBIVMALL:

Public Member Functions
	TLBIVMALL (TranslationRegime _target_regime, SecurityState _ss, bool _stage2, Attr _attr)

void	operator() (ThreadContext *tc) override

bool	matchEntry (TlbEntry *entry, vmid_t curr_vmid) const override

bool	stage2Flush () const override
	Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class.

Public Member Functions inherited from gem5::ArmISA::TLBIOp
	TLBIOp (TranslationRegime _target_regime, SecurityState _ss, Attr _attr)

virtual	~TLBIOp ()

void	broadcast (ThreadContext *tc)
	Broadcast the TLB Invalidate operation to all TLBs in the Arm system.

bool	match (TlbEntry *entry, vmid_t curr_vmid) const

virtual bool	stage1Flush () const
	Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class.

Public Attributes
bool	el2Enabled

bool	stage2

Public Attributes inherited from gem5::ArmISA::TLBIOp
SecurityState	ss

TranslationRegime	targetRegime

Attr	attr

Additional Inherited Members
Public Types inherited from gem5::ArmISA::TLBIOp
enum class	Attr { None , ExcludeXS }

Detailed Description

Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions.

Definition at line 190 of file tlbi_op.hh.

Constructor & Destructor Documentation

◆ TLBIVMALL()

gem5::ArmISA::TLBIVMALL::TLBIVMALL	(	TranslationRegime	_target_regime,
		SecurityState	_ss,
		bool	_stage2,
		Attr	_attr
	)

inline

Definition at line 193 of file tlbi_op.hh.

Member Function Documentation

◆ matchEntry()

bool gem5::ArmISA::TLBIVMALL::matchEntry	(	TlbEntry *	entry,
		vmid_t	curr_vmid
	)		const

overridevirtual

Implements gem5::ArmISA::TLBIOp.

Definition at line 137 of file tlbi_op.cc.

References el2Enabled, gem5::ArmISA::TLBIOp::ss, gem5::ArmISA::TLBIOp::targetRegime, gem5::ArmISA::te, and gem5::ArmISA::useVMID().

◆ operator()()

void gem5::ArmISA::TLBIVMALL::operator() ( ThreadContext * tc )

overridevirtual

Reimplemented from gem5::ArmISA::TLBIOp.

Definition at line 123 of file tlbi_op.cc.

References el2Enabled, gem5::ArmISA::EL2Enabled(), gem5::ArmISA::MMU::flush(), gem5::ThreadContext::getCheckerCpuPtr(), and gem5::ArmISA::getMMUPtr().

◆ stage2Flush()

bool gem5::ArmISA::TLBIVMALL::stage2Flush ( ) const

inlineoverridevirtual

Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class.

Reimplemented from gem5::ArmISA::TLBIOp.

Definition at line 204 of file tlbi_op.hh.

References stage2.

Member Data Documentation

◆ el2Enabled

bool gem5::ArmISA::TLBIVMALL::el2Enabled

Definition at line 209 of file tlbi_op.hh.

Referenced by matchEntry(), and operator()().

◆ stage2

bool gem5::ArmISA::TLBIVMALL::stage2

Definition at line 210 of file tlbi_op.hh.

Referenced by stage2Flush().

The documentation for this class was generated from the following files:

arch/arm/tlbi_op.hh
arch/arm/tlbi_op.cc

Public Member Functions

Public Attributes

Additional Inherited Members