gem5 v24.0.0.0
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gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4 Class Reference

#include <instructions.hh>

Inheritance diagram for gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4:
gem5::VegaISA::Inst_SMEM gem5::VegaISA::VEGAGPUStaticInst gem5::GPUStaticInst

Public Member Functions

int getNumOperands () override
int numDstRegOperands () override
int numSrcRegOperands () override
int getOperandSize (int opIdx) override
void execute (GPUDynInstPtr) override
void initiateAcc (GPUDynInstPtr) override
void completeAcc (GPUDynInstPtr) override
- Public Member Functions inherited from gem5::VegaISA::Inst_SMEM
 Inst_SMEM (InFmt_SMEM *, const std::string &opcode)
 ~Inst_SMEM ()
int instSize () const override
void generateDisassembly () override
void initOperandInfo () override
- Public Member Functions inherited from gem5::VegaISA::VEGAGPUStaticInst
 VEGAGPUStaticInst (const std::string &opcode)
 ~VEGAGPUStaticInst ()
void generateDisassembly () override
bool isFlatScratchRegister (int opIdx) override
bool isExecMaskRegister (int opIdx) override
void initOperandInfo () override
int getOperandSize (int opIdx) override
int coalescerTokenCount () const override
 Return the number of tokens needed by the coalescer.
ScalarRegU32 srcLiteral () const override
- Public Member Functions inherited from gem5::GPUStaticInst
 GPUStaticInst (const std::string &opcode)
virtual ~GPUStaticInst ()
void instAddr (int inst_addr)
int instAddr () const
int nextInstAddr () const
void instNum (int num)
int instNum ()
void ipdInstNum (int num)
int ipdInstNum () const
void initDynOperandInfo (Wavefront *wf, ComputeUnit *cu)
const std::string & disassemble ()
int numSrcVecOperands ()
int numDstVecOperands ()
int numSrcVecDWords ()
int numDstVecDWords ()
int numSrcScalarOperands ()
int numDstScalarOperands ()
int numSrcScalarDWords ()
int numDstScalarDWords ()
int maxOperandSize ()
bool isALU () const
bool isBranch () const
bool isCondBranch () const
bool isNop () const
bool isReturn () const
bool isEndOfKernel () const
bool isKernelLaunch () const
bool isSDWAInst () const
bool isDPPInst () const
bool isUnconditionalJump () const
bool isSpecialOp () const
bool isWaitcnt () const
bool isSleep () const
bool isBarrier () const
bool isMemSync () const
bool isMemRef () const
bool isFlat () const
bool isFlatGlobal () const
bool isFlatScratch () const
bool isLoad () const
bool isStore () const
bool isAtomic () const
bool isAtomicNoRet () const
bool isAtomicRet () const
bool isScalar () const
bool readsSCC () const
bool writesSCC () const
bool readsVCC () const
bool writesVCC () const
bool readsEXEC () const
bool writesEXEC () const
bool readsMode () const
bool writesMode () const
bool ignoreExec () const
bool isAtomicAnd () const
bool isAtomicOr () const
bool isAtomicXor () const
bool isAtomicCAS () const
bool isAtomicExch () const
bool isAtomicAdd () const
bool isAtomicSub () const
bool isAtomicInc () const
bool isAtomicDec () const
bool isAtomicMax () const
bool isAtomicMin () const
bool isArgLoad () const
bool isGlobalMem () const
bool isLocalMem () const
bool isArgSeg () const
bool isGlobalSeg () const
bool isGroupSeg () const
bool isKernArgSeg () const
bool isPrivateSeg () const
bool isReadOnlySeg () const
bool isSpillSeg () const
bool isGloballyCoherent () const
 Coherence domain of a memory instruction.
bool isSystemCoherent () const
bool isI8 () const
bool isF16 () const
bool isF32 () const
bool isF64 () const
bool isFMA () const
bool isMAC () const
bool isMAD () const
bool isMFMA () const
virtual uint32_t getTargetPc ()
void setFlag (Flags flag)
const std::string & opcode () const
const std::vector< OperandInfo > & srcOperands () const
const std::vector< OperandInfo > & dstOperands () const
const std::vector< OperandInfo > & srcVecRegOperands () const
const std::vector< OperandInfo > & dstVecRegOperands () const
const std::vector< OperandInfo > & srcScalarRegOperands () const
const std::vector< OperandInfo > & dstScalarRegOperands () const

Additional Inherited Members

- Public Types inherited from gem5::GPUStaticInst
typedef int(RegisterManager::* MapRegFn) (Wavefront *, int)
- Public Attributes inherited from gem5::GPUStaticInst
enums::StorageClassType executed_as
- Static Public Attributes inherited from gem5::GPUStaticInst
static uint64_t dynamic_id_count
- Protected Member Functions inherited from gem5::VegaISA::Inst_SMEM
template<int N>
void initMemRead (GPUDynInstPtr gpuDynInst)
 initiate a memory read access for N dwords
template<int N>
void initMemWrite (GPUDynInstPtr gpuDynInst)
 initiate a memory write access for N dwords
void calcAddr (GPUDynInstPtr gpu_dyn_inst, ConstScalarOperandU64 &addr, ScalarRegU32 offset)
 For normal s_load_dword/s_store_dword instruction addresses.
void calcAddr (GPUDynInstPtr gpu_dyn_inst, ConstScalarOperandU128 &s_rsrc_desc, ScalarRegU32 offset)
 For s_buffer_load_dword/s_buffer_store_dword instruction addresses.
- Protected Member Functions inherited from gem5::VegaISA::VEGAGPUStaticInst
void panicUnimplemented () const
- Protected Attributes inherited from gem5::VegaISA::Inst_SMEM
InFmt_SMEM instData
InFmt_SMEM_1 extData
- Protected Attributes inherited from gem5::VegaISA::VEGAGPUStaticInst
ScalarRegU32 _srcLiteral
 if the instruction has a src literal - an immediate value that is part of the instruction stream - we store that here
- Protected Attributes inherited from gem5::GPUStaticInst
const std::string _opcode
std::string disassembly
int _instNum
int _instAddr
std::vector< OperandInfosrcOps
std::vector< OperandInfodstOps

Detailed Description

Definition at line 5467 of file instructions.hh.

Constructor & Destructor Documentation


gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4::Inst_SMEM__S_LOAD_DWORDX4 ( InFmt_SMEM * iFmt)

Definition at line 153 of file

References gem5::GPUStaticInst::setFlag().


gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4::~Inst_SMEM__S_LOAD_DWORDX4 ( )

Definition at line 160 of file

Member Function Documentation

◆ completeAcc()

void gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4::completeAcc ( GPUDynInstPtr gpuDynInst)

◆ execute()

◆ getNumOperands()

int gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4::getNumOperands ( )

Implements gem5::GPUStaticInst.

Definition at line 5474 of file instructions.hh.

References numDstRegOperands(), and numSrcRegOperands().

◆ getOperandSize()

int gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4::getOperandSize ( int opIdx)

Implements gem5::GPUStaticInst.

Definition at line 5483 of file instructions.hh.

References fatal.

◆ initiateAcc()

void gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4::initiateAcc ( GPUDynInstPtr gpuDynInst)

Reimplemented from gem5::GPUStaticInst.

Definition at line 194 of file

References gem5::VegaISA::Inst_SMEM::initMemRead().

◆ numDstRegOperands()

int gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4::numDstRegOperands ( )

Implements gem5::GPUStaticInst.

Definition at line 5479 of file instructions.hh.

Referenced by getNumOperands().

◆ numSrcRegOperands()

int gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4::numSrcRegOperands ( )

Implements gem5::GPUStaticInst.

Definition at line 5480 of file instructions.hh.

Referenced by getNumOperands().

The documentation for this class was generated from the following files:

Generated on Tue Jun 18 2024 16:24:33 for gem5 by doxygen 1.11.0