| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| addToRetryList(MemResponsePort *port) | gem5::ruby::RubyPort | inlineprivate |
| atomicCallback(Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0)) | gem5::ruby::Sequencer | |
| clockDomain | gem5::Clocked | private |
| Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
| Clocked(Clocked &)=delete | gem5::Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
| clockPeriod() const | gem5::Clocked | inline |
| clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
| collateStats() | gem5::ruby::Sequencer | |
| completeHitCallback(std::vector< PacketPtr > &list) | gem5::ruby::Sequencer | |
| coreId() const | gem5::ruby::Sequencer | inline |
| CpuPortIter typedef | gem5::ruby::RubyPort | private |
| curCycle() const | gem5::Clocked | inline |
| currentSection() | gem5::Serializable | static |
| cycle | gem5::Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
| deadlockCheckEvent | gem5::ruby::Sequencer | private |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| descheduleDeadlockEvent() override | gem5::ruby::Sequencer | inlinevirtual |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| drain() override | gem5::ruby::RubyPort | virtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() | gem5::Drainable | inlineprotectedvirtual |
| drainState() const | gem5::Drainable | inline |
| empty() const override | gem5::ruby::HTMSequencer | virtual |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| evictionCallback(Addr address) | gem5::ruby::Sequencer | |
| find(const char *name) | gem5::SimObject | static |
| frequency() const | gem5::Clocked | inline |
| functionalWrite(Packet *func_pkt) override | gem5::ruby::Sequencer | virtual |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getCurrentUnaddressedTransactionID() const | gem5::ruby::Sequencer | private |
| getFirstResponseToCompletionDelayHist(const MachineType t) const | gem5::ruby::Sequencer | inline |
| getForwardRequestToFirstResponseHist(const MachineType t) const | gem5::ruby::Sequencer | inline |
| getHitLatencyHist() | gem5::ruby::Sequencer | inline |
| getHitMachLatencyHist(uint32_t t) | gem5::ruby::Sequencer | inline |
| getHitTypeLatencyHist(uint32_t t) | gem5::ruby::Sequencer | inline |
| getHitTypeMachLatencyHist(uint32_t r, uint32_t t) | gem5::ruby::Sequencer | inline |
| getId() | gem5::ruby::RubyPort | inline |
| getIncompleteTimes(const MachineType t) const | gem5::ruby::Sequencer | inline |
| getInitialToForwardDelayHist(const MachineType t) const | gem5::ruby::Sequencer | inline |
| getIssueToInitialDelayHist(uint32_t t) const | gem5::ruby::Sequencer | inline |
| getLatencyHist() | gem5::ruby::Sequencer | inline |
| getMissLatencyHist() | gem5::ruby::Sequencer | inline |
| getMissMachLatencyHist(uint32_t t) const | gem5::ruby::Sequencer | inline |
| getMissTypeLatencyHist(uint32_t t) | gem5::ruby::Sequencer | inline |
| getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const | gem5::ruby::Sequencer | inline |
| getOutstandReqHist() | gem5::ruby::Sequencer | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | gem5::ruby::RubyPort | virtual |
| getProbeManager() | gem5::SimObject | |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| getTypeLatencyHist(uint32_t t) | gem5::ruby::Sequencer | inline |
| gotAddrRanges | gem5::ruby::RubyPort | private |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| hitCallback(SequencerRequest *srequest, DataBlock &data, bool llscSuccess, const MachineType mach, const bool externalHit, const Cycles initialRequestTime, const Cycles forwardRequestTime, const Cycles firstResponseTime, const bool was_coalesced) | gem5::ruby::Sequencer | private |
| htmCallback(Addr, const HtmCallbackMode, const HtmFailedInCacheReason) | gem5::ruby::HTMSequencer | |
| htmRetCodeConversion(const HtmFailedInCacheReason rc) | gem5::ruby::HTMSequencer | private |
| HTMSequencer(const RubyHTMSequencerParams &p) | gem5::ruby::HTMSequencer | |
| HTMSequencer(const HTMSequencer &obj) | gem5::ruby::HTMSequencer | private |
| incrementUnaddressedTransactionCnt() | gem5::ruby::Sequencer | private |
| init() override | gem5::ruby::RubyPort | virtual |
| initState() | gem5::SimObject | virtual |
| insertRequest(PacketPtr pkt, RubyRequestType primary_type, RubyRequestType secondary_type) override | gem5::ruby::HTMSequencer | privatevirtual |
| invL1() | gem5::ruby::Sequencer | |
| invL1Callback() | gem5::ruby::Sequencer | |
| isCPUSequencer() | gem5::ruby::RubyPort | inline |
| isDeadlockEventScheduled() const override | gem5::ruby::Sequencer | inlinevirtual |
| issueRequest(PacketPtr pkt, RubyRequestType type) | gem5::ruby::Sequencer | private |
| llscCheckMonitor(const Addr) | gem5::ruby::Sequencer | |
| llscClearLocalMonitor() | gem5::ruby::Sequencer | |
| llscClearMonitor(const Addr) | gem5::ruby::Sequencer | private |
| llscLoadLinked(const Addr) | gem5::ruby::Sequencer | private |
| llscStoreConditional(const Addr) | gem5::ruby::Sequencer | private |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| m_cache_inv_pkt | gem5::ruby::Sequencer | private |
| m_controller | gem5::ruby::RubyPort | protected |
| m_coreId | gem5::ruby::Sequencer | private |
| m_data_cache_hit_latency | gem5::ruby::Sequencer | private |
| m_dataCache_ptr | gem5::ruby::Sequencer | private |
| m_deadlock_check_scheduled | gem5::ruby::Sequencer | private |
| m_deadlock_threshold | gem5::ruby::Sequencer | protected |
| m_FirstResponseToCompletionDelayHist | gem5::ruby::Sequencer | private |
| m_ForwardToFirstResponseDelayHist | gem5::ruby::Sequencer | private |
| m_hitLatencyHist | gem5::ruby::Sequencer | private |
| m_hitMachLatencyHist | gem5::ruby::Sequencer | private |
| m_hitTypeLatencyHist | gem5::ruby::Sequencer | private |
| m_hitTypeMachLatencyHist | gem5::ruby::Sequencer | private |
| m_htm_transaction_abort_cause | gem5::ruby::HTMSequencer | private |
| m_htm_transaction_cycles | gem5::ruby::HTMSequencer | private |
| m_htm_transaction_instructions | gem5::ruby::HTMSequencer | private |
| m_htmCmdRequestTable | gem5::ruby::HTMSequencer | private |
| m_htmstart_instruction | gem5::ruby::HTMSequencer | private |
| m_htmstart_tick | gem5::ruby::HTMSequencer | private |
| m_IncompleteTimes | gem5::ruby::Sequencer | private |
| m_InitialToForwardDelayHist | gem5::ruby::Sequencer | private |
| m_inst_cache_hit_latency | gem5::ruby::Sequencer | private |
| m_isCPUSequencer | gem5::ruby::RubyPort | private |
| m_IssueToInitialDelayHist | gem5::ruby::Sequencer | private |
| m_latencyHist | gem5::ruby::Sequencer | private |
| m_mandatory_q_ptr | gem5::ruby::RubyPort | protected |
| m_max_outstanding_requests | gem5::ruby::Sequencer | private |
| m_missLatencyHist | gem5::ruby::Sequencer | private |
| m_missMachLatencyHist | gem5::ruby::Sequencer | private |
| m_missTypeLatencyHist | gem5::ruby::Sequencer | private |
| m_missTypeMachLatencyHist | gem5::ruby::Sequencer | private |
| m_num_pending_invs | gem5::ruby::Sequencer | private |
| m_outstanding_count | gem5::ruby::Sequencer | private |
| m_outstandReqHist | gem5::ruby::Sequencer | private |
| m_RequestTable | gem5::ruby::Sequencer | protected |
| m_ruby_system | gem5::ruby::RubyPort | protected |
| m_runningGarnetStandalone | gem5::ruby::Sequencer | private |
| m_typeLatencyHist | gem5::ruby::Sequencer | private |
| m_UnaddressedRequestTable | gem5::ruby::Sequencer | protected |
| m_unaddressedTransactionCnt | gem5::ruby::Sequencer | private |
| m_usingRubyTester | gem5::ruby::RubyPort | protected |
| m_version | gem5::ruby::RubyPort | protected |
| makeRequest(PacketPtr pkt) override | gem5::ruby::Sequencer | virtual |
| markRemoved() | gem5::ruby::Sequencer | |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memRequestPort | gem5::ruby::RubyPort | private |
| memResponsePort | gem5::ruby::RubyPort | private |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| nextCycle() const | gem5::Clocked | inline |
| notifyFork() | gem5::Drainable | inlinevirtual |
| onRetryList(MemResponsePort *port) | gem5::ruby::RubyPort | inlineprivate |
| operator=(const HTMSequencer &obj) | gem5::ruby::HTMSequencer | private |
| gem5::ruby::RubyPort::operator=(const Group &)=delete | gem5::statistics::Group | |
| gem5::ruby::RubyPort::operator=(Clocked &)=delete | gem5::Clocked | protected |
| outstandingCount() const override | gem5::ruby::Sequencer | inlinevirtual |
| Params typedef | gem5::ruby::Sequencer | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| pioRequestPort | gem5::ruby::RubyPort | private |
| pioResponsePort | gem5::ruby::RubyPort | private |
| powerState | gem5::ClockedObject | |
| preDumpStats() | gem5::statistics::Group | virtual |
| print(std::ostream &out) const override | gem5::ruby::HTMSequencer | virtual |
| probeManager | gem5::SimObject | private |
| readCallback(Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0)) | gem5::ruby::Sequencer | |
| recordMissLatency(SequencerRequest *srequest, bool llscSuccess, const MachineType respondingMach, bool isExternalHit, Cycles initialRequestTime, Cycles forwardRequestTime, Cycles firstResponseTime) | gem5::ruby::Sequencer | private |
| recordRequestType(SequencerRequestType requestType) | gem5::ruby::Sequencer | |
| recvTimingResp(PacketPtr pkt, PortID request_port_id) | gem5::ruby::RubyPort | protected |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() | gem5::SimObject | virtual |
| regStats() | gem5::statistics::Group | virtual |
| request_ports | gem5::ruby::RubyPort | private |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetClock() const | gem5::Clocked | inlineprotected |
| resetStats() override | gem5::ruby::Sequencer | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| response_ports | gem5::ruby::RubyPort | protected |
| retryList | gem5::ruby::RubyPort | private |
| ruby_eviction_callback(Addr address) | gem5::ruby::RubyPort | protected |
| ruby_hit_callback(PacketPtr pkt) | gem5::ruby::RubyPort | protected |
| ruby_stale_translation_callback(Addr txnId) | gem5::ruby::RubyPort | protected |
| ruby_unaddressed_callback(PacketPtr pkt) | gem5::ruby::RubyPort | protected |
| rubyHtmCallback(PacketPtr pkt, const HtmFailedInCacheReason fail_r) | gem5::ruby::HTMSequencer | private |
| RubyPort(const Params &p) | gem5::ruby::RubyPort | |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| Sequencer(const Params &) | gem5::ruby::Sequencer | |
| Sequencer(const Sequencer &obj) | gem5::ruby::Sequencer | private |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::ClockedObject | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setController(AbstractController *_cntrl) | gem5::ruby::RubyPort | inline |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| SimObjectList typedef | gem5::SimObject | private |
| simObjectList | gem5::SimObject | privatestatic |
| startup() | gem5::SimObject | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::statistics::Group | private |
| system | gem5::ruby::RubyPort | protected |
| testDrainComplete() | gem5::ruby::RubyPort | protected |
| tick | gem5::Clocked | mutableprivate |
| ticksToCycles(Tick t) const | gem5::Clocked | inline |
| trySendRetries() | gem5::ruby::RubyPort | protected |
| unaddressedCallback(Addr unaddressedReqId, RubyRequestType requestType, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0)) | gem5::ruby::Sequencer | |
| unserialize(CheckpointIn &cp) override | gem5::ClockedObject | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| update() const | gem5::Clocked | inlineprivate |
| updateClockPeriod() | gem5::Clocked | inline |
| voltage() const | gem5::Clocked | inline |
| wakeup() override | gem5::ruby::HTMSequencer | virtual |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| writeCallback(Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0), const bool noCoales=false) | gem5::ruby::Sequencer | |
| writeCallbackScFail(Addr address, DataBlock &data) | gem5::ruby::Sequencer | |
| writeUniqueCallback(Addr address, DataBlock &data) | gem5::ruby::Sequencer | inline |
| ~Clocked() | gem5::Clocked | inlineprotectedvirtual |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~HTMSequencer() | gem5::ruby::HTMSequencer | |
| ~Named()=default | gem5::Named | virtual |
| ~RubyPort() | gem5::ruby::RubyPort | inlinevirtual |
| ~Sequencer() | gem5::ruby::Sequencer | |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |