fvp_base_pwr_ctrl.hh

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/*
 * Copyright (c) 2020 ARM Limited
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 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
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#ifndef __DEV_ARM_FVP_BASE_PWR_CTRL_HH__
#define __DEV_ARM_FVP_BASE_PWR_CTRL_HH__
 
#include <unordered_map>
 
#include "base/bitunion.hh"
#include "dev/io_device.hh"
 
namespace gem5
{
 
class ArmSystem;
struct FVPBasePwrCtrlParams;
class ThreadContext;
 
class FVPBasePwrCtrl : public BasicPioDevice
{
  public:
    FVPBasePwrCtrl(const FVPBasePwrCtrlParams &params);
 
    void setStandByWfi(ThreadContext *const tc);
 
    void clearStandByWfi(ThreadContext *const tc);
 
    bool setWakeRequest(ThreadContext *const tc);
 
    void clearWakeRequest(ThreadContext *const tc);
 
    void startup() override;
 
  protected:
    Tick read(PacketPtr pkt) override;
    Tick write(PacketPtr pkt) override;
 
  private:
    BitUnion32(PwrStatus)
        Bitfield<30> l1;
        Bitfield<29> l0;
        Bitfield<28> wen;
        Bitfield<27> pc;
        Bitfield<26> pp;
        Bitfield<25,24> wk;
        Bitfield<1> pwfi;
        Bitfield<0> pwk;
    EndBitUnion(PwrStatus)
 
    enum Offset : Addr
    {
        PPOFFR = 0x00,
        PPONR  = 0x04,
        PCOFFR = 0x08,
        PWKUPR = 0x0c,
        PSYSR  = 0x10
    };
 
    struct Registers
    {
        uint32_t ppoffr;
        uint32_t pponr;
        uint32_t pcoffr;
        uint32_t pwkupr;
        uint32_t psysr;
    } regs;
 
    static constexpr uint32_t MPID_MSK = 0x00ffffff;
    enum { WK_COLD, WK_RESET, WK_PPONR, WK_GICWR };
 
    std::vector<PwrStatus> corePwrStatus;
 
    std::unordered_map<uint32_t, size_t> poweredCoresPerCluster;
 
    PwrStatus *getCorePwrStatus(ThreadContext *const tc);
 
    ThreadContext *getThreadContextByMPID(uint32_t mpid) const;
 
    void powerCoreOn(ThreadContext *const tc, PwrStatus *const pwrs);
 
    void powerCoreOff(ThreadContext *const tc, PwrStatus *const pwrs);
 
    void startCoreUp(ThreadContext *const tc);
 
    ArmSystem &system;
};
 
} // namespace gem5
 
#endif // __DEV_ARM_FVP_BASE_PWR_CTRL_HH__