gem5  v21.1.0.2
fvp_base_pwr_ctrl.hh
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37 
38 #ifndef __DEV_ARM_FVP_BASE_PWR_CTRL_HH__
39 #define __DEV_ARM_FVP_BASE_PWR_CTRL_HH__
40 
41 #include <unordered_map>
42 
43 #include "base/bitunion.hh"
44 #include "dev/io_device.hh"
45 
46 namespace gem5
47 {
48 
49 class ArmSystem;
50 struct FVPBasePwrCtrlParams;
51 class ThreadContext;
52 
59 {
60  public:
61  FVPBasePwrCtrl(const FVPBasePwrCtrlParams &params);
62 
69  void setStandByWfi(ThreadContext *const tc);
70 
77  void clearStandByWfi(ThreadContext *const tc);
78 
86  bool setWakeRequest(ThreadContext *const tc);
87 
92  void clearWakeRequest(ThreadContext *const tc);
93 
94  void startup() override;
95 
96  protected:
97  Tick read(PacketPtr pkt) override;
98  Tick write(PacketPtr pkt) override;
99 
100  private:
101  BitUnion32(PwrStatus)
102  Bitfield<30> l1;
103  Bitfield<29> l0;
104  Bitfield<28> wen;
105  Bitfield<27> pc;
106  Bitfield<26> pp;
107  Bitfield<25,24> wk;
108  Bitfield<1> pwfi;
109  Bitfield<0> pwk;
110  EndBitUnion(PwrStatus)
111 
112  enum Offset : Addr
113  {
114  PPOFFR = 0x00,
115  PPONR = 0x04,
116  PCOFFR = 0x08,
117  PWKUPR = 0x0c,
118  PSYSR = 0x10
119  };
120 
121  struct Registers
122  {
123  uint32_t ppoffr;
124  uint32_t pponr;
125  uint32_t pcoffr;
126  uint32_t pwkupr;
127  uint32_t psysr;
128  } regs;
129 
131  static constexpr uint32_t MPID_MSK = 0x00ffffff;
134 
140 
142  std::unordered_map<uint32_t, size_t> poweredCoresPerCluster;
143 
151  PwrStatus *getCorePwrStatus(ThreadContext *const tc);
152 
158  ThreadContext *getThreadContextByMPID(uint32_t mpid) const;
159 
166  void powerCoreOn(ThreadContext *const tc, PwrStatus *const pwrs);
167 
174  void powerCoreOff(ThreadContext *const tc, PwrStatus *const pwrs);
175 
182  void startCoreUp(ThreadContext *const tc);
183 
186 };
187 
188 } // namespace gem5
189 
190 #endif // __DEV_ARM_FVP_BASE_PWR_CTRL_HH__
io_device.hh
gem5::FVPBasePwrCtrl::powerCoreOn
void powerCoreOn(ThreadContext *const tc, PwrStatus *const pwrs)
Powers on a core.
Definition: fvp_base_pwr_ctrl.cc:271
gem5::FVPBasePwrCtrl::clearWakeRequest
void clearWakeRequest(ThreadContext *const tc)
Triggered by the GIC when GICR_WAKER.ProcessorSleep becomes 0.
Definition: fvp_base_pwr_ctrl.cc:115
gem5::FVPBasePwrCtrl::system
ArmSystem & system
Reference to the arm system.
Definition: fvp_base_pwr_ctrl.hh:185
gem5::FVPBasePwrCtrl::Registers
Definition: fvp_base_pwr_ctrl.hh:121
gem5::FVPBasePwrCtrl::Registers::pwkupr
uint32_t pwkupr
Definition: fvp_base_pwr_ctrl.hh:126
gem5::FVPBasePwrCtrl::Registers::pponr
uint32_t pponr
Definition: fvp_base_pwr_ctrl.hh:124
gem5::FVPBasePwrCtrl::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: fvp_base_pwr_ctrl.cc:64
gem5::FVPBasePwrCtrl::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: fvp_base_pwr_ctrl.cc:126
gem5::FVPBasePwrCtrl::WK_COLD
@ WK_COLD
Definition: fvp_base_pwr_ctrl.hh:133
std::vector< PwrStatus >
gem5::FVPBasePwrCtrl::BitUnion32
BitUnion32(PwrStatus) Bitfield< 30 > l1
gem5::FVPBasePwrCtrl::corePwrStatus
std::vector< PwrStatus > corePwrStatus
Per-core power status.
Definition: fvp_base_pwr_ctrl.hh:139
gem5::FVPBasePwrCtrl::setStandByWfi
void setStandByWfi(ThreadContext *const tc)
Triggered by the ISA when a WFI instruction is executed and (1) there are no pending interrupts and (...
Definition: fvp_base_pwr_ctrl.cc:74
gem5::FVPBasePwrCtrl::powerCoreOff
void powerCoreOff(ThreadContext *const tc, PwrStatus *const pwrs)
Powers off a core.
Definition: fvp_base_pwr_ctrl.cc:290
gem5::FVPBasePwrCtrl::setWakeRequest
bool setWakeRequest(ThreadContext *const tc)
Triggered by the GIC when GICR_WAKER.ProcessorSleep is 1 and there are pending interrupts for the cor...
Definition: fvp_base_pwr_ctrl.cc:98
gem5::FVPBasePwrCtrl::pp
Bitfield< 26 > pp
Definition: fvp_base_pwr_ctrl.hh:106
gem5::FVPBasePwrCtrl::pwfi
Bitfield< 1 > pwfi
Definition: fvp_base_pwr_ctrl.hh:108
gem5::FVPBasePwrCtrl::Registers::ppoffr
uint32_t ppoffr
Definition: fvp_base_pwr_ctrl.hh:123
gem5::FVPBasePwrCtrl::pc
Bitfield< 27 > pc
Definition: fvp_base_pwr_ctrl.hh:105
gem5::FVPBasePwrCtrl::Registers::pcoffr
uint32_t pcoffr
Definition: fvp_base_pwr_ctrl.hh:125
gem5::FVPBasePwrCtrl::wen
Bitfield< 28 > wen
Definition: fvp_base_pwr_ctrl.hh:104
gem5::FVPBasePwrCtrl::getCorePwrStatus
PwrStatus * getCorePwrStatus(ThreadContext *const tc)
Retrieves the power status of a certain core and resizes the entries if needed.
Definition: fvp_base_pwr_ctrl.cc:253
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
EndBitUnion
EndBitUnion(PciCommandRegister) union PCIConfig
Definition: pcireg.h:65
gem5::FVPBasePwrCtrl::regs
EndBitUnion(PwrStatus) enum Offset struct gem5::FVPBasePwrCtrl::Registers regs
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
bitunion.hh
gem5::FVPBasePwrCtrl::FVPBasePwrCtrl
FVPBasePwrCtrl(const FVPBasePwrCtrlParams &params)
Definition: fvp_base_pwr_ctrl.cc:53
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::FVPBasePwrCtrl::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: fvp_base_pwr_ctrl.cc:163
gem5::FVPBasePwrCtrl::WK_PPONR
@ WK_PPONR
Definition: fvp_base_pwr_ctrl.hh:133
gem5::FVPBasePwrCtrl::l0
Bitfield< 29 > l0
Definition: fvp_base_pwr_ctrl.hh:103
gem5::FVPBasePwrCtrl::wk
Bitfield< 25, 24 > wk
Definition: fvp_base_pwr_ctrl.hh:107
gem5::ArmSystem
Definition: system.hh:62
gem5::FVPBasePwrCtrl
Definition: fvp_base_pwr_ctrl.hh:58
gem5::FVPBasePwrCtrl::MPID_MSK
static constexpr uint32_t MPID_MSK
Mask for extracting the MPID from a 32-bit value.
Definition: fvp_base_pwr_ctrl.hh:131
gem5::FVPBasePwrCtrl::WK_GICWR
@ WK_GICWR
Definition: fvp_base_pwr_ctrl.hh:133
gem5::FVPBasePwrCtrl::getThreadContextByMPID
ThreadContext * getThreadContextByMPID(uint32_t mpid) const
Retrieves the thread context reference for a CPU core by MPID.
Definition: fvp_base_pwr_ctrl.cc:261
gem5::FVPBasePwrCtrl::Registers::psysr
uint32_t psysr
Definition: fvp_base_pwr_ctrl.hh:127
gem5::FVPBasePwrCtrl::startCoreUp
void startCoreUp(ThreadContext *const tc)
Starts a core up.
Definition: fvp_base_pwr_ctrl.cc:305
gem5::X86ISA::l1
Bitfield< 2 > l1
Definition: misc.hh:664
gem5::FVPBasePwrCtrl::clearStandByWfi
void clearStandByWfi(ThreadContext *const tc)
Triggered when an interrupt is posted to the core.
Definition: fvp_base_pwr_ctrl.cc:87
gem5::FVPBasePwrCtrl::poweredCoresPerCluster
std::unordered_map< uint32_t, size_t > poweredCoresPerCluster
Number of powered cores per cluster.
Definition: fvp_base_pwr_ctrl.hh:142
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BasicPioDevice
Definition: io_device.hh:147
gem5::FVPBasePwrCtrl::pwk
Bitfield< 0 > pwk
Definition: fvp_base_pwr_ctrl.hh:109
gem5::FVPBasePwrCtrl::WK_RESET
@ WK_RESET
Definition: fvp_base_pwr_ctrl.hh:133

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