gem5  v21.2.1.1
mmu.cc
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43 
44 #include "arch/generic/mmu.hh"
45 #include "arch/generic/tlb.hh"
46 #include "cpu/thread_context.hh"
47 #include "sim/system.hh"
48 
49 namespace gem5
50 {
51 
52 void
54 {
55  auto traverse_hierarchy = [this](BaseTLB *starter) {
56  for (BaseTLB *tlb = starter; tlb; tlb = tlb->nextLevel()) {
57  switch (tlb->type()) {
58  case TypeTLB::instruction:
59  if (instruction.find(tlb) == instruction.end())
60  instruction.insert(tlb);
61  break;
62  case TypeTLB::data:
63  if (data.find(tlb) == data.end())
64  data.insert(tlb);
65  break;
66  case TypeTLB::unified:
67  if (unified.find(tlb) == unified.end())
68  unified.insert(tlb);
69  break;
70  default:
71  panic("Invalid TLB type\n");
72  }
73  }
74  };
75 
76  traverse_hierarchy(itb);
77  traverse_hierarchy(dtb);
78 }
79 
80 void
82 {
83  for (auto tlb : instruction) {
84  tlb->flushAll();
85  }
86 
87  for (auto tlb : data) {
88  tlb->flushAll();
89  }
90 
91  for (auto tlb : unified) {
92  tlb->flushAll();
93  }
94 }
95 
96 void
98 {
99  itb->demapPage(vaddr, asn);
100  dtb->demapPage(vaddr, asn);
101 }
102 
103 Fault
106 {
107  return getTlb(mode)->translateAtomic(req, tc, mode);
108 }
109 
110 void
113 {
114  return getTlb(mode)->translateTiming(req, tc, translation, mode);
115 }
116 
117 Fault
120 {
121  return getTlb(mode)->translateFunctional(req, tc, mode);
122 }
123 
124 Fault
126  BaseMMU::Mode mode) const
127 {
128  return getTlb(mode)->finalizePhysical(req, tc, mode);
129 }
130 
132  Addr new_start, Addr new_size, ThreadContext *new_tc,
133  BaseMMU *new_mmu, BaseMMU::Mode new_mode, Request::Flags new_flags) :
134  TranslationGen(new_start, new_size), tc(new_tc), cid(tc->contextId()),
135  mmu(new_mmu), mode(new_mode), flags(new_flags),
136  pageBytes(page_bytes)
137 {}
138 
139 void
141 {
142  Addr next = roundUp(range.vaddr, pageBytes);
143  if (next == range.vaddr)
144  next += pageBytes;
145  range.size = std::min(range.size, next - range.vaddr);
146 
147  auto req = std::make_shared<Request>(
148  range.vaddr, range.size, flags, Request::funcRequestorId, 0, cid);
149 
150  range.fault = mmu->translateFunctional(req, tc, mode);
151 
152  if (range.fault == NoFault)
153  range.paddr = req->getPaddr();
154 }
155 
156 void
158 {
159  Port *old_itb_port = old_mmu->itb->getTableWalkerPort();
160  Port *old_dtb_port = old_mmu->dtb->getTableWalkerPort();
161  Port *new_itb_port = itb->getTableWalkerPort();
162  Port *new_dtb_port = dtb->getTableWalkerPort();
163 
164  // Move over any table walker ports if they exist
165  if (new_itb_port)
166  new_itb_port->takeOverFrom(old_itb_port);
167  if (new_dtb_port)
168  new_dtb_port->takeOverFrom(old_dtb_port);
169 
170  itb->takeOverFrom(old_mmu->itb);
171  dtb->takeOverFrom(old_mmu->dtb);
172 }
173 
174 } // namespace gem5
gem5::BaseMMU::getTlb
BaseTLB * getTlb(Mode mode) const
Definition: mmu.hh:95
gem5::ArmISA::tlb
Bitfield< 59, 56 > tlb
Definition: misc_types.hh:92
gem5::TranslationGen::Range::size
Addr size
Definition: translation_gen.hh:71
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
system.hh
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::BaseTLB::takeOverFrom
virtual void takeOverFrom(BaseTLB *otlb)=0
Take over from an old tlb context.
gem5::BaseMMU::dtb
BaseTLB * dtb
Definition: mmu.hh:158
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::BaseMMU::MMUTranslationGen::translate
void translate(Range &range) const override
Subclasses implement this function to complete TranslationGen.
Definition: mmu.cc:140
gem5::TranslationGen::Range::vaddr
Addr vaddr
Definition: translation_gen.hh:70
gem5::BaseTLB::finalizePhysical
virtual Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const =0
Do post-translation physical address finalization.
tlb.hh
gem5::TranslationGen::Range::paddr
Addr paddr
Definition: translation_gen.hh:73
gem5::BaseMMU::init
void init() override
Called at init time, this method is traversing the TLB hierarchy and pupulating the instruction/data/...
Definition: mmu.cc:53
gem5::Port::takeOverFrom
void takeOverFrom(Port *old)
A utility function to make it easier to swap out ports.
Definition: port.hh:137
gem5::Request::funcRequestorId
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
Definition: request.hh:262
gem5::TranslationGen::Range
This structure represents a single, contiguous translation, or carries information about whatever fau...
Definition: translation_gen.hh:68
gem5::BaseMMU
Definition: mmu.hh:53
gem5::BaseMMU::translateFunctional
virtual Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
Definition: mmu.cc:118
gem5::Flags< FlagsType >
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::TranslationGen::Range::fault
Fault fault
Definition: translation_gen.hh:74
gem5::BaseMMU::unified
std::set< BaseTLB * > unified
Definition: mmu.hh:183
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
mmu.hh
gem5::BaseTLB
Definition: tlb.hh:58
gem5::BaseMMU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: mmu.cc:97
gem5::BaseTLB::demapPage
virtual void demapPage(Addr vaddr, uint64_t asn)=0
gem5::BaseTLB::translateFunctional
virtual Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)
Definition: tlb.hh:78
gem5::BaseTLB::translateTiming
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode)=0
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::TranslationGen
TranslationGen is a base class for a generator object which returns information about address transla...
Definition: translation_gen.hh:60
gem5::BaseMMU::translateTiming
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode)
Definition: mmu.cc:111
gem5::BaseMMU::instruction
std::set< BaseTLB * > instruction
It is possible from the MMU to traverse the entire hierarchy of TLBs, starting from the DTB and ITB (...
Definition: mmu.hh:181
gem5::BaseTLB::translateAtomic
virtual Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)=0
gem5::BaseMMU::Translation
Definition: mmu.hh:58
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::roundUp
static constexpr T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:260
gem5::BaseMMU::flushAll
virtual void flushAll()
Definition: mmu.cc:81
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::BaseMMU::finalizePhysical
virtual Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, Mode mode) const
Definition: mmu.cc:125
gem5::BaseMMU::translateAtomic
virtual Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
Definition: mmu.cc:104
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::BaseMMU::MMUTranslationGen::MMUTranslationGen
MMUTranslationGen(Addr page_bytes, Addr new_start, Addr new_size, ThreadContext *new_tc, BaseMMU *new_mmu, BaseMMU::Mode new_mode, Request::Flags new_flags)
Definition: mmu.cc:131
gem5::BaseMMU::takeOverFrom
virtual void takeOverFrom(BaseMMU *old_mmu)
Definition: mmu.cc:157
gem5::BaseTLB::getTableWalkerPort
virtual Port * getTableWalkerPort()
Get the table walker port if present.
Definition: tlb.hh:121
thread_context.hh
gem5::BaseMMU::data
std::set< BaseTLB * > data
Definition: mmu.hh:182
gem5::BaseMMU::itb
BaseTLB * itb
Definition: mmu.hh:159
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74

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