gem5  v21.1.0.2
mmu.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2011-2012,2016-2017, 2019-2020 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
15  * Copyright (c) 2011 Regents of the University of California
16  * Copyright (c) 2013 Advanced Micro Devices, Inc.
17  * Copyright (c) 2013 Mark D. Hill and David A. Wood
18  * All rights reserved.
19  *
20  * Redistribution and use in source and binary forms, with or without
21  * modification, are permitted provided that the following conditions are
22  * met: redistributions of source code must retain the above copyright
23  * notice, this list of conditions and the following disclaimer;
24  * redistributions in binary form must reproduce the above copyright
25  * notice, this list of conditions and the following disclaimer in the
26  * documentation and/or other materials provided with the distribution;
27  * neither the name of the copyright holders nor the names of its
28  * contributors may be used to endorse or promote products derived from
29  * this software without specific prior written permission.
30  *
31  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42  */
43 
44 #include "arch/generic/mmu.hh"
45 #include "arch/generic/tlb.hh"
46 
47 namespace gem5
48 {
49 
50 void
52 {
53  dtb->flushAll();
54  itb->flushAll();
55 }
56 
57 void
59 {
60  itb->demapPage(vaddr, asn);
61  dtb->demapPage(vaddr, asn);
62 }
63 
64 Fault
67 {
68  return getTlb(mode)->translateAtomic(req, tc, mode);
69 }
70 
71 void
74 {
75  return getTlb(mode)->translateTiming(req, tc, translation, mode);
76 }
77 
78 Fault
81 {
82  return getTlb(mode)->translateFunctional(req, tc, mode);
83 }
84 
85 Fault
87  BaseMMU::Mode mode) const
88 {
89  return getTlb(mode)->finalizePhysical(req, tc, mode);
90 }
91 
92 void
94 {
95  Port *old_itb_port = old_mmu->itb->getTableWalkerPort();
96  Port *old_dtb_port = old_mmu->dtb->getTableWalkerPort();
97  Port *new_itb_port = itb->getTableWalkerPort();
98  Port *new_dtb_port = dtb->getTableWalkerPort();
99 
100  // Move over any table walker ports if they exist
101  if (new_itb_port)
102  new_itb_port->takeOverFrom(old_itb_port);
103  if (new_dtb_port)
104  new_dtb_port->takeOverFrom(old_dtb_port);
105 
106  itb->takeOverFrom(old_mmu->itb);
107  dtb->takeOverFrom(old_mmu->dtb);
108 }
109 
110 } // namespace gem5
gem5::BaseMMU::getTlb
BaseTLB * getTlb(Mode mode) const
Definition: mmu.hh:92
gem5::BaseTLB::takeOverFrom
virtual void takeOverFrom(BaseTLB *otlb)=0
Take over from an old tlb context.
gem5::BaseMMU::dtb
BaseTLB * dtb
Definition: mmu.hh:120
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::BaseTLB::finalizePhysical
virtual Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const =0
Do post-translation physical address finalization.
tlb.hh
gem5::Port::takeOverFrom
void takeOverFrom(Port *old)
A utility function to make it easier to swap out ports.
Definition: port.hh:137
gem5::BaseMMU
Definition: mmu.hh:50
gem5::BaseMMU::translateFunctional
Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
Definition: mmu.cc:79
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
mmu.hh
gem5::BaseMMU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: mmu.cc:58
gem5::BaseTLB::demapPage
virtual void demapPage(Addr vaddr, uint64_t asn)=0
gem5::BaseTLB::translateFunctional
virtual Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)
Definition: tlb.hh:68
gem5::BaseTLB::translateTiming
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode)=0
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::BaseMMU::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode)
Definition: mmu.cc:72
gem5::BaseTLB::translateAtomic
virtual Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)=0
gem5::BaseMMU::Translation
Definition: mmu.hh:55
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::BaseMMU::flushAll
virtual void flushAll()
Definition: mmu.cc:51
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::BaseMMU::finalizePhysical
Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, Mode mode) const
Definition: mmu.cc:86
gem5::BaseMMU::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
Definition: mmu.cc:65
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BaseMMU::takeOverFrom
virtual void takeOverFrom(BaseMMU *old_mmu)
Definition: mmu.cc:93
gem5::BaseTLB::getTableWalkerPort
virtual Port * getTableWalkerPort()
Get the table walker port if present.
Definition: tlb.hh:111
gem5::BaseMMU::itb
BaseTLB * itb
Definition: mmu.hh:121
gem5::BaseTLB::flushAll
virtual void flushAll()=0
Remove all entries from the TLB.
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73

Generated on Tue Sep 21 2021 12:24:37 for gem5 by doxygen 1.8.17