gem5  v21.1.0.2
hmc_controller.cc
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1 #include "mem/hmc_controller.hh"
2 
3 #include "base/random.hh"
4 #include "base/trace.hh"
5 #include "debug/HMCController.hh"
6 
7 namespace gem5
8 {
9 
10 HMCController::HMCController(const HMCControllerParams &p) :
12  numMemSidePorts(p.port_mem_side_ports_connection_count),
13  rr_counter(0)
14 {
15  assert(p.port_cpu_side_ports_connection_count == 1);
16 }
17 
18 // Since this module is a load distributor, all its request ports have the same
19 // range so we should keep only one of the ranges and ignore the others
20 void HMCController::recvRangeChange(PortID mem_side_port_id)
21 {
22  if (mem_side_port_id == 0)
23  {
24  gotAllAddrRanges = true;
25  BaseXBar::recvRangeChange(mem_side_port_id);
26  }
27  else
28  gotAddrRanges[mem_side_port_id] = true;
29 }
30 
32 {
33  int current_value = rr_counter;
34  rr_counter++;
36  rr_counter = 0;
37  return current_value;
38 }
39 
40 bool HMCController::recvTimingReq(PacketPtr pkt, PortID cpu_side_port_id)
41 {
42  // determine the source port based on the id
43  ResponsePort *src_port = cpuSidePorts[cpu_side_port_id];
44 
45  // we should never see express snoops on a non-coherent component
46  assert(!pkt->isExpressSnoop());
47 
48  // For now, this is a simple round robin counter, for distribution the
49  // load among the serial links
50  PortID mem_side_port_id = rotate_counter();
51 
52  // test if the layer should be considered occupied for the current
53  // port
54  if (!reqLayers[mem_side_port_id]->tryTiming(src_port)) {
55  DPRINTF(HMCController, "recvTimingReq: src %s %s 0x%x BUSY\n",
56  src_port->name(), pkt->cmdString(), pkt->getAddr());
57  return false;
58  }
59 
60  DPRINTF(HMCController, "recvTimingReq: src %s %s 0x%x\n",
61  src_port->name(), pkt->cmdString(), pkt->getAddr());
62 
63  // store size and command as they might be modified when
64  // forwarding the packet
65  unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
66  unsigned int pkt_cmd = pkt->cmdToIndex();
67 
68  // store the old header delay so we can restore it if needed
69  Tick old_header_delay = pkt->headerDelay;
70 
71  // a request sees the frontend and forward latency
72  Tick xbar_delay = (frontendLatency + forwardLatency) * clockPeriod();
73 
74  // set the packet header and payload delay
75  calcPacketTiming(pkt, xbar_delay);
76 
77  // determine how long to be layer is busy
78  Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
79 
80  // before forwarding the packet (and possibly altering it),
81  // remember if we are expecting a response
82  const bool expect_response = pkt->needsResponse() &&
83  !pkt->cacheResponding();
84 
85  // since it is a normal request, attempt to send the packet
86  bool success = memSidePorts[mem_side_port_id]->sendTimingReq(pkt);
87 
88  if (!success) {
89  DPRINTF(HMCController, "recvTimingReq: src %s %s 0x%x RETRY\n",
90  src_port->name(), pkt->cmdString(), pkt->getAddr());
91 
92  // restore the header delay as it is additive
93  pkt->headerDelay = old_header_delay;
94 
95  // occupy until the header is sent
96  reqLayers[mem_side_port_id]->failedTiming(src_port,
97  clockEdge(Cycles(1)));
98 
99  return false;
100  }
101 
102  // remember where to route the response to
103  if (expect_response) {
104  assert(routeTo.find(pkt->req) == routeTo.end());
105  routeTo[pkt->req] = cpu_side_port_id;
106  }
107 
108  reqLayers[mem_side_port_id]->succeededTiming(packetFinishTime);
109 
110  // stats updates
111  pktCount[cpu_side_port_id][mem_side_port_id]++;
112  pktSize[cpu_side_port_id][mem_side_port_id] += pkt_size;
113  transDist[pkt_cmd]++;
114 
115  return true;
116 }
117 
118 } // namespace gem5
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::Packet::cmdString
const std::string & cmdString() const
Return the string name of the cmd field (for debugging and tracing).
Definition: packet.hh:577
hmc_controller.hh
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
gem5::BaseXBar::cpuSidePorts
std::vector< QueuedResponsePort * > cpuSidePorts
The memory-side ports and CPU-side ports of the crossbar.
Definition: xbar.hh:379
gem5::HMCController::rr_counter
int rr_counter
Definition: hmc_controller.hh:96
gem5::BaseXBar::frontendLatency
const Cycles frontendLatency
Cycles of front-end pipeline including the delay to accept the request and to decode the address.
Definition: xbar.hh:311
gem5::NoncoherentXBar
A non-coherent crossbar connects a number of non-snooping memory-side ports and cpu_sides,...
Definition: noncoherent_xbar.hh:68
gem5::BaseXBar::routeTo
std::unordered_map< RequestPtr, PortID > routeTo
Remember where request packets came from so that we can route responses to the appropriate port.
Definition: xbar.hh:327
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::NoncoherentXBar::reqLayers
std::vector< ReqLayer * > reqLayers
Declare the layers of this crossbar, one vector for requests and one for responses.
Definition: noncoherent_xbar.hh:77
gem5::HMCController::rotate_counter
int rotate_counter()
Function for rotating the round robin counter.
Definition: hmc_controller.cc:31
random.hh
gem5::BaseXBar::pktCount
statistics::Vector2d pktCount
Definition: xbar.hh:403
gem5::Packet::cacheResponding
bool cacheResponding() const
Definition: packet.hh:646
gem5::Packet::headerDelay
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition: packet.hh:420
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::Packet::hasData
bool hasData() const
Definition: packet.hh:603
gem5::Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:438
gem5::BaseXBar::forwardLatency
const Cycles forwardLatency
Definition: xbar.hh:312
gem5::HMCController::HMCController
HMCController(const HMCControllerParams &p)
Definition: hmc_controller.cc:10
gem5::BaseXBar::transDist
statistics::Vector transDist
Stats for transaction distribution and data passing through the crossbar.
Definition: xbar.hh:402
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::HMCController
HMC Controller, in general, is responsible for translating the host protocol (AXI for example) to ser...
Definition: hmc_controller.hh:76
gem5::BaseXBar::recvRangeChange
virtual void recvRangeChange(PortID mem_side_port_id)
Function called by the port when the crossbar is recieving a range change.
Definition: xbar.cc:364
gem5::HMCController::recvTimingReq
virtual bool recvTimingReq(PacketPtr pkt, PortID cpu_side_port_id)
Definition: hmc_controller.cc:40
gem5::Packet::needsResponse
bool needsResponse() const
Definition: packet.hh:597
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::BaseXBar::gotAllAddrRanges
bool gotAllAddrRanges
Definition: xbar.hh:376
gem5::ResponsePort
A ResponsePort is a specialization of a port.
Definition: port.hh:268
gem5::BaseXBar::pktSize
statistics::Vector2d pktSize
Definition: xbar.hh:404
gem5::BaseXBar::calcPacketTiming
void calcPacketTiming(PacketPtr pkt, Tick header_delay)
Calculate the timing parameters for the packet.
Definition: xbar.cc:105
gem5::Packet::isExpressSnoop
bool isExpressSnoop() const
Definition: packet.hh:689
trace.hh
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::HMCController::recvRangeChange
virtual void recvRangeChange(PortID mem_side_port_id)
Function called by the port when the crossbar is recieving a range change.
Definition: hmc_controller.cc:20
gem5::Packet::cmdToIndex
int cmdToIndex() const
Return the index of this command.
Definition: packet.hh:580
gem5::HMCController::numMemSidePorts
int numMemSidePorts
Definition: hmc_controller.hh:93
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::BaseXBar::gotAddrRanges
std::vector< bool > gotAddrRanges
Remember for each of the memory-side ports of the crossbar if we got an address range from the connec...
Definition: xbar.hh:375
gem5::Clocked::clockPeriod
Tick clockPeriod() const
Definition: clocked_object.hh:217
gem5::BaseXBar::memSidePorts
std::vector< RequestPort * > memSidePorts
Definition: xbar.hh:380

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