inteltrace.cc

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/*
 * Copyright (c) 2001-2005 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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#include "cpu/inteltrace.hh"
 
#include <iomanip>
 
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
 
namespace gem5
{
 
namespace trace {
 
void
IntelTraceRecord::dump()
{
    std::ostream &outs = trace::output();
    ccprintf(outs, "%7d ) ", when);
    outs << "0x" << std::hex << pc->instAddr() << ":\t";
    if (staticInst->isLoad()) {
        ccprintf(outs, "<RD %#x>", addr);
    } else if (staticInst->isStore()) {
        ccprintf(outs, "<WR %#x>", addr);
    }
    outs << std::endl;
}
 
} // namespace trace
} // namespace gem5