gem5  v21.1.0.2
dyn_inst.hh
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37 
46 #ifndef __CPU_MINOR_DYN_INST_HH__
47 #define __CPU_MINOR_DYN_INST_HH__
48 
49 #include <iostream>
50 
51 #include "arch/generic/isa.hh"
52 #include "base/named.hh"
53 #include "base/refcnt.hh"
54 #include "base/types.hh"
55 #include "cpu/inst_seq.hh"
56 #include "cpu/minor/buffers.hh"
57 #include "cpu/static_inst.hh"
58 #include "cpu/timing_expr.hh"
59 #include "sim/faults.hh"
60 #include "sim/insttracer.hh"
61 
62 namespace gem5
63 {
64 
66 namespace minor
67 {
68 
70 
73 
76 class InstId
77 {
78  public:
81  static const InstSeqNum firstStreamSeqNum = 1;
83  static const InstSeqNum firstLineSeqNum = 1;
84  static const InstSeqNum firstFetchSeqNum = 1;
85  static const InstSeqNum firstExecSeqNum = 1;
86 
87  public:
90 
95 
99 
103 
107 
112 
113  public:
116  ThreadID thread_id = 0, InstSeqNum stream_seq_num = 0,
117  InstSeqNum prediction_seq_num = 0, InstSeqNum line_seq_num = 0,
118  InstSeqNum fetch_seq_num = 0, InstSeqNum exec_seq_num = 0) :
119  threadId(thread_id), streamSeqNum(stream_seq_num),
120  predictionSeqNum(prediction_seq_num), lineSeqNum(line_seq_num),
121  fetchSeqNum(fetch_seq_num), execSeqNum(exec_seq_num)
122  { }
123 
124  public:
125  /* Equal if the thread and last set sequence number matches */
126  bool
127  operator== (const InstId &rhs)
128  {
129  /* If any of fetch and exec sequence number are not set
130  * they need to be 0, so a straight comparison is still
131  * fine */
132  bool ret = (threadId == rhs.threadId &&
133  lineSeqNum == rhs.lineSeqNum &&
134  fetchSeqNum == rhs.fetchSeqNum &&
135  execSeqNum == rhs.execSeqNum);
136 
137  /* Stream and prediction *must* match if these are the same id */
138  if (ret) {
139  assert(streamSeqNum == rhs.streamSeqNum &&
141  }
142 
143  return ret;
144  }
145 };
146 
149 std::ostream &operator <<(std::ostream &os, const InstId &id);
150 
151 class MinorDynInst;
152 
157 std::ostream &operator <<(std::ostream &os, const MinorDynInst &inst);
158 
163 class MinorDynInst : public RefCounted
164 {
165  private:
169 
170  public:
172 
174 
177 
180 
183 
187 
191 
194 
198  unsigned int fuIndex;
199 
201  bool inLSQ;
202 
205 
208 
213 
215  bool predicate;
216 
220 
226 
230 
234 
239 
240  public:
242  staticInst(si), id(id_), traceData(NULL),
243  pc(TheISA::PCState(0)), fault(fault_),
244  triedToPredict(false), predictedTaken(false),
245  fuIndex(0), inLSQ(false), translationFault(NoFault),
246  inStoreBuffer(false), canEarlyIssue(false), predicate(true),
249  flatDestRegIdx(si ? si->numDestRegs() : 0)
250  { }
251 
252  public:
254  bool isBubble() const { return id.fetchSeqNum == 0; }
255 
257  static MinorDynInstPtr bubble() { return bubbleInst; }
258 
260  bool isFault() const { return fault != NoFault; }
261 
263  bool isInst() const { return !isBubble() && !isFault(); }
264 
266  bool isMemRef() const { return isInst() && staticInst->isMemRef(); }
267 
270  bool isNoCostInst() const;
271 
274  bool isLastOpInInst() const;
275 
277  static void init();
278 
281  void minorTraceInst(const Named &named_object,
282  const BaseISA::RegClasses &reg_classes) const;
283 
285  void reportData(std::ostream &os) const;
286 
287  bool readPredicate() const { return predicate; }
288 
289  void setPredicate(bool val) { predicate = val; }
290 
291  bool readMemAccPredicate() const { return memAccPredicate; }
292 
294 
295  ~MinorDynInst();
296 };
297 
299 std::ostream &operator <<(std::ostream &os, const MinorDynInst &inst);
300 
301 } // namespace minor
302 } // namespace gem5
303 
304 #endif /* __CPU_MINOR_DYN_INST_HH__ */
gem5::minor::MinorDynInst::~MinorDynInst
~MinorDynInst()
Definition: dyn_inst.cc:242
refcnt.hh
gem5::minor::InstId::firstPredictionSeqNum
static const InstSeqNum firstPredictionSeqNum
Definition: dyn_inst.hh:82
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::minor::InstId::fetchSeqNum
InstSeqNum fetchSeqNum
Fetch sequence number.
Definition: dyn_inst.hh:106
gem5::minor::InstId
Id for lines and instructions.
Definition: dyn_inst.hh:76
gem5::minor::MinorDynInst::canEarlyIssue
bool canEarlyIssue
Can this instruction be executed out of order.
Definition: dyn_inst.hh:212
gem5::minor::MinorDynInst::flatDestRegIdx
std::vector< RegId > flatDestRegIdx
Flat register indices so that, when clearing the scoreboard, we have the same register indices as whe...
Definition: dyn_inst.hh:238
insttracer.hh
gem5::minor::MinorDynInst::staticInst
const StaticInstPtr staticInst
Definition: dyn_inst.hh:171
named.hh
timing_expr.hh
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
minor
gem5::minor::MinorDynInst::bubbleInst
static MinorDynInstPtr bubbleInst
A prototypical bubble instruction.
Definition: dyn_inst.hh:168
gem5::minor::MinorDynInst::setPredicate
void setPredicate(bool val)
Definition: dyn_inst.hh:289
gem5::minor::MinorDynInst::readMemAccPredicate
bool readMemAccPredicate() const
Definition: dyn_inst.hh:291
gem5::minor::MinorDynInst::minorTraceInst
void minorTraceInst(const Named &named_object, const BaseISA::RegClasses &reg_classes) const
Print (possibly verbose) instruction information for MinorTrace using the given Named object's name.
Definition: dyn_inst.cc:185
std::vector
STL vector class.
Definition: stl.hh:37
gem5::minor::MinorDynInst::translationFault
Fault translationFault
Translation fault in case of a mem ref.
Definition: dyn_inst.hh:204
gem5::minor::MinorDynInst::fuIndex
unsigned int fuIndex
Fields only set during execution.
Definition: dyn_inst.hh:198
gem5::minor::MinorDynInst::setMemAccPredicate
void setMemAccPredicate(bool val)
Definition: dyn_inst.hh:293
gem5::minor::MinorDynInst::extraCommitDelay
Cycles extraCommitDelay
Extra delay at the end of the pipeline.
Definition: dyn_inst.hh:228
gem5::minor::MinorDynInst::init
static void init()
Initialise the class.
Definition: dyn_inst.cc:83
gem5::minor::MinorDynInst::triedToPredict
bool triedToPredict
Tried to predict the destination of this inst (if a control instruction or a sys call)
Definition: dyn_inst.hh:186
gem5::minor::InstId::firstFetchSeqNum
static const InstSeqNum firstFetchSeqNum
Definition: dyn_inst.hh:84
gem5::minor::MinorDynInst::predictedTarget
TheISA::PCState predictedTarget
Predicted branch target.
Definition: dyn_inst.hh:193
faults.hh
gem5::minor::MinorDynInstPtr
RefCountingPtr< MinorDynInst > MinorDynInstPtr
MinorDynInsts are currently reference counted.
Definition: dyn_inst.hh:69
gem5::minor::MinorDynInst::isMemRef
bool isMemRef() const
Is this a real mem ref instruction.
Definition: dyn_inst.hh:266
gem5::minor::InstId::firstStreamSeqNum
static const InstSeqNum firstStreamSeqNum
First sequence numbers to use in initialisation of the pipeline and to be expected on the first line/...
Definition: dyn_inst.hh:81
gem5::minor::MinorDynInst::memAccPredicate
bool memAccPredicate
Flag controlling conditional execution of the memory access associated with the instruction (only mea...
Definition: dyn_inst.hh:219
gem5::minor::MinorDynInst::MinorDynInst
MinorDynInst(StaticInstPtr si, InstId id_=InstId(), Fault fault_=NoFault)
Definition: dyn_inst.hh:241
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::minor::InstId::firstLineSeqNum
static const InstSeqNum firstLineSeqNum
Definition: dyn_inst.hh:83
gem5::minor::MinorDynInst::readPredicate
bool readPredicate() const
Definition: dyn_inst.hh:287
gem5::RefCountingPtr< MinorDynInst >
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::Named
Interface for things with names.
Definition: named.hh:38
gem5::minor::MinorDynInst::minimumCommitCycle
Cycles minimumCommitCycle
Once issued, extraCommitDelay becomes minimumCommitCycle to account for delay in absolute time.
Definition: dyn_inst.hh:233
gem5::minor::MinorDynInst::predictedTaken
bool predictedTaken
This instruction was predicted to change control flow and the following instructions will have a newe...
Definition: dyn_inst.hh:190
gem5::minor::InstId::operator==
bool operator==(const InstId &rhs)
Definition: dyn_inst.hh:127
inst_seq.hh
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::TimingExpr
Definition: timing_expr.hh:91
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::minor::InstId::streamSeqNum
InstSeqNum streamSeqNum
The 'stream' this instruction belongs to.
Definition: dyn_inst.hh:94
gem5::minor::MinorDynInst::bubble
static MinorDynInstPtr bubble()
There is a single bubble inst.
Definition: dyn_inst.hh:257
static_inst.hh
gem5::minor::InstId::firstExecSeqNum
static const InstSeqNum firstExecSeqNum
Definition: dyn_inst.hh:85
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:772
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::StaticInst::isMemRef
bool isMemRef() const
Definition: static_inst.hh:165
gem5::minor::MinorDynInst::inLSQ
bool inLSQ
This instruction is in the LSQ, not a functional unit.
Definition: dyn_inst.hh:201
gem5::minor::MinorDynInst::isInst
bool isInst() const
Is this a real instruction.
Definition: dyn_inst.hh:263
gem5::minor::InstId::InstId
InstId(ThreadID thread_id=0, InstSeqNum stream_seq_num=0, InstSeqNum prediction_seq_num=0, InstSeqNum line_seq_num=0, InstSeqNum fetch_seq_num=0, InstSeqNum exec_seq_num=0)
Very boring default constructor.
Definition: dyn_inst.hh:115
gem5::minor::MinorDynInst::fault
Fault fault
This is actually a fault masquerading as an instruction.
Definition: dyn_inst.hh:182
gem5::minor::MinorDynInst::extraCommitDelayExpr
TimingExpr * extraCommitDelayExpr
Definition: dyn_inst.hh:229
gem5::minor::MinorDynInst::isBubble
bool isBubble() const
The BubbleIF interface.
Definition: dyn_inst.hh:254
gem5::RefCounted
Derive from RefCounted if you want to enable reference counting of this class.
Definition: refcnt.hh:60
isa.hh
gem5::minor::MinorDynInst::isFault
bool isFault() const
Is this a fault rather than instruction.
Definition: dyn_inst.hh:260
gem5::minor::InstId::lineSeqNum
InstSeqNum lineSeqNum
Line sequence number.
Definition: dyn_inst.hh:102
gem5::minor::MinorDynInst::id
InstId id
Definition: dyn_inst.hh:173
gem5::minor::MinorDynInst
Dynamic instruction for Minor.
Definition: dyn_inst.hh:163
types.hh
gem5::minor::MinorDynInst::reportData
void reportData(std::ostream &os) const
ReportIF interface.
Definition: dyn_inst.cc:107
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::minor::operator<<
std::ostream & operator<<(std::ostream &os, const InstId &id)
Print this id in the usual slash-separated format expected by MinorTrace.
Definition: dyn_inst.cc:65
gem5::minor::MinorDynInst::isNoCostInst
bool isNoCostInst() const
Is this an instruction that can be executed ‘for free’ and needn't spend time in an FU.
Definition: dyn_inst.cc:101
gem5::minor::MinorDynInst::pc
TheISA::PCState pc
The fetch address of this instruction.
Definition: dyn_inst.hh:179
gem5::minor::MinorDynInst::isLastOpInInst
bool isLastOpInInst() const
Assuming this is not a fault, is this instruction either a whole instruction or the last microop from...
Definition: dyn_inst.cc:94
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::minor::MinorDynInst::predicate
bool predicate
Flag controlling conditional execution of the instruction.
Definition: dyn_inst.hh:215
gem5::minor::InstId::execSeqNum
InstSeqNum execSeqNum
'Execute' sequence number.
Definition: dyn_inst.hh:111
buffers.hh
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::minor::InstId::predictionSeqNum
InstSeqNum predictionSeqNum
The predicted qualifier to stream, attached by Fetch2 as a consequence of branch prediction.
Definition: dyn_inst.hh:98
gem5::minor::MinorDynInst::traceData
Trace::InstRecord * traceData
Trace information for this instruction's execution.
Definition: dyn_inst.hh:176
gem5::minor::MinorDynInst::instToWaitFor
InstSeqNum instToWaitFor
execSeqNum of the latest inst on which this inst depends.
Definition: dyn_inst.hh:225
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::minor::InstId::threadId
ThreadID threadId
The thread to which this line/instruction belongs.
Definition: dyn_inst.hh:89
gem5::minor::MinorDynInst::inStoreBuffer
bool inStoreBuffer
The instruction has been sent to the store buffer.
Definition: dyn_inst.hh:207

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