dyn_inst.hh

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/*
 * Copyright (c) 2013-2014,2018 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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#ifndef __CPU_MINOR_DYN_INST_HH__
#define __CPU_MINOR_DYN_INST_HH__
 
#include <iostream>
 
#include "arch/generic/isa.hh"
#include "base/named.hh"
#include "base/refcnt.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "cpu/minor/buffers.hh"
#include "cpu/static_inst.hh"
#include "cpu/timing_expr.hh"
#include "sim/faults.hh"
#include "sim/insttracer.hh"
 
namespace gem5
{
 
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
 
class MinorDynInst;
 
typedef RefCountingPtr<MinorDynInst> MinorDynInstPtr;
 
class InstId
{
  public:
    static const InstSeqNum firstStreamSeqNum = 1;
    static const InstSeqNum firstPredictionSeqNum = 1;
    static const InstSeqNum firstLineSeqNum = 1;
    static const InstSeqNum firstFetchSeqNum = 1;
    static const InstSeqNum firstExecSeqNum = 1;
 
  public:
    ThreadID threadId;
 
    InstSeqNum streamSeqNum;
 
    InstSeqNum predictionSeqNum;
 
    InstSeqNum lineSeqNum;
 
    InstSeqNum fetchSeqNum;
 
    InstSeqNum execSeqNum;
 
  public:
    InstId(
        ThreadID thread_id = 0, InstSeqNum stream_seq_num = 0,
        InstSeqNum prediction_seq_num = 0, InstSeqNum line_seq_num = 0,
        InstSeqNum fetch_seq_num = 0, InstSeqNum exec_seq_num = 0) :
        threadId(thread_id), streamSeqNum(stream_seq_num),
        predictionSeqNum(prediction_seq_num), lineSeqNum(line_seq_num),
        fetchSeqNum(fetch_seq_num), execSeqNum(exec_seq_num)
    { }
 
  public:
    /* Equal if the thread and last set sequence number matches */
    bool
    operator== (const InstId &rhs)
    {
        /* If any of fetch and exec sequence number are not set
         *  they need to be 0, so a straight comparison is still
         *  fine */
        bool ret = (threadId == rhs.threadId &&
            lineSeqNum == rhs.lineSeqNum &&
            fetchSeqNum == rhs.fetchSeqNum &&
            execSeqNum == rhs.execSeqNum);
 
        /* Stream and prediction *must* match if these are the same id */
        if (ret) {
            assert(streamSeqNum == rhs.streamSeqNum &&
                predictionSeqNum == rhs.predictionSeqNum);
        }
 
        return ret;
    }
};
 
std::ostream &operator <<(std::ostream &os, const InstId &id);
 
class MinorDynInst;
 
std::ostream &operator <<(std::ostream &os, const MinorDynInst &inst);
 
class MinorDynInst : public RefCounted
{
  private:
    static MinorDynInstPtr bubbleInst;
 
  public:
    const StaticInstPtr staticInst;
 
    InstId id;
 
    trace::InstRecord *traceData = nullptr;
 
    std::unique_ptr<PCStateBase> pc;
 
    Fault fault;
 
    bool triedToPredict = false;
 
    bool predictedTaken = false;
 
    std::unique_ptr<PCStateBase> predictedTarget;
 
    unsigned int fuIndex = 0;
 
    bool inLSQ = false;
 
    Fault translationFault;
 
    bool inStoreBuffer = false;
 
    bool canEarlyIssue = false;
 
    bool predicate = true;
 
    bool memAccPredicate = true;
 
    InstSeqNum instToWaitFor = 0;
 
    Cycles extraCommitDelay{0};
    TimingExpr *extraCommitDelayExpr = nullptr;
 
    Cycles minimumCommitCycle{0};
 
    std::vector<RegId> flatDestRegIdx;
 
  public:
    MinorDynInst(StaticInstPtr si, InstId id_=InstId(), Fault fault_=NoFault) :
        staticInst(si), id(id_), fault(fault_), translationFault(NoFault),
        flatDestRegIdx(si ? si->numDestRegs() : 0)
    { }
 
  public:
    bool isBubble() const { return id.fetchSeqNum == 0; }
 
    static MinorDynInstPtr bubble() { return bubbleInst; }
 
    bool isFault() const { return fault != NoFault; }
 
    bool isInst() const { return !isBubble() && !isFault(); }
 
    bool isMemRef() const { return isInst() && staticInst->isMemRef(); }
 
    bool isNoCostInst() const;
 
    bool isLastOpInInst() const;
 
    void minorTraceInst(const Named &named_object) const;
 
    void reportData(std::ostream &os) const;
 
    bool readPredicate() const { return predicate; }
 
    void setPredicate(bool val) { predicate = val; }
 
    bool readMemAccPredicate() const { return memAccPredicate; }
 
    void setMemAccPredicate(bool val) { memAccPredicate = val; }
 
    ~MinorDynInst();
};
 
std::ostream &operator <<(std::ostream &os, const MinorDynInst &inst);
 
} // namespace minor
} // namespace gem5
 
#endif /* __CPU_MINOR_DYN_INST_HH__ */