gem5  v21.1.0.2
dyn_inst.cc
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37 
38 #include "cpu/minor/dyn_inst.hh"
39 
40 #include <iomanip>
41 #include <sstream>
42 
43 #include "arch/isa.hh"
44 #include "cpu/base.hh"
45 #include "cpu/minor/trace.hh"
46 #include "cpu/null_static_inst.hh"
47 #include "cpu/reg_class.hh"
48 #include "debug/MinorExecute.hh"
49 #include "enums/OpClass.hh"
50 
51 namespace gem5
52 {
53 
55 namespace minor
56 {
57 
63 
64 std::ostream &
65 operator <<(std::ostream &os, const InstId &id)
66 {
67  os << id.threadId << '/' << id.streamSeqNum << '.'
68  << id.predictionSeqNum << '/' << id.lineSeqNum;
69 
70  /* Not all structures have fetch and exec sequence numbers */
71  if (id.fetchSeqNum != 0) {
72  os << '/' << id.fetchSeqNum;
73  if (id.execSeqNum != 0)
74  os << '.' << id.execSeqNum;
75  }
76 
77  return os;
78 }
79 
81 
82 void
84 {
85  if (!bubbleInst) {
87  assert(bubbleInst->isBubble());
88  /* Make bubbleInst immortal */
89  bubbleInst->incref();
90  }
91 }
92 
93 bool
95 {
96  assert(staticInst);
97  return !(staticInst->isMicroop() && !staticInst->isLastMicroop());
98 }
99 
100 bool
102 {
103  return isInst() && staticInst->opClass() == No_OpClass;
104 }
105 
106 void
107 MinorDynInst::reportData(std::ostream &os) const
108 {
109  if (isBubble())
110  os << "-";
111  else if (isFault())
112  os << "F;" << id;
113  else if (translationFault != NoFault)
114  os << "TF;" << id;
115  else
116  os << id;
117 }
118 
119 std::ostream &
120 operator <<(std::ostream &os, const MinorDynInst &inst)
121 {
122  os << inst.id << " pc: 0x"
123  << std::hex << inst.pc.instAddr() << std::dec << " (";
124 
125  if (inst.isFault())
126  os << "fault: \"" << inst.fault->name() << '"';
127  else if (inst.translationFault != NoFault)
128  os << "translation fault: \"" << inst.translationFault->name() << '"';
129  else if (inst.staticInst)
130  os << inst.staticInst->getName();
131  else
132  os << "bubble";
133 
134  os << ')';
135 
136  return os;
137 }
138 
141 static void
142 printRegName(std::ostream &os, const RegId& reg,
143  const BaseISA::RegClasses &reg_classes)
144 {
145  const auto &reg_class = reg_classes.at(reg.classValue());
146  switch (reg.classValue()) {
147  case MiscRegClass:
148  {
149  RegIndex misc_reg = reg.index();
150 
151  /* This is an ugly test because not all archs. have miscRegName */
152 #if THE_ISA == ARM_ISA
153  os << 'm' << misc_reg << '(' << TheISA::miscRegName[misc_reg] <<
154  ')';
155 #else
156  os << 'n' << misc_reg;
157 #endif
158  }
159  break;
160  case FloatRegClass:
161  os << 'f' << reg.index();
162  break;
163  case VecRegClass:
164  os << 'v' << reg.index();
165  break;
166  case VecElemClass:
167  os << 'v' << reg.index() << '[' << reg.elemIndex() << ']';
168  break;
169  case IntRegClass:
170  if (reg.index() == reg_class.zeroReg()) {
171  os << 'z';
172  } else {
173  os << 'r' << reg.index();
174  }
175  break;
176  case CCRegClass:
177  os << 'c' << reg.index();
178  break;
179  default:
180  panic("Unknown register class: %d", (int)reg.classValue());
181  }
182 }
183 
184 void
186  const BaseISA::RegClasses &reg_classes) const
187 {
188  if (isFault()) {
189  minorInst(named_object, "id=F;%s addr=0x%x fault=\"%s\"\n",
190  id, pc.instAddr(), fault->name());
191  } else {
192  unsigned int num_src_regs = staticInst->numSrcRegs();
193  unsigned int num_dest_regs = staticInst->numDestRegs();
194 
195  std::ostringstream regs_str;
196 
197  /* Format lists of src and dest registers for microops and
198  * 'full' instructions */
199  if (!staticInst->isMacroop()) {
200  regs_str << " srcRegs=";
201 
202  unsigned int src_reg = 0;
203  while (src_reg < num_src_regs) {
204  printRegName(regs_str, staticInst->srcRegIdx(src_reg),
205  reg_classes);
206 
207  src_reg++;
208  if (src_reg != num_src_regs)
209  regs_str << ',';
210  }
211 
212  regs_str << " destRegs=";
213 
214  unsigned int dest_reg = 0;
215  while (dest_reg < num_dest_regs) {
216  printRegName(regs_str, staticInst->destRegIdx(dest_reg),
217  reg_classes);
218 
219  dest_reg++;
220  if (dest_reg != num_dest_regs)
221  regs_str << ',';
222  }
223 
224  ccprintf(regs_str, " extMachInst=%160x", staticInst->getEMI());
225  }
226 
227  std::ostringstream flags;
228  staticInst->printFlags(flags, " ");
229 
230  minorInst(named_object, "id=%s addr=0x%x inst=\"%s\" class=%s"
231  " flags=\"%s\"%s%s\n",
232  id, pc.instAddr(),
233  (staticInst->opClass() == No_OpClass ?
234  "(invalid)" : staticInst->disassemble(0,NULL)),
235  enums::OpClassStrings[staticInst->opClass()],
236  flags.str(),
237  regs_str.str(),
238  (predictedTaken ? " predictedTaken" : ""));
239  }
240 }
241 
243 {
244  if (traceData)
245  delete traceData;
246 }
247 
248 } // namespace minor
249 } // namespace gem5
dyn_inst.hh
gem5::minor::MinorDynInst::~MinorDynInst
~MinorDynInst()
Definition: dyn_inst.cc:242
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:62
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
gem5::minor::InstId::firstPredictionSeqNum
static const InstSeqNum firstPredictionSeqNum
Definition: dyn_inst.hh:82
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:208
gem5::minor::minorInst
void minorInst(const Named &named, const char *fmt, Args ...args)
DPRINTFN for MinorTrace MinorInst line reporting.
Definition: trace.hh:75
gem5::minor::InstId
Id for lines and instructions.
Definition: dyn_inst.hh:76
gem5::minor::MinorDynInst::staticInst
const StaticInstPtr staticInst
Definition: dyn_inst.hh:171
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
minor
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
gem5::ArmISA::miscRegName
const char *const miscRegName[]
Definition: misc.hh:1172
gem5::minor::MinorDynInst::bubbleInst
static MinorDynInstPtr bubbleInst
A prototypical bubble instruction.
Definition: dyn_inst.hh:168
gem5::StaticInst::numSrcRegs
int8_t numSrcRegs() const
Number of source registers.
Definition: static_inst.hh:139
gem5::minor::MinorDynInst::minorTraceInst
void minorTraceInst(const Named &named_object, const BaseISA::RegClasses &reg_classes) const
Print (possibly verbose) instruction information for MinorTrace using the given Named object's name.
Definition: dyn_inst.cc:185
std::vector< RegClassInfo >
gem5::minor::printRegName
static void printRegName(std::ostream &os, const RegId &reg, const BaseISA::RegClasses &reg_classes)
Print a register in the form r<n>, f<n>, m<n>(<name>) for integer, float, and misc given an 'architec...
Definition: dyn_inst.cc:142
gem5::minor::MinorDynInst::translationFault
Fault translationFault
Translation fault in case of a mem ref.
Definition: dyn_inst.hh:204
gem5::minor::MinorDynInst::init
static void init()
Initialise the class.
Definition: dyn_inst.cc:83
gem5::minor::InstId::firstFetchSeqNum
static const InstSeqNum firstFetchSeqNum
Definition: dyn_inst.hh:84
gem5::minor::MinorDynInstPtr
RefCountingPtr< MinorDynInst > MinorDynInstPtr
MinorDynInsts are currently reference counted.
Definition: dyn_inst.hh:69
gem5::minor::InstId::firstStreamSeqNum
static const InstSeqNum firstStreamSeqNum
First sequence numbers to use in initialisation of the pipeline and to be expected on the first line/...
Definition: dyn_inst.hh:81
gem5::minor::MinorDynInst::MinorDynInst
MinorDynInst(StaticInstPtr si, InstId id_=InstId(), Fault fault_=NoFault)
Definition: dyn_inst.hh:241
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:237
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::minor::InstId::firstLineSeqNum
static const InstSeqNum firstLineSeqNum
Definition: dyn_inst.hh:83
gem5::Named
Interface for things with names.
Definition: named.hh:38
gem5::StaticInst::opClass
OpClass opClass() const
Operation class. Used to select appropriate function unit in issue.
Definition: static_inst.hh:232
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::minor::MinorDynInst::predictedTaken
bool predictedTaken
This instruction was predicted to change control flow and the following instructions will have a newe...
Definition: dyn_inst.hh:190
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:247
gem5::StaticInst::getName
std::string getName()
Return name of machine instruction.
Definition: static_inst.hh:378
gem5::minor::InstId::firstExecSeqNum
static const InstSeqNum firstExecSeqNum
Definition: dyn_inst.hh:85
null_static_inst.hh
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::StaticInst::isLastMicroop
bool isLastMicroop() const
Definition: static_inst.hh:210
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::minor::MinorDynInst::isInst
bool isInst() const
Is this a real instruction.
Definition: dyn_inst.hh:263
gem5::minor::MinorDynInst::fault
Fault fault
This is actually a fault masquerading as an instruction.
Definition: dyn_inst.hh:182
gem5::minor::MinorDynInst::isBubble
bool isBubble() const
The BubbleIF interface.
Definition: dyn_inst.hh:254
gem5::minor::MinorDynInst::isFault
bool isFault() const
Is this a fault rather than instruction.
Definition: dyn_inst.hh:260
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
gem5::StaticInst::getEMI
virtual uint64_t getEMI() const
Definition: static_inst.hh:258
gem5::StaticInst::disassemble
virtual const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:75
gem5::minor::MinorDynInst::id
InstId id
Definition: dyn_inst.hh:173
gem5::minor::MinorDynInst
Dynamic instruction for Minor.
Definition: dyn_inst.hh:163
base.hh
gem5::minor::MinorDynInst::reportData
void reportData(std::ostream &os) const
ReportIF interface.
Definition: dyn_inst.cc:107
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::minor::operator<<
std::ostream & operator<<(std::ostream &os, const InstId &id)
Print this id in the usual slash-separated format expected by MinorTrace.
Definition: dyn_inst.cc:65
gem5::minor::MinorDynInst::isNoCostInst
bool isNoCostInst() const
Is this an instruction that can be executed ‘for free’ and needn't spend time in an FU.
Definition: dyn_inst.cc:101
gem5::StaticInst::isMacroop
bool isMacroop() const
Definition: static_inst.hh:207
reg_class.hh
gem5::minor::MinorDynInst::pc
TheISA::PCState pc
The fetch address of this instruction.
Definition: dyn_inst.hh:179
gem5::StaticInst::numDestRegs
int8_t numDestRegs() const
Number of destination registers.
Definition: static_inst.hh:141
gem5::minor::MinorDynInst::isLastOpInInst
bool isLastOpInInst() const
Assuming this is not a fault, is this instruction either a whole instruction or the last microop from...
Definition: dyn_inst.cc:94
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
trace.hh
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::minor::MinorDynInst::traceData
Trace::InstRecord * traceData
Trace information for this instruction's execution.
Definition: dyn_inst.hh:176
gem5::StaticInst::printFlags
void printFlags(std::ostream &outs, const std::string &separator) const
Print a separator separated list of this instruction's set flag names on the given stream.
Definition: static_inst.cc:86
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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