gem5  v22.0.0.1
tlb.hh
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1 /*
2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
3  * Copyright (c) 2007 MIPS Technologies, Inc.
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29 
30 #ifndef __ARCH_MIPS_TLB_HH__
31 #define __ARCH_MIPS_TLB_HH__
32 
33 #include <map>
34 
35 #include "arch/generic/tlb.hh"
36 #include "arch/mips/pagetable.hh"
37 #include "arch/mips/utility.hh"
38 #include "base/statistics.hh"
39 #include "mem/request.hh"
40 #include "params/MipsTLB.hh"
41 #include "sim/sim_object.hh"
42 
43 namespace gem5
44 {
45 
46 class ThreadContext;
47 
48 /* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB
49  However, to maintain compatibility with other architectures, we'll
50  simply create an ITLB and DTLB that will point to the real TLB */
51 namespace MipsISA {
52 
53 class TLB : public BaseTLB
54 {
55  protected:
56  typedef std::multimap<Addr, int> PageTable;
57  PageTable lookupTable; // Quick lookup into page table
58 
59  MipsISA::PTE *table; // the Page Table
60  int size; // TLB Size
61  int nlu; // not last used entry (for replacement)
62 
63  void nextnlu() { if (++nlu >= size) nlu = 0; }
64  MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
65 
66  public:
67  typedef MipsTLBParams Params;
68  TLB(const Params &p);
69 
70  int probeEntry(Addr vpn,uint8_t) const;
71  MipsISA::PTE *getEntry(unsigned) const;
72  virtual ~TLB();
73 
74  void takeOverFrom(BaseTLB *otlb) override {}
75 
77  int getsize() const { return size; }
78 
79  MipsISA::PTE &index(bool advance = true);
80  void insert(Addr vaddr, MipsISA::PTE &pte);
81  void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
82  void flushAll() override;
83  void demapPage(Addr vaddr, uint64_t asn) override
84  {
85  panic("demapPage unimplemented.\n");
86  }
87 
88  // static helper functions... really
89  static bool validVirtualAddress(Addr vaddr);
90 
91  static Fault checkCacheability(const RequestPtr &req);
92 
93  // Checkpointing
94  void serialize(CheckpointOut &cp) const override;
95  void unserialize(CheckpointIn &cp) override;
96 
98  const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override;
99  void translateTiming(
100  const RequestPtr &req, ThreadContext *tc,
101  BaseMMU::Translation *translation, BaseMMU::Mode mode) override;
103  const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override;
105  const RequestPtr &req,
106  ThreadContext *tc, BaseMMU::Mode mode) const override;
107 };
108 
109 } // namespace MipsISA
110 } // namespace gem5
111 
112 #endif // __MIPS_MEMORY_HH__
gem5::MipsISA::TLB::lookup
MipsISA::PTE * lookup(Addr vpn, uint8_t asn) const
gem5::MipsISA::TLB::getsize
int getsize() const
Definition: tlb.hh:77
gem5::MipsISA::TLB::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
gem5::MipsISA::TLB::takeOverFrom
void takeOverFrom(BaseTLB *otlb) override
Take over from an old tlb context.
Definition: tlb.hh:74
gem5::MipsISA::TLB::nlu
int nlu
Definition: tlb.hh:61
gem5::MipsISA::TLB::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
gem5::MipsISA::TLB::finalizePhysical
Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const override
Do post-translation physical address finalization.
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::MipsISA::TLB::checkCacheability
static Fault checkCacheability(const RequestPtr &req)
gem5::CheckpointIn
Definition: serialize.hh:68
tlb.hh
gem5::MipsISA::TLB::TLB
TLB(const Params &p)
gem5::MipsISA::TLB::~TLB
virtual ~TLB()
gem5::MipsISA::TLB::nextnlu
void nextnlu()
Definition: tlb.hh:63
gem5::MipsISA::TLB::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
gem5::MipsISA::TLB::validVirtualAddress
static bool validVirtualAddress(Addr vaddr)
request.hh
gem5::MipsISA::TLB::lookupTable
PageTable lookupTable
Definition: tlb.hh:57
gem5::MipsISA::TLB::flushAll
void flushAll() override
Remove all entries from the TLB.
gem5::MipsISA::TLB::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) override
gem5::MipsISA::TLB::getEntry
MipsISA::PTE * getEntry(unsigned) const
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
sim_object.hh
gem5::MipsISA::TLB::index
MipsISA::PTE & index(bool advance=true)
gem5::MipsISA::TLB::probeEntry
int probeEntry(Addr vpn, uint8_t) const
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
statistics.hh
gem5::MipsISA::TLB::PageTable
std::multimap< Addr, int > PageTable
Definition: tlb.hh:56
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::BaseTLB
Definition: tlb.hh:58
utility.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::MipsISA::TLB::Params
MipsTLBParams Params
Definition: tlb.hh:67
gem5::MipsISA::TLB::insert
void insert(Addr vaddr, MipsISA::PTE &pte)
gem5::BaseMMU::Translation
Definition: mmu.hh:58
gem5::MipsISA::TLB
Definition: tlb.hh:53
gem5::MipsISA::TLB::translateFunctional
Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
gem5::MipsISA::PTE
Definition: pagetable.hh:43
gem5::MipsISA::TLB::smallPages
int smallPages
Definition: tlb.hh:76
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::MipsISA::TLB::insertAt
void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages)
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::MipsISA::TLB::table
MipsISA::PTE * table
Definition: tlb.hh:59
gem5::MipsISA::TLB::size
int size
Definition: tlb.hh:60
gem5::MipsISA::TLB::demapPage
void demapPage(Addr vaddr, uint64_t asn) override
Definition: tlb.hh:83
pagetable.hh
gem5::MipsISA::mode
Bitfield< 11, 7 > mode
Definition: dt_constants.hh:98
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178

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