gem5  v21.1.0.2
Classes | Public Types | Public Member Functions | Public Attributes | Private Member Functions | Private Attributes | List of all members
gem5::o3::IEW Class Reference

IEW handles both single threaded and SMT IEW (issue/execute/writeback). More...

#include <iew.hh>

Classes

struct  IEWStats
 

Public Types

enum  Status { Active, Inactive }
 Overall IEW stage status. More...
 
enum  StageStatus {
  Running, Blocked, Idle, StartSquash,
  Squashing, Unblocking
}
 Status for Issue, Execute, and Writeback stages. More...
 

Public Member Functions

 IEW (CPU *_cpu, const O3CPUParams &params)
 Constructs a IEW with the given parameters. More...
 
std::string name () const
 Returns the name of the IEW stage. More...
 
void regProbePoints ()
 Registers probes. More...
 
void startupStage ()
 Initializes stage; sends back the number of free IQ and LSQ entries. More...
 
void clearStates (ThreadID tid)
 Clear all thread-specific states. More...
 
void setTimeBuffer (TimeBuffer< TimeStruct > *tb_ptr)
 Sets main time buffer used for backwards communication. More...
 
void setRenameQueue (TimeBuffer< RenameStruct > *rq_ptr)
 Sets time buffer for getting instructions coming from rename. More...
 
void setIEWQueue (TimeBuffer< IEWStruct > *iq_ptr)
 Sets time buffer to pass on instructions to commit. More...
 
void setActiveThreads (std::list< ThreadID > *at_ptr)
 Sets pointer to list of active threads. More...
 
void setScoreboard (Scoreboard *sb_ptr)
 Sets pointer to the scoreboard. More...
 
void drainSanityCheck () const
 Perform sanity checks after a drain. More...
 
bool isDrained () const
 Has the stage drained? More...
 
void takeOverFrom ()
 Takes over from another CPU's thread. More...
 
void squash (ThreadID tid)
 Squashes instructions in IEW for a specific thread. More...
 
void wakeDependents (const DynInstPtr &inst)
 Wakes all dependents of a completed instruction. More...
 
void rescheduleMemInst (const DynInstPtr &inst)
 Tells memory dependence unit that a memory instruction needs to be rescheduled. More...
 
void replayMemInst (const DynInstPtr &inst)
 Re-executes all rescheduled memory instructions. More...
 
void blockMemInst (const DynInstPtr &inst)
 Moves memory instruction onto the list of cache blocked instructions. More...
 
void cacheUnblocked ()
 Notifies that the cache has become unblocked. More...
 
void instToCommit (const DynInstPtr &inst)
 Sends an instruction to commit through the time buffer. More...
 
void skidInsert (ThreadID tid)
 Inserts unused instructions of a thread into the skid buffer. More...
 
int skidCount ()
 Returns the max of the number of entries in all of the skid buffers. More...
 
bool skidsEmpty ()
 Returns if all of the skid buffers are empty. More...
 
void updateStatus ()
 Updates overall IEW status based on all of the stages' statuses. More...
 
void resetEntries ()
 Resets entries of the IQ and the LSQ. More...
 
void wakeCPU ()
 Tells the CPU to wakeup if it has descheduled itself due to no activity. More...
 
void activityThisCycle ()
 Reports to the CPU that there is activity this cycle. More...
 
void activateStage ()
 Tells CPU that the IEW stage is active and running. More...
 
void deactivateStage ()
 Tells CPU that the IEW stage is inactive and idle. More...
 
bool hasStoresToWB ()
 Returns if the LSQ has any stores to writeback. More...
 
bool hasStoresToWB (ThreadID tid)
 Returns if the LSQ has any stores to writeback. More...
 
void checkMisprediction (const DynInstPtr &inst)
 Check misprediction
More...
 
void setLastRetiredHtmUid (ThreadID tid, uint64_t htmUid)
 
void tick ()
 Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and Writeback to run for one cycle. More...
 

Public Attributes

InstructionQueue instQueue
 Instruction queue. More...
 
LSQ ldstQueue
 Load / store queue. More...
 
FUPoolfuPool
 Pointer to the functional unit pool. More...
 
bool updateLSQNextCycle
 Records if the LSQ needs to be updated on the next cycle, so that IEW knows if there will be activity on the next cycle. More...
 

Private Member Functions

void squashDueToBranch (const DynInstPtr &inst, ThreadID tid)
 Sends commit proper information for a squash due to a branch mispredict. More...
 
void squashDueToMemOrder (const DynInstPtr &inst, ThreadID tid)
 Sends commit proper information for a squash due to a memory order violation. More...
 
void block (ThreadID tid)
 Sets Dispatch to blocked, and signals back to other stages to block. More...
 
void unblock (ThreadID tid)
 Unblocks Dispatch if the skid buffer is empty, and signals back to other stages to unblock. More...
 
void dispatch (ThreadID tid)
 Determines proper actions to take given Dispatch's status. More...
 
void dispatchInsts (ThreadID tid)
 Dispatches instructions to IQ and LSQ. More...
 
void executeInsts ()
 Executes instructions. More...
 
void writebackInsts ()
 Writebacks instructions. More...
 
bool checkStall (ThreadID tid)
 Checks if any of the stall conditions are currently true. More...
 
void checkSignalsAndUpdate (ThreadID tid)
 Processes inputs and changes state accordingly. More...
 
void emptyRenameInsts (ThreadID tid)
 Removes instructions from rename from a thread's instruction list. More...
 
void sortInsts ()
 Sorts instructions coming from rename into lists separated by thread. More...
 
void updateExeInstStats (const DynInstPtr &inst)
 Updates execution stats based on the instruction. More...
 
void printAvailableInsts ()
 Debug function to print instructions that are issued this cycle. More...
 

Private Attributes

Status _status
 Overall stage status. More...
 
StageStatus dispatchStatus [MaxThreads]
 Dispatch status. More...
 
StageStatus exeStatus
 Execute status. More...
 
StageStatus wbStatus
 Writeback status. More...
 
ProbePointArg< DynInstPtr > * ppMispredict
 Probe points. More...
 
ProbePointArg< DynInstPtr > * ppDispatch
 
ProbePointArg< DynInstPtr > * ppExecute
 To probe when instruction execution begins. More...
 
ProbePointArg< DynInstPtr > * ppToCommit
 To probe when instruction execution is complete. More...
 
TimeBuffer< TimeStruct > * timeBuffer
 Pointer to main time buffer used for backwards communication. More...
 
TimeBuffer< TimeStruct >::wire toFetch
 Wire to write information heading to previous stages. More...
 
TimeBuffer< TimeStruct >::wire fromCommit
 Wire to get commit's output from backwards time buffer. More...
 
TimeBuffer< TimeStruct >::wire toRename
 Wire to write information heading to previous stages. More...
 
TimeBuffer< RenameStruct > * renameQueue
 Rename instruction queue interface. More...
 
TimeBuffer< RenameStruct >::wire fromRename
 Wire to get rename's output from rename queue. More...
 
TimeBuffer< IssueStructissueToExecQueue
 Issue stage queue. More...
 
TimeBuffer< IssueStruct >::wire fromIssue
 Wire to read information from the issue stage time queue. More...
 
TimeBuffer< IEWStruct > * iewQueue
 IEW stage time buffer. More...
 
TimeBuffer< IEWStruct >::wire toCommit
 Wire to write infromation heading to commit. More...
 
std::queue< DynInstPtrinsts [MaxThreads]
 Queue of all instructions coming from rename this cycle. More...
 
std::queue< DynInstPtrskidBuffer [MaxThreads]
 Skid buffer between rename and IEW. More...
 
Scoreboardscoreboard
 Scoreboard pointer. More...
 
CPUcpu
 CPU pointer. More...
 
bool wroteToTimeBuffer
 Records if IEW has written to the time buffer this cycle, so that the CPU can deschedule itself if there is no activity. More...
 
bool fetchRedirect [MaxThreads]
 Records if there is a fetch redirect on this cycle for each thread. More...
 
bool updatedQueues
 Records if the queues have been changed (inserted or issued insts), so that IEW knows to broadcast the updated amount of free entries. More...
 
Cycles commitToIEWDelay
 Commit to IEW delay. More...
 
Cycles renameToIEWDelay
 Rename to IEW delay. More...
 
Cycles issueToExecuteDelay
 Issue to execute delay. More...
 
unsigned dispatchWidth
 Width of dispatch, in instructions. More...
 
unsigned issueWidth
 Width of issue, in instructions. More...
 
unsigned wbNumInst
 Index into queue of instructions being written back. More...
 
unsigned wbCycle
 Cycle number within the queue of instructions being written back. More...
 
unsigned wbWidth
 Writeback width. More...
 
ThreadID numThreads
 Number of active threads. More...
 
std::list< ThreadID > * activeThreads
 Pointer to list of active threads. More...
 
unsigned skidBufferMax
 Maximum size of the skid buffer. More...
 
gem5::o3::IEW::IEWStats iewStats
 

Detailed Description

IEW handles both single threaded and SMT IEW (issue/execute/writeback).

It handles the dispatching of instructions to the LSQ/IQ as part of the issue stage, and has the IQ try to issue instructions each cycle. The execute latency is actually tied into the issue latency to allow the IQ to be able to do back-to-back scheduling without having to speculatively schedule instructions. This happens by having the IQ have access to the functional units, and the IQ gets the execution latencies from the FUs when it issues instructions. Instructions reach the execute stage on the last cycle of their execution, which is when the IQ knows to wake up any dependent instructions, allowing back to back scheduling. The execute portion of IEW separates memory instructions from non-memory instructions, either telling the LSQ to execute the instruction, or executing the instruction directly. The writeback portion of IEW completes the instructions by waking up any dependents, and marking the register ready on the scoreboard.

Definition at line 87 of file iew.hh.

Member Enumeration Documentation

◆ StageStatus

Status for Issue, Execute, and Writeback stages.

Enumerator
Running 
Blocked 
Idle 
StartSquash 
Squashing 
Unblocking 

Definition at line 100 of file iew.hh.

◆ Status

Overall IEW stage status.

Used to determine if the CPU can deschedule itself due to a lack of activity.

Enumerator
Active 
Inactive 

Definition at line 93 of file iew.hh.

Constructor & Destructor Documentation

◆ IEW()

gem5::o3::IEW::IEW ( CPU _cpu,
const O3CPUParams &  params 
)

Member Function Documentation

◆ activateStage()

void gem5::o3::IEW::activateStage ( )

Tells CPU that the IEW stage is active and running.

Definition at line 818 of file iew.cc.

References gem5::o3::CPU::activateStage(), cpu, DPRINTF, and gem5::o3::CPU::IEWIdx.

Referenced by updateStatus().

◆ activityThisCycle()

void gem5::o3::IEW::activityThisCycle ( )

Reports to the CPU that there is activity this cycle.

Definition at line 811 of file iew.cc.

References gem5::o3::CPU::activityThisCycle(), cpu, and DPRINTF.

Referenced by executeInsts(), gem5::o3::LSQUnit::executeLoad(), and gem5::o3::LSQUnit::writeback().

◆ block()

void gem5::o3::IEW::block ( ThreadID  tid)
private

Sets Dispatch to blocked, and signals back to other stages to block.

Definition at line 505 of file iew.cc.

References Blocked, dispatchStatus, DPRINTF, skidInsert(), toRename, Unblocking, and wroteToTimeBuffer.

Referenced by checkSignalsAndUpdate(), and dispatchInsts().

◆ blockMemInst()

void gem5::o3::IEW::blockMemInst ( const DynInstPtr inst)

Moves memory instruction onto the list of cache blocked instructions.

Definition at line 557 of file iew.cc.

References gem5::o3::InstructionQueue::blockMemInst(), and instQueue.

Referenced by gem5::o3::LSQUnit::read().

◆ cacheUnblocked()

void gem5::o3::IEW::cacheUnblocked ( )

Notifies that the cache has become unblocked.

Definition at line 563 of file iew.cc.

References gem5::o3::InstructionQueue::cacheUnblocked(), and instQueue.

Referenced by gem5::o3::LSQ::recvReqRetry(), and gem5::o3::LSQ::tick().

◆ checkMisprediction()

void gem5::o3::IEW::checkMisprediction ( const DynInstPtr inst)

◆ checkSignalsAndUpdate()

void gem5::o3::IEW::checkSignalsAndUpdate ( ThreadID  tid)
private

Processes inputs and changes state accordingly.

Definition at line 708 of file iew.cc.

References block(), Blocked, checkStall(), dispatchStatus, DPRINTF, emptyRenameInsts(), fetchRedirect, fromCommit, Running, squash(), Squashing, toRename, unblock(), Unblocking, and wroteToTimeBuffer.

Referenced by tick().

◆ checkStall()

bool gem5::o3::IEW::checkStall ( ThreadID  tid)
private

Checks if any of the stall conditions are currently true.

Definition at line 692 of file iew.cc.

References DPRINTF, fromCommit, instQueue, and gem5::o3::InstructionQueue::isFull().

Referenced by checkSignalsAndUpdate().

◆ clearStates()

void gem5::o3::IEW::clearStates ( ThreadID  tid)

◆ deactivateStage()

void gem5::o3::IEW::deactivateStage ( )

Tells CPU that the IEW stage is inactive and idle.

Definition at line 825 of file iew.cc.

References cpu, gem5::o3::CPU::deactivateStage(), DPRINTF, and gem5::o3::CPU::IEWIdx.

Referenced by updateStatus().

◆ dispatch()

void gem5::o3::IEW::dispatch ( ThreadID  tid)
private

◆ dispatchInsts()

void gem5::o3::IEW::dispatchInsts ( ThreadID  tid)
private

◆ drainSanityCheck()

void gem5::o3::IEW::drainSanityCheck ( ) const

Perform sanity checks after a drain.

Definition at line 383 of file iew.cc.

References gem5::o3::InstructionQueue::drainSanityCheck(), gem5::o3::LSQ::drainSanityCheck(), instQueue, isDrained(), and ldstQueue.

Referenced by gem5::o3::CPU::drainSanityCheck().

◆ emptyRenameInsts()

void gem5::o3::IEW::emptyRenameInsts ( ThreadID  tid)
private

Removes instructions from rename from a thread's instruction list.

Definition at line 784 of file iew.cc.

References DPRINTF, insts, and toRename.

Referenced by checkSignalsAndUpdate(), and squash().

◆ executeInsts()

void gem5::o3::IEW::executeInsts ( )
private

◆ hasStoresToWB() [1/2]

bool gem5::o3::IEW::hasStoresToWB ( )
inline

Returns if the LSQ has any stores to writeback.

Definition at line 221 of file iew.hh.

References gem5::o3::LSQ::hasStoresToWB(), and ldstQueue.

Referenced by gem5::o3::Commit::commit(), and gem5::o3::Commit::commitHead().

◆ hasStoresToWB() [2/2]

bool gem5::o3::IEW::hasStoresToWB ( ThreadID  tid)
inline

Returns if the LSQ has any stores to writeback.

Definition at line 224 of file iew.hh.

References gem5::o3::LSQ::hasStoresToWB(), and ldstQueue.

◆ instToCommit()

void gem5::o3::IEW::instToCommit ( const DynInstPtr inst)

Sends an instruction to commit through the time buffer.

Definition at line 569 of file iew.cc.

References DPRINTF, iewQueue, insts, wbCycle, wbNumInst, and wbWidth.

Referenced by executeInsts(), gem5::o3::LSQUnit::executeLoad(), and gem5::o3::LSQUnit::writeback().

◆ isDrained()

bool gem5::o3::IEW::isDrained ( ) const

◆ name()

std::string gem5::o3::IEW::name ( ) const

Returns the name of the IEW stage.

Definition at line 119 of file iew.cc.

References cpu, and gem5::Named::name().

Referenced by gem5::o3::LSQUnit::name(), and gem5::o3::LSQ::name().

◆ printAvailableInsts()

void gem5::o3::IEW::printAvailableInsts ( )
private

Debug function to print instructions that are issued this cycle.

Definition at line 1115 of file iew.cc.

References fromIssue.

◆ regProbePoints()

void gem5::o3::IEW::regProbePoints ( )

Registers probes.

Probe point with dynamic instruction as the argument used to probe when an instruction starts to execute.

Probe point with dynamic instruction as the argument used to probe when an instruction execution completes and it is marked ready to commit.

Definition at line 125 of file iew.cc.

References cpu, gem5::SimObject::getProbeManager(), ppDispatch, ppExecute, ppMispredict, and ppToCommit.

Referenced by gem5::o3::CPU::regProbePoints().

◆ replayMemInst()

void gem5::o3::IEW::replayMemInst ( const DynInstPtr inst)

Re-executes all rescheduled memory instructions.

Definition at line 551 of file iew.cc.

References instQueue, and gem5::o3::InstructionQueue::replayMemInst().

Referenced by gem5::o3::LSQUnit::completeStore(), and gem5::o3::LSQUnit::storePostSend().

◆ rescheduleMemInst()

void gem5::o3::IEW::rescheduleMemInst ( const DynInstPtr inst)

Tells memory dependence unit that a memory instruction needs to be rescheduled.

It will re-execute once replayMemInst() is called.

Definition at line 545 of file iew.cc.

References instQueue, and gem5::o3::InstructionQueue::rescheduleMemInst().

Referenced by gem5::o3::LSQUnit::read().

◆ resetEntries()

void gem5::o3::IEW::resetEntries ( )

Resets entries of the IQ and the LSQ.

◆ setActiveThreads()

void gem5::o3::IEW::setActiveThreads ( std::list< ThreadID > *  at_ptr)

Sets pointer to list of active threads.

Definition at line 340 of file iew.cc.

References activeThreads, instQueue, ldstQueue, gem5::o3::InstructionQueue::setActiveThreads(), and gem5::o3::LSQ::setActiveThreads().

◆ setIEWQueue()

void gem5::o3::IEW::setIEWQueue ( TimeBuffer< IEWStruct > *  iq_ptr)

Sets time buffer to pass on instructions to commit.

Definition at line 331 of file iew.cc.

References iewQueue, and toCommit.

◆ setLastRetiredHtmUid()

void gem5::o3::IEW::setLastRetiredHtmUid ( ThreadID  tid,
uint64_t  htmUid 
)
inline

Definition at line 234 of file iew.hh.

References ldstQueue, and gem5::o3::LSQ::setLastRetiredHtmUid().

Referenced by gem5::o3::Commit::commitHead().

◆ setRenameQueue()

void gem5::o3::IEW::setRenameQueue ( TimeBuffer< RenameStruct > *  rq_ptr)

Sets time buffer for getting instructions coming from rename.

Definition at line 322 of file iew.cc.

References fromRename, renameQueue, and renameToIEWDelay.

◆ setScoreboard()

void gem5::o3::IEW::setScoreboard ( Scoreboard sb_ptr)

Sets pointer to the scoreboard.

Definition at line 349 of file iew.cc.

References scoreboard.

◆ setTimeBuffer()

void gem5::o3::IEW::setTimeBuffer ( TimeBuffer< TimeStruct > *  tb_ptr)

Sets main time buffer used for backwards communication.

Definition at line 305 of file iew.cc.

References commitToIEWDelay, fromCommit, instQueue, gem5::o3::InstructionQueue::setTimeBuffer(), timeBuffer, toFetch, and toRename.

◆ skidCount()

int gem5::o3::IEW::skidCount ( )

Returns the max of the number of entries in all of the skid buffers.

Definition at line 618 of file iew.cc.

References activeThreads, and skidBuffer.

◆ skidInsert()

void gem5::o3::IEW::skidInsert ( ThreadID  tid)

Inserts unused instructions of a thread into the skid buffer.

Definition at line 597 of file iew.cc.

References DPRINTF, insts, skidBuffer, and skidBufferMax.

Referenced by block(), and dispatch().

◆ skidsEmpty()

bool gem5::o3::IEW::skidsEmpty ( )

Returns if all of the skid buffers are empty.

Definition at line 636 of file iew.cc.

References activeThreads, and skidBuffer.

Referenced by dispatch().

◆ sortInsts()

void gem5::o3::IEW::sortInsts ( )
private

Sorts instructions coming from rename into lists separated by thread.

Definition at line 771 of file iew.cc.

References fromRename, gem5::ArmISA::i, insts, and numThreads.

Referenced by tick().

◆ squash()

void gem5::o3::IEW::squash ( ThreadID  tid)

Squashes instructions in IEW for a specific thread.

Definition at line 419 of file iew.cc.

References DPRINTF, emptyRenameInsts(), fromCommit, instQueue, ldstQueue, skidBuffer, gem5::o3::InstructionQueue::squash(), gem5::o3::LSQ::squash(), toRename, and updatedQueues.

Referenced by checkSignalsAndUpdate().

◆ squashDueToBranch()

void gem5::o3::IEW::squashDueToBranch ( const DynInstPtr inst,
ThreadID  tid 
)
private

Sends commit proper information for a squash due to a branch mispredict.

Definition at line 454 of file iew.cc.

References DPRINTF, gem5::MipsISA::pc, toCommit, and wroteToTimeBuffer.

Referenced by checkMisprediction(), and executeInsts().

◆ squashDueToMemOrder()

void gem5::o3::IEW::squashDueToMemOrder ( const DynInstPtr inst,
ThreadID  tid 
)
private

Sends commit proper information for a squash due to a memory order violation.

Definition at line 479 of file iew.cc.

References DPRINTF, toCommit, and wroteToTimeBuffer.

Referenced by executeInsts().

◆ startupStage()

void gem5::o3::IEW::startupStage ( )

◆ takeOverFrom()

void gem5::o3::IEW::takeOverFrom ( )

◆ tick()

void gem5::o3::IEW::tick ( )

◆ unblock()

void gem5::o3::IEW::unblock ( ThreadID  tid)
private

Unblocks Dispatch if the skid buffer is empty, and signals back to other stages to unblock.

Definition at line 523 of file iew.cc.

References dispatchStatus, DPRINTF, Running, skidBuffer, toRename, and wroteToTimeBuffer.

Referenced by checkSignalsAndUpdate(), and dispatch().

◆ updateExeInstStats()

void gem5::o3::IEW::updateExeInstStats ( const DynInstPtr inst)
private

◆ updateStatus()

void gem5::o3::IEW::updateStatus ( )

◆ wakeCPU()

void gem5::o3::IEW::wakeCPU ( )

Tells the CPU to wakeup if it has descheduled itself due to no activity.

Used mainly by the LdWritebackEvent.

Definition at line 805 of file iew.cc.

References cpu, and gem5::o3::CPU::wakeCPU().

Referenced by gem5::o3::InstructionQueue::processFUCompletion(), and gem5::o3::LSQUnit::writeback().

◆ wakeDependents()

void gem5::o3::IEW::wakeDependents ( const DynInstPtr inst)

Wakes all dependents of a completed instruction.

Definition at line 539 of file iew.cc.

References instQueue, and gem5::o3::InstructionQueue::wakeDependents().

◆ writebackInsts()

void gem5::o3::IEW::writebackInsts ( )
private

Writebacks instructions.

In our model, the instruction's execute() function atomically reads registers, executes, and writes registers. Thus this writeback only wakes up dependent instructions, and informs the scoreboard of registers becoming ready.

Definition at line 1383 of file iew.cc.

References gem5::o3::IEW::IEWStats::consumerInst, DPRINTF, gem5::ArmISA::i, iewStats, instQueue, gem5::o3::IEW::IEWStats::instsToCommit, gem5::NoFault, ppToCommit, gem5::o3::IEW::IEWStats::producerInst, scoreboard, gem5::o3::Scoreboard::setReg(), toCommit, gem5::o3::InstructionQueue::wakeDependents(), wbWidth, and gem5::o3::IEW::IEWStats::writebackCount.

Referenced by tick().

Member Data Documentation

◆ _status

Status gem5::o3::IEW::_status
private

Overall stage status.

Definition at line 112 of file iew.hh.

Referenced by IEW(), takeOverFrom(), and updateStatus().

◆ activeThreads

std::list<ThreadID>* gem5::o3::IEW::activeThreads
private

Pointer to list of active threads.

Definition at line 412 of file iew.hh.

Referenced by executeInsts(), setActiveThreads(), skidCount(), skidsEmpty(), tick(), and updateStatus().

◆ commitToIEWDelay

Cycles gem5::o3::IEW::commitToIEWDelay
private

Commit to IEW delay.

Definition at line 377 of file iew.hh.

Referenced by setTimeBuffer().

◆ cpu

CPU* gem5::o3::IEW::cpu
private

◆ dispatchStatus

StageStatus gem5::o3::IEW::dispatchStatus[MaxThreads]
private

Dispatch status.

Definition at line 114 of file iew.hh.

Referenced by block(), checkSignalsAndUpdate(), dispatch(), dispatchInsts(), IEW(), isDrained(), takeOverFrom(), unblock(), and updateStatus().

◆ dispatchWidth

unsigned gem5::o3::IEW::dispatchWidth
private

Width of dispatch, in instructions.

Definition at line 390 of file iew.hh.

Referenced by dispatchInsts(), and IEW().

◆ exeStatus

StageStatus gem5::o3::IEW::exeStatus
private

Execute status.

Definition at line 116 of file iew.hh.

Referenced by executeInsts(), IEW(), takeOverFrom(), and tick().

◆ fetchRedirect

bool gem5::o3::IEW::fetchRedirect[MaxThreads]
private

Records if there is a fetch redirect on this cycle for each thread.

Definition at line 369 of file iew.hh.

Referenced by checkMisprediction(), checkSignalsAndUpdate(), executeInsts(), IEW(), and takeOverFrom().

◆ fromCommit

TimeBuffer<TimeStruct>::wire gem5::o3::IEW::fromCommit
private

Wire to get commit's output from backwards time buffer.

Definition at line 306 of file iew.hh.

Referenced by checkSignalsAndUpdate(), checkStall(), setTimeBuffer(), squash(), and tick().

◆ fromIssue

TimeBuffer<IssueStruct>::wire gem5::o3::IEW::fromIssue
private

Wire to read information from the issue stage time queue.

Definition at line 321 of file iew.hh.

Referenced by executeInsts(), IEW(), and printAvailableInsts().

◆ fromRename

TimeBuffer<RenameStruct>::wire gem5::o3::IEW::fromRename
private

Wire to get rename's output from rename queue.

Definition at line 315 of file iew.hh.

Referenced by dispatch(), setRenameQueue(), and sortInsts().

◆ fuPool

FUPool* gem5::o3::IEW::fuPool

Pointer to the functional unit pool.

Definition at line 361 of file iew.hh.

Referenced by isDrained(), takeOverFrom(), and tick().

◆ iewQueue

TimeBuffer<IEWStruct>* gem5::o3::IEW::iewQueue
private

IEW stage time buffer.

Holds ROB indices of instructions that can be marked as completed.

Definition at line 327 of file iew.hh.

Referenced by instToCommit(), and setIEWQueue().

◆ iewStats

gem5::o3::IEW::IEWStats gem5::o3::IEW::iewStats
private

◆ instQueue

InstructionQueue gem5::o3::IEW::instQueue

◆ insts

std::queue<DynInstPtr> gem5::o3::IEW::insts[MaxThreads]
private

Queue of all instructions coming from rename this cycle.

Definition at line 333 of file iew.hh.

Referenced by dispatchInsts(), emptyRenameInsts(), instToCommit(), isDrained(), skidInsert(), and sortInsts().

◆ issueToExecQueue

TimeBuffer<IssueStruct> gem5::o3::IEW::issueToExecQueue
private

Issue stage queue.

Definition at line 318 of file iew.hh.

Referenced by IEW(), takeOverFrom(), and tick().

◆ issueToExecuteDelay

Cycles gem5::o3::IEW::issueToExecuteDelay
private

Issue to execute delay.

What this actually represents is the amount of time it takes for an instruction to wake up, be scheduled, and sent to a FU for execution.

Definition at line 387 of file iew.hh.

Referenced by IEW().

◆ issueWidth

unsigned gem5::o3::IEW::issueWidth
private

Width of issue, in instructions.

Definition at line 393 of file iew.hh.

Referenced by IEW().

◆ ldstQueue

LSQ gem5::o3::IEW::ldstQueue

◆ numThreads

ThreadID gem5::o3::IEW::numThreads
private

Number of active threads.

Definition at line 409 of file iew.hh.

Referenced by isDrained(), sortInsts(), startupStage(), and takeOverFrom().

◆ ppDispatch

ProbePointArg<DynInstPtr>* gem5::o3::IEW::ppDispatch
private

Definition at line 122 of file iew.hh.

Referenced by dispatchInsts(), and regProbePoints().

◆ ppExecute

ProbePointArg<DynInstPtr>* gem5::o3::IEW::ppExecute
private

To probe when instruction execution begins.

Definition at line 124 of file iew.hh.

Referenced by executeInsts(), and regProbePoints().

◆ ppMispredict

ProbePointArg<DynInstPtr>* gem5::o3::IEW::ppMispredict
private

Probe points.

Definition at line 121 of file iew.hh.

Referenced by executeInsts(), and regProbePoints().

◆ ppToCommit

ProbePointArg<DynInstPtr>* gem5::o3::IEW::ppToCommit
private

To probe when instruction execution is complete.

Definition at line 126 of file iew.hh.

Referenced by regProbePoints(), and writebackInsts().

◆ renameQueue

TimeBuffer<RenameStruct>* gem5::o3::IEW::renameQueue
private

Rename instruction queue interface.

Definition at line 312 of file iew.hh.

Referenced by setRenameQueue().

◆ renameToIEWDelay

Cycles gem5::o3::IEW::renameToIEWDelay
private

Rename to IEW delay.

Definition at line 380 of file iew.hh.

Referenced by IEW(), and setRenameQueue().

◆ scoreboard

Scoreboard* gem5::o3::IEW::scoreboard
private

Scoreboard pointer.

Definition at line 339 of file iew.hh.

Referenced by setScoreboard(), and writebackInsts().

◆ skidBuffer

std::queue<DynInstPtr> gem5::o3::IEW::skidBuffer[MaxThreads]
private

Skid buffer between rename and IEW.

Definition at line 336 of file iew.hh.

Referenced by dispatchInsts(), isDrained(), skidCount(), skidInsert(), skidsEmpty(), squash(), and unblock().

◆ skidBufferMax

unsigned gem5::o3::IEW::skidBufferMax
private

Maximum size of the skid buffer.

Definition at line 415 of file iew.hh.

Referenced by IEW(), and skidInsert().

◆ timeBuffer

TimeBuffer<TimeStruct>* gem5::o3::IEW::timeBuffer
private

Pointer to main time buffer used for backwards communication.

Definition at line 300 of file iew.hh.

Referenced by setTimeBuffer().

◆ toCommit

TimeBuffer<IEWStruct>::wire gem5::o3::IEW::toCommit
private

Wire to write infromation heading to commit.

Definition at line 330 of file iew.hh.

Referenced by checkMisprediction(), executeInsts(), setIEWQueue(), squashDueToBranch(), squashDueToMemOrder(), and writebackInsts().

◆ toFetch

TimeBuffer<TimeStruct>::wire gem5::o3::IEW::toFetch
private

Wire to write information heading to previous stages.

Definition at line 303 of file iew.hh.

Referenced by setTimeBuffer(), and tick().

◆ toRename

TimeBuffer<TimeStruct>::wire gem5::o3::IEW::toRename
private

Wire to write information heading to previous stages.

Definition at line 309 of file iew.hh.

Referenced by block(), checkSignalsAndUpdate(), clearStates(), dispatchInsts(), emptyRenameInsts(), setTimeBuffer(), squash(), startupStage(), tick(), and unblock().

◆ updatedQueues

bool gem5::o3::IEW::updatedQueues
private

Records if the queues have been changed (inserted or issued insts), so that IEW knows to broadcast the updated amount of free entries.

Definition at line 374 of file iew.hh.

Referenced by dispatchInsts(), executeInsts(), squash(), and tick().

◆ updateLSQNextCycle

bool gem5::o3::IEW::updateLSQNextCycle

Records if the LSQ needs to be updated on the next cycle, so that IEW knows if there will be activity on the next cycle.

Definition at line 365 of file iew.hh.

Referenced by gem5::o3::LSQUnit::completeStore(), IEW(), takeOverFrom(), and tick().

◆ wbCycle

unsigned gem5::o3::IEW::wbCycle
private

Cycle number within the queue of instructions being written back.

Used in case there are too many instructions writing back at the current cycle and writesbacks need to be scheduled for the future. See comments in instToCommit().

Definition at line 403 of file iew.hh.

Referenced by executeInsts(), instToCommit(), and tick().

◆ wbNumInst

unsigned gem5::o3::IEW::wbNumInst
private

Index into queue of instructions being written back.

Definition at line 396 of file iew.hh.

Referenced by executeInsts(), instToCommit(), and tick().

◆ wbStatus

StageStatus gem5::o3::IEW::wbStatus
private

Writeback status.

Definition at line 118 of file iew.hh.

Referenced by IEW(), and takeOverFrom().

◆ wbWidth

unsigned gem5::o3::IEW::wbWidth
private

Writeback width.

Definition at line 406 of file iew.hh.

Referenced by IEW(), instToCommit(), and writebackInsts().

◆ wroteToTimeBuffer

bool gem5::o3::IEW::wroteToTimeBuffer
private

Records if IEW has written to the time buffer this cycle, so that the CPU can deschedule itself if there is no activity.

Definition at line 348 of file iew.hh.

Referenced by block(), checkSignalsAndUpdate(), squashDueToBranch(), squashDueToMemOrder(), tick(), and unblock().


The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:31:45 for gem5 by doxygen 1.8.17