gem5  v21.1.0.2
sve.hh
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37 
38 #ifndef __ARCH_ARM_INSTS_SVE_HH__
39 #define __ARCH_ARM_INSTS_SVE_HH__
40 
42 
43 namespace gem5
44 {
45 
46 namespace ArmISA {
47 
48 enum class SvePredType
49 {
50  NONE,
51  MERGE,
52  ZERO,
53  SELECT
54 };
55 
57 const char* svePredTypeToStr(SvePredType pt);
58 
61 {
62  protected:
63  IntRegIndex dest;
64  int8_t imm1;
65  int8_t imm2;
66 
67  SveIndexIIOp(const char* mnem, ExtMachInst _machInst,
68  OpClass __opClass, IntRegIndex _dest,
69  int8_t _imm1, int8_t _imm2) :
70  ArmStaticInst(mnem, _machInst, __opClass),
71  dest(_dest), imm1(_imm1), imm2(_imm2)
72  {}
73  std::string generateDisassembly(
74  Addr pc, const loader::SymbolTable *symtab) const override;
75 };
76 
78 {
79  protected:
80  IntRegIndex dest;
81  int8_t imm1;
82  IntRegIndex op2;
83 
84  SveIndexIROp(const char* mnem, ExtMachInst _machInst,
85  OpClass __opClass, IntRegIndex _dest,
86  int8_t _imm1, IntRegIndex _op2) :
87  ArmStaticInst(mnem, _machInst, __opClass),
88  dest(_dest), imm1(_imm1), op2(_op2)
89  {}
90  std::string generateDisassembly(
91  Addr pc, const loader::SymbolTable *symtab) const override;
92 };
93 
95 {
96  protected:
97  IntRegIndex dest;
98  IntRegIndex op1;
99  int8_t imm2;
100 
101  SveIndexRIOp(const char* mnem, ExtMachInst _machInst,
102  OpClass __opClass, IntRegIndex _dest,
103  IntRegIndex _op1, int8_t _imm2) :
104  ArmStaticInst(mnem, _machInst, __opClass),
105  dest(_dest), op1(_op1), imm2(_imm2)
106  {}
107  std::string generateDisassembly(
108  Addr pc, const loader::SymbolTable *symtab) const override;
109 };
110 
112 {
113  protected:
114  IntRegIndex dest;
115  IntRegIndex op1;
116  IntRegIndex op2;
117 
118  SveIndexRROp(const char* mnem, ExtMachInst _machInst,
119  OpClass __opClass, IntRegIndex _dest,
120  IntRegIndex _op1, IntRegIndex _op2) :
121  ArmStaticInst(mnem, _machInst, __opClass),
122  dest(_dest), op1(_op1), op2(_op2)
123  {}
124  std::string generateDisassembly(
125  Addr pc, const loader::SymbolTable *symtab) const override;
126 };
127 
128 // Predicate count SVE instruction.
130 {
131  protected:
132  IntRegIndex dest;
133  IntRegIndex gp;
134  bool srcIs32b;
135  bool destIsVec;
136 
137  SvePredCountOp(const char* mnem, ExtMachInst _machInst,
138  OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp,
139  bool _srcIs32b = false, bool _destIsVec = false) :
140  ArmStaticInst(mnem, _machInst, __opClass),
141  dest(_dest), gp(_gp),
142  srcIs32b(_srcIs32b), destIsVec(_destIsVec)
143  {}
144  std::string generateDisassembly(
145  Addr pc, const loader::SymbolTable *symtab) const override;
146 };
147 
148 // Predicate count SVE instruction (predicated).
150 {
151  protected:
152  IntRegIndex dest;
153  IntRegIndex op1;
154  IntRegIndex gp;
155 
156  SvePredCountPredOp(const char* mnem, ExtMachInst _machInst,
157  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
158  IntRegIndex _gp) :
159  ArmStaticInst(mnem, _machInst, __opClass),
160  dest(_dest), op1(_op1), gp(_gp)
161  {}
162  std::string generateDisassembly(
163  Addr pc, const loader::SymbolTable *symtab) const override;
164 };
165 
167 class SveWhileOp : public ArmStaticInst
168 {
169  protected:
170  IntRegIndex dest, op1, op2;
171  bool srcIs32b;
172 
173  SveWhileOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
174  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
175  bool _srcIs32b) :
176  ArmStaticInst(mnem, _machInst, __opClass),
177  dest(_dest), op1(_op1), op2(_op2), srcIs32b(_srcIs32b)
178  {}
179  std::string generateDisassembly(
180  Addr pc, const loader::SymbolTable *symtab) const override;
181 };
182 
185 {
186  protected:
187  IntRegIndex op1, op2;
188 
189  SveCompTermOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
190  IntRegIndex _op1, IntRegIndex _op2) :
191  ArmStaticInst(mnem, _machInst, __opClass),
192  op1(_op1), op2(_op2)
193  {}
194  std::string generateDisassembly(
195  Addr pc, const loader::SymbolTable *symtab) const override;
196 };
197 
200 {
201  protected:
202  IntRegIndex dest, op1, gp;
203 
204  SveUnaryPredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
205  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp) :
206  ArmStaticInst(mnem, _machInst, __opClass),
207  dest(_dest), op1(_op1), gp(_gp)
208  {}
209 
210  std::string generateDisassembly(
211  Addr pc, const loader::SymbolTable *symtab) const override;
212 };
213 
216 {
217  protected:
218  IntRegIndex dest, op1;
219 
220  SveUnaryUnpredOp(const char* mnem, ExtMachInst _machInst,
221  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1) :
222  ArmStaticInst(mnem, _machInst, __opClass),
223  dest(_dest), op1(_op1)
224  {}
225 
226  std::string generateDisassembly(
227  Addr pc, const loader::SymbolTable *symtab) const override;
228 };
229 
232 {
233  protected:
234  IntRegIndex dest;
235  uint64_t imm;
236 
237  SveUnaryWideImmUnpredOp(const char* mnem, ExtMachInst _machInst,
238  OpClass __opClass, IntRegIndex _dest,
239  uint64_t _imm) :
240  ArmStaticInst(mnem, _machInst, __opClass),
241  dest(_dest), imm(_imm)
242  {}
243 
244  std::string generateDisassembly(
245  Addr pc, const loader::SymbolTable *symtab) const override;
246 };
247 
250 {
251  protected:
252  IntRegIndex dest;
253  uint64_t imm;
254  IntRegIndex gp;
255 
256  bool isMerging;
257 
258  SveUnaryWideImmPredOp(const char* mnem, ExtMachInst _machInst,
259  OpClass __opClass, IntRegIndex _dest,
260  uint64_t _imm, IntRegIndex _gp, bool _isMerging) :
261  ArmStaticInst(mnem, _machInst, __opClass),
262  dest(_dest), imm(_imm), gp(_gp), isMerging(_isMerging)
263  {}
264 
265  std::string generateDisassembly(
266  Addr pc, const loader::SymbolTable *symtab) const override;
267 };
268 
271 {
272  protected:
273  IntRegIndex dest, op1;
274  uint64_t imm;
275 
276  SveBinImmUnpredConstrOp(const char* mnem, ExtMachInst _machInst,
277  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
278  uint64_t _imm) :
279  ArmStaticInst(mnem, _machInst, __opClass),
280  dest(_dest), op1(_op1), imm(_imm)
281  {}
282 
283  std::string generateDisassembly(
284  Addr pc, const loader::SymbolTable *symtab) const override;
285 };
286 
289 {
290  protected:
291  IntRegIndex dest, gp;
292  uint64_t imm;
293 
294  SveBinImmPredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
295  IntRegIndex _dest, uint64_t _imm, IntRegIndex _gp) :
296  ArmStaticInst(mnem, _machInst, __opClass),
297  dest(_dest), gp(_gp), imm(_imm)
298  {}
299 
300  std::string generateDisassembly(
301  Addr pc, const loader::SymbolTable *symtab) const override;
302 };
303 
306 {
307  protected:
308  IntRegIndex dest;
309  uint64_t imm;
310 
311  SveBinWideImmUnpredOp(const char* mnem, ExtMachInst _machInst,
312  OpClass __opClass, IntRegIndex _dest,
313  uint64_t _imm) :
314  ArmStaticInst(mnem, _machInst, __opClass),
315  dest(_dest), imm(_imm)
316  {}
317 
318  std::string generateDisassembly(
319  Addr pc, const loader::SymbolTable *symtab) const override;
320 };
321 
324 {
325  protected:
326  IntRegIndex dest, op2, gp;
327 
328  SveBinDestrPredOp(const char* mnem, ExtMachInst _machInst,
329  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op2,
330  IntRegIndex _gp) :
331  ArmStaticInst(mnem, _machInst, __opClass),
332  dest(_dest), op2(_op2), gp(_gp)
333  {}
334 
335  std::string generateDisassembly(
336  Addr pc, const loader::SymbolTable *symtab) const override;
337 };
338 
341 {
342  protected:
343  IntRegIndex dest, op1, op2, gp;
345 
346  SveBinConstrPredOp(const char* mnem, ExtMachInst _machInst,
347  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
348  IntRegIndex _op2, IntRegIndex _gp,
349  SvePredType _predType) :
350  ArmStaticInst(mnem, _machInst, __opClass),
351  dest(_dest), op1(_op1), op2(_op2), gp(_gp), predType(_predType)
352  {}
353 
354  std::string generateDisassembly(
355  Addr pc, const loader::SymbolTable *symtab) const override;
356 };
357 
360 {
361  protected:
362  IntRegIndex dest, op1, op2;
363 
364  SveBinUnpredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
365  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
366  ArmStaticInst(mnem, _machInst, __opClass),
367  dest(_dest), op1(_op1), op2(_op2)
368  {}
369 
370  std::string generateDisassembly(
371  Addr pc, const loader::SymbolTable *symtab) const override;
372 };
373 
376 {
377  protected:
378  IntRegIndex dest, op1, op2;
379  uint8_t index;
380 
381  SveBinIdxUnpredOp(const char* mnem, ExtMachInst _machInst,
382  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
383  IntRegIndex _op2, uint8_t _index) :
384  ArmStaticInst(mnem, _machInst, __opClass),
385  dest(_dest), op1(_op1), op2(_op2), index(_index)
386  {}
387 
388  std::string generateDisassembly(
389  Addr pc, const loader::SymbolTable *symtab) const override;
390 };
391 
394 {
395  protected:
396  IntRegIndex dest, op1, op2, gp;
397  bool isSel;
398 
399  SvePredLogicalOp(const char* mnem, ExtMachInst _machInst,
400  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
401  IntRegIndex _op2, IntRegIndex _gp, bool _isSel = false) :
402  ArmStaticInst(mnem, _machInst, __opClass),
403  dest(_dest), op1(_op1), op2(_op2), gp(_gp), isSel(_isSel)
404  {}
405 
406  std::string generateDisassembly(
407  Addr pc, const loader::SymbolTable *symtab) const override;
408 };
409 
412 {
413  protected:
414  IntRegIndex dest, op1, op2;
415 
416  SvePredBinPermOp(const char* mnem, ExtMachInst _machInst,
417  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
418  IntRegIndex _op2) :
419  ArmStaticInst(mnem, _machInst, __opClass),
420  dest(_dest), op1(_op1), op2(_op2)
421  {}
422 
423  std::string generateDisassembly(
424  Addr pc, const loader::SymbolTable *symtab) const override;
425 };
426 
428 class SveCmpOp : public ArmStaticInst
429 {
430  protected:
431  IntRegIndex dest, gp, op1, op2;
432 
433  SveCmpOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
434  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
435  IntRegIndex _gp) :
436  ArmStaticInst(mnem, _machInst, __opClass),
437  dest(_dest), gp(_gp), op1(_op1), op2(_op2)
438  {}
439 
440  std::string generateDisassembly(
441  Addr pc, const loader::SymbolTable *symtab) const override;
442 };
443 
446 {
447  protected:
448  IntRegIndex dest, gp, op1;
449  uint64_t imm;
450 
451  SveCmpImmOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
452  IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm,
453  IntRegIndex _gp) :
454  ArmStaticInst(mnem, _machInst, __opClass),
455  dest(_dest), gp(_gp), op1(_op1), imm(_imm)
456  {}
457 
458  std::string generateDisassembly(
459  Addr pc, const loader::SymbolTable *symtab) const override;
460 };
461 
464 {
465  protected:
466  IntRegIndex dest, op1, op2, gp;
467 
468  SveTerPredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
469  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
470  IntRegIndex _gp) :
471  ArmStaticInst(mnem, _machInst, __opClass),
472  dest(_dest), op1(_op1), op2(_op2), gp(_gp)
473  {}
474 
475  std::string generateDisassembly(
476  Addr pc, const loader::SymbolTable *symtab) const override;
477 };
478 
481 {
482  protected:
483  IntRegIndex dest, op2;
484  uint64_t imm;
485 
486  SveTerImmUnpredOp(const char* mnem, ExtMachInst _machInst,
487  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op2,
488  uint64_t _imm) :
489  ArmStaticInst(mnem, _machInst, __opClass),
490  dest(_dest), op2(_op2), imm(_imm)
491  {}
492 
493  std::string generateDisassembly(
494  Addr pc, const loader::SymbolTable *symtab) const override;
495 };
496 
498 class SveReducOp : public ArmStaticInst
499 {
500  protected:
501  IntRegIndex dest, op1, gp;
502 
503  SveReducOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
504  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp) :
505  ArmStaticInst(mnem, _machInst, __opClass),
506  dest(_dest), op1(_op1), gp(_gp)
507  {}
508 
509  std::string generateDisassembly(
510  Addr pc, const loader::SymbolTable *symtab) const override;
511 };
512 
515 {
516  protected:
517  IntRegIndex dest, op1, gp;
518 
519  SveOrdReducOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
520  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp) :
521  ArmStaticInst(mnem, _machInst, __opClass),
522  dest(_dest), op1(_op1), gp(_gp)
523  {}
524 
525  std::string generateDisassembly(
526  Addr pc, const loader::SymbolTable *symtab) const override;
527 };
528 
530 class SvePtrueOp : public ArmStaticInst
531 {
532  protected:
533  IntRegIndex dest;
534  uint8_t imm;
535 
536  SvePtrueOp(const char* mnem, ExtMachInst _machInst,
537  OpClass __opClass, IntRegIndex _dest, uint8_t _imm) :
538  ArmStaticInst(mnem, _machInst, __opClass),
539  dest(_dest), imm(_imm)
540  {}
541 
542  std::string generateDisassembly(
543  Addr pc, const loader::SymbolTable *symtab) const override;
544 };
545 
548 {
549  protected:
550  IntRegIndex dest;
551  IntRegIndex op1, op2;
552  IntRegIndex gp;
553  bool op2IsWide;
554 
555  SveIntCmpOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
556  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
557  IntRegIndex _gp, bool _op2IsWide = false) :
558  ArmStaticInst(mnem, _machInst, __opClass),
559  dest(_dest), op1(_op1), op2(_op2), gp(_gp), op2IsWide(_op2IsWide)
560  {}
561  std::string generateDisassembly(
562  Addr pc, const loader::SymbolTable *symtab) const override;
563 };
564 
567 {
568  protected:
569  IntRegIndex dest;
570  IntRegIndex op1;
571  int64_t imm;
572  IntRegIndex gp;
573 
574  SveIntCmpImmOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
575  IntRegIndex _dest, IntRegIndex _op1, int64_t _imm,
576  IntRegIndex _gp) :
577  ArmStaticInst(mnem, _machInst, __opClass),
578  dest(_dest), op1(_op1), imm(_imm), gp(_gp)
579  {}
580  std::string generateDisassembly(
581  Addr pc, const loader::SymbolTable *symtab) const override;
582 };
583 
585 class SveAdrOp : public ArmStaticInst
586 {
587  public:
589  {
593  };
594 
595  protected:
596  IntRegIndex dest, op1, op2;
597  uint8_t mult;
599 
600  SveAdrOp(const char* mnem, ExtMachInst _machInst,
601  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
602  IntRegIndex _op2, uint8_t _mult,
603  SveAdrOffsetFormat _offsetFormat) :
604  ArmStaticInst(mnem, _machInst, __opClass),
605  dest(_dest), op1(_op1), op2(_op2), mult(_mult),
606  offsetFormat(_offsetFormat)
607  {}
608  std::string generateDisassembly(
609  Addr pc, const loader::SymbolTable *symtab) const override;
610 };
611 
614 {
615  protected:
616  IntRegIndex dest;
617  uint8_t pattern;
618  uint8_t imm;
619  bool dstIsVec;
620  bool dstIs32b;
621  uint8_t esize;
622 
623  SveElemCountOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
624  IntRegIndex _dest, uint8_t _pattern, uint8_t _imm,
625  bool _dstIsVec, bool _dstIs32b) :
626  ArmStaticInst(mnem, _machInst, __opClass),
627  dest(_dest), pattern(_pattern), imm(_imm), dstIsVec(_dstIsVec),
628  dstIs32b(_dstIs32b)
629  {}
630  std::string generateDisassembly(
631  Addr pc, const loader::SymbolTable *symtab) const override;
632 };
633 
636 {
637  protected:
638  IntRegIndex dest;
639  IntRegIndex gp;
640  IntRegIndex op1;
641  bool isMerging;
642 
643  SvePartBrkOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
644  IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _op1,
645  bool _isMerging) :
646  ArmStaticInst(mnem, _machInst, __opClass),
647  dest(_dest), gp(_gp), op1(_op1), isMerging(_isMerging)
648  {}
649  std::string generateDisassembly(
650  Addr pc, const loader::SymbolTable *symtab) const override;
651 };
652 
655 {
656  protected:
657  IntRegIndex dest;
658  IntRegIndex op1;
659  IntRegIndex op2;
660  IntRegIndex gp;
661 
662  SvePartBrkPropOp(const char* mnem, ExtMachInst _machInst,
663  OpClass __opClass, IntRegIndex _dest,
664  IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _gp) :
665  ArmStaticInst(mnem, _machInst, __opClass),
666  dest(_dest), op1(_op1), op2(_op2), gp(_gp)
667  {}
668  std::string generateDisassembly(
669  Addr pc, const loader::SymbolTable *symtab) const override;
670 };
671 
674 {
675  protected:
676  IntRegIndex dest;
677  IntRegIndex op1;
678  IntRegIndex gp;
680  bool scalar;
681  bool simdFp;
682  size_t scalar_width;
683 
684  SveSelectOp(const char* mnem, ExtMachInst _machInst,
685  OpClass __opClass, IntRegIndex _dest,
686  IntRegIndex _op1, IntRegIndex _gp,
687  bool _conditional, bool _scalar,
688  bool _simdFp) :
689  ArmStaticInst(mnem, _machInst, __opClass),
690  dest(_dest), op1(_op1), gp(_gp), conditional(_conditional),
691  scalar(_scalar), simdFp(_simdFp)
692  {}
693  std::string generateDisassembly(
694  Addr pc, const loader::SymbolTable *symtab) const override;
695 };
696 
699 {
700  protected:
701  IntRegIndex dest;
702  IntRegIndex op1;
703  IntRegIndex gp;
704 
705  SveUnaryPredPredOp(const char* mnem, ExtMachInst _machInst,
706  OpClass __opClass, IntRegIndex _dest,
707  IntRegIndex _op1, IntRegIndex _gp) :
708  ArmStaticInst(mnem, _machInst, __opClass),
709  dest(_dest), op1(_op1), gp(_gp)
710  {}
711  std::string generateDisassembly(
712  Addr pc, const loader::SymbolTable *symtab) const override;
713 };
714 
716 class SveTblOp : public ArmStaticInst
717 {
718  protected:
719  IntRegIndex dest;
720  IntRegIndex op1;
721  IntRegIndex op2;
722 
723  SveTblOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
724  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
725  ArmStaticInst(mnem, _machInst, __opClass),
726  dest(_dest), op1(_op1), op2(_op2)
727  {}
728  std::string generateDisassembly(
729  Addr pc, const loader::SymbolTable *symtab) const override;
730 };
731 
734 {
735  protected:
736  IntRegIndex dest;
737  IntRegIndex op1;
738 
739  SveUnpackOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
740  IntRegIndex _dest, IntRegIndex _op1) :
741  ArmStaticInst(mnem, _machInst, __opClass),
742  dest(_dest), op1(_op1)
743  {}
744  std::string generateDisassembly(
745  Addr pc, const loader::SymbolTable *symtab) const override;
746 };
747 
750 {
751  protected:
752  IntRegIndex op1;
753  IntRegIndex gp;
754 
755  SvePredTestOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
756  IntRegIndex _op1, IntRegIndex _gp) :
757  ArmStaticInst(mnem, _machInst, __opClass),
758  op1(_op1), gp(_gp)
759  {}
760  std::string generateDisassembly(
761  Addr pc, const loader::SymbolTable *symtab) const override;
762 };
763 
766 {
767  protected:
768  IntRegIndex dest;
769 
770  SvePredUnaryWImplicitSrcOp(const char* mnem, ExtMachInst _machInst,
771  OpClass __opClass, IntRegIndex _dest) :
772  ArmStaticInst(mnem, _machInst, __opClass),
773  dest(_dest)
774  {}
775  std::string generateDisassembly(
776  Addr pc, const loader::SymbolTable *symtab) const override;
777 };
778 
781 {
782  protected:
783  IntRegIndex dest;
784  IntRegIndex gp;
785 
786  SvePredUnaryWImplicitSrcPredOp(const char* mnem, ExtMachInst _machInst,
787  OpClass __opClass, IntRegIndex _dest,
788  IntRegIndex _gp) :
789  ArmStaticInst(mnem, _machInst, __opClass),
790  dest(_dest), gp(_gp)
791  {}
792  std::string generateDisassembly(
793  Addr pc, const loader::SymbolTable *symtab) const override;
794 };
795 
798 {
799  protected:
800  IntRegIndex op1;
801 
802  SvePredUnaryWImplicitDstOp(const char* mnem, ExtMachInst _machInst,
803  OpClass __opClass, IntRegIndex _op1) :
804  ArmStaticInst(mnem, _machInst, __opClass),
805  op1(_op1)
806  {}
807  std::string generateDisassembly(
808  Addr pc, const loader::SymbolTable *symtab) const override;
809 };
810 
813 {
814  protected:
815  SveWImplicitSrcDstOp(const char* mnem, ExtMachInst _machInst,
816  OpClass __opClass) :
817  ArmStaticInst(mnem, _machInst, __opClass)
818  {}
819  std::string generateDisassembly(
820  Addr pc, const loader::SymbolTable *symtab) const override;
821 };
822 
825 {
826  protected:
827  IntRegIndex dest;
828  IntRegIndex op1;
829  uint64_t imm;
830 
831  SveBinImmUnpredDestrOp(const char* mnem, ExtMachInst _machInst,
832  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
833  uint64_t _imm) :
834  ArmStaticInst(mnem, _machInst, __opClass),
835  dest(_dest), op1(_op1), imm(_imm)
836  {}
837  std::string generateDisassembly(
838  Addr pc, const loader::SymbolTable *symtab) const override;
839 };
840 
843 {
844  protected:
845  IntRegIndex dest, op1;
846  uint64_t imm;
847 
848  SveBinImmIdxUnpredOp(const char* mnem, ExtMachInst _machInst,
849  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
850  uint64_t _imm) :
851  ArmStaticInst(mnem, _machInst, __opClass),
852  dest(_dest), op1(_op1), imm(_imm)
853  {}
854 
855  std::string generateDisassembly(
856  Addr pc, const loader::SymbolTable *symtab) const override;
857 };
858 
861 {
862  protected:
863  IntRegIndex dest, op1;
864  bool simdFp;
865 
866  SveUnarySca2VecUnpredOp(const char* mnem, ExtMachInst _machInst,
867  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
868  bool _simdFp) :
869  ArmStaticInst(mnem, _machInst, __opClass),
870  dest(_dest), op1(_op1), simdFp(_simdFp)
871  {}
872 
873  std::string generateDisassembly(
874  Addr pc, const loader::SymbolTable *symtab) const override;
875 };
876 
879 {
880  protected:
881  IntRegIndex dest, op1, op2;
882  uint64_t imm;
883  uint8_t esize;
884 
885  public:
886  SveDotProdIdxOp(const char* mnem, ExtMachInst _machInst,
887  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
888  IntRegIndex _op2, uint64_t _imm) :
889  ArmStaticInst(mnem, _machInst, __opClass),
890  dest(_dest), op1(_op1), op2(_op2), imm(_imm)
891  {}
892 
893  std::string generateDisassembly(
894  Addr pc, const loader::SymbolTable *symtab) const override;
895 };
896 
899 {
900  protected:
901  IntRegIndex dest, op1, op2;
902  uint8_t esize;
903 
904  public:
905  SveDotProdOp(const char* mnem, ExtMachInst _machInst,
906  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
907  IntRegIndex _op2) :
908  ArmStaticInst(mnem, _machInst, __opClass),
909  dest(_dest), op1(_op1), op2(_op2)
910  {}
911 
912  std::string generateDisassembly(
913  Addr pc, const loader::SymbolTable *symtab) const override;
914 };
915 
918 {
919  protected:
920  IntRegIndex dest, op1, op2, gp;
921  uint8_t rot;
922 
923  public:
924  SveComplexOp(const char* mnem, ExtMachInst _machInst,
925  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
926  IntRegIndex _op2, IntRegIndex _gp, uint8_t _rot) :
927  ArmStaticInst(mnem, _machInst, __opClass),
928  dest(_dest), op1(_op1), op2(_op2), gp(_gp), rot(_rot)
929  {}
930 
931  std::string generateDisassembly(
932  Addr pc, const loader::SymbolTable *symtab) const override;
933 };
934 
937 {
938  protected:
939  IntRegIndex dest, op1, op2;
940  uint8_t rot, imm;
941 
942  public:
943  SveComplexIdxOp(const char* mnem, ExtMachInst _machInst,
944  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
945  IntRegIndex _op2, uint8_t _rot, uint8_t _imm) :
946  ArmStaticInst(mnem, _machInst, __opClass),
947  dest(_dest), op1(_op1), op2(_op2), rot(_rot), imm(_imm)
948  {}
949 
950  std::string generateDisassembly(
951  Addr pc, const loader::SymbolTable *symtab) const override;
952 };
953 
954 
957 std::string sveDisasmPredCountImm(uint8_t imm);
958 
963 unsigned int sveDecodePredCount(uint8_t imm, unsigned int num_elems);
964 
969 uint64_t sveExpandFpImmAddSub(uint8_t imm, uint8_t size);
970 
976 uint64_t sveExpandFpImmMaxMin(uint8_t imm, uint8_t size);
977 
982 uint64_t sveExpandFpImmMul(uint8_t imm, uint8_t size);
983 
984 } // namespace ArmISA
985 } // namespace gem5
986 
987 #endif // __ARCH_ARM_INSTS_SVE_HH__
gem5::ArmISA::SveAdrOp::dest
IntRegIndex dest
Definition: sve.hh:596
gem5::ArmISA::SveTblOp
SVE table lookup/permute using vector of element indices (TBL)
Definition: sve.hh:716
gem5::ArmISA::SveBinImmPredOp::imm
uint64_t imm
Definition: sve.hh:292
gem5::ArmISA::SveIndexIIOp
Index generation instruction, immediate operands.
Definition: sve.hh:60
gem5::ArmISA::SveUnaryWideImmUnpredOp::imm
uint64_t imm
Definition: sve.hh:235
gem5::ArmISA::SveBinImmUnpredConstrOp::dest
IntRegIndex dest
Definition: sve.hh:273
gem5::ArmISA::SveDotProdOp::SveDotProdOp
SveDotProdOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2)
Definition: sve.hh:905
gem5::ArmISA::SveReducOp
SVE reductions.
Definition: sve.hh:498
gem5::ArmISA::SveUnaryPredOp
Unary, constructive, predicated (merging) SVE instruction.
Definition: sve.hh:199
gem5::ArmISA::SveTerImmUnpredOp
Ternary with immediate, destructive, unpredicated SVE instruction.
Definition: sve.hh:480
gem5::ArmISA::SveTerImmUnpredOp::op2
IntRegIndex op2
Definition: sve.hh:483
gem5::ArmISA::SveTblOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:639
gem5::ArmISA::SveUnaryPredOp::dest
IntRegIndex dest
Definition: sve.hh:202
gem5::ArmISA::sveExpandFpImmMaxMin
uint64_t sveExpandFpImmMaxMin(uint8_t imm, uint8_t size)
Expand 1-bit floating-point immediate to 0.0 or 1.0 (FMAX, FMAXNM, FMIN, FMINNM).
Definition: sve.cc:932
gem5::ArmISA::SveIndexRIOp::op1
IntRegIndex op1
Definition: sve.hh:98
gem5::ArmISA::SvePtrueOp::imm
uint8_t imm
Definition: sve.hh:534
gem5::ArmISA::SvePredCountPredOp::dest
IntRegIndex dest
Definition: sve.hh:152
gem5::ArmISA::sveDisasmPredCountImm
std::string sveDisasmPredCountImm(uint8_t imm)
Returns the symbolic name associated with pattern imm for PTRUE(S) instructions.
Definition: sve.cc:835
gem5::ArmISA::SveCmpOp::op2
IntRegIndex op2
Definition: sve.hh:431
gem5::ArmISA::SveTblOp::op1
IntRegIndex op1
Definition: sve.hh:720
gem5::ArmISA::SveIndexRROp::SveIndexRROp
SveIndexRROp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2)
Definition: sve.hh:118
gem5::ArmISA::SveUnaryWideImmUnpredOp::SveUnaryWideImmUnpredOp
SveUnaryWideImmUnpredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, uint64_t _imm)
Definition: sve.hh:237
gem5::ArmISA::SveDotProdIdxOp::imm
uint64_t imm
Definition: sve.hh:882
gem5::ArmISA::SveBinIdxUnpredOp::index
uint8_t index
Definition: sve.hh:379
gem5::ArmISA::SveIndexRROp::op2
IntRegIndex op2
Definition: sve.hh:116
gem5::ArmISA::SveWImplicitSrcDstOp
SVE unary predicate instructions with implicit destination operand.
Definition: sve.hh:812
gem5::ArmISA::SveAdrOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:517
gem5::ArmISA::SveBinImmUnpredConstrOp::imm
uint64_t imm
Definition: sve.hh:274
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::ArmISA::SveUnarySca2VecUnpredOp::op1
IntRegIndex op1
Definition: sve.hh:863
gem5::ArmISA::SveBinImmIdxUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:734
gem5::ArmISA::SveWhileOp
While predicate generation SVE instruction.
Definition: sve.hh:167
gem5::ArmISA::SveBinUnpredOp
Binary, unpredicated SVE instruction with indexed operand.
Definition: sve.hh:359
gem5::ArmISA::SveIndexIIOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:96
gem5::ArmISA::SvePredUnaryWImplicitDstOp::SvePredUnaryWImplicitDstOp
SvePredUnaryWImplicitDstOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _op1)
Definition: sve.hh:802
gem5::ArmISA::SveComplexOp::dest
IntRegIndex dest
Definition: sve.hh:920
gem5::ArmISA::SveAdrOp::offsetFormat
SveAdrOffsetFormat offsetFormat
Definition: sve.hh:598
gem5::ArmISA::SvePtrueOp::SvePtrueOp
SvePtrueOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, uint8_t _imm)
Definition: sve.hh:536
gem5::ArmISA::SvePartBrkOp::op1
IntRegIndex op1
Definition: sve.hh:640
gem5::ArmISA::SveIndexRIOp::dest
IntRegIndex dest
Definition: sve.hh:97
gem5::ArmISA::SveIntCmpOp
Integer compare SVE instruction.
Definition: sve.hh:547
gem5::ArmISA::SveIndexRROp::op1
IntRegIndex op1
Definition: sve.hh:115
gem5::ArmISA::SvePredLogicalOp::gp
IntRegIndex gp
Definition: sve.hh:396
gem5::ArmISA::SveBinDestrPredOp::op2
IntRegIndex op2
Definition: sve.hh:326
gem5::ArmISA::SveBinUnpredOp::op1
IntRegIndex op1
Definition: sve.hh:362
gem5::ArmISA::SvePredBinPermOp::op1
IntRegIndex op1
Definition: sve.hh:414
gem5::ArmISA::sveDecodePredCount
unsigned int sveDecodePredCount(uint8_t imm, unsigned int num_elems)
Returns the actual number of elements active for PTRUE(S) instructions.
Definition: sve.cc:867
gem5::ArmISA::SveBinImmIdxUnpredOp::op1
IntRegIndex op1
Definition: sve.hh:845
gem5::ArmISA::SveSelectOp::scalar
bool scalar
Definition: sve.hh:680
gem5::ArmISA::SveUnaryPredPredOp::gp
IntRegIndex gp
Definition: sve.hh:703
gem5::ArmISA::SveBinWideImmUnpredOp::imm
uint64_t imm
Definition: sve.hh:309
gem5::ArmISA::SveIndexIROp::op2
IntRegIndex op2
Definition: sve.hh:82
gem5::ArmISA::SvePredBinPermOp::dest
IntRegIndex dest
Definition: sve.hh:414
gem5::ArmISA::SveUnaryWideImmPredOp::gp
IntRegIndex gp
Definition: sve.hh:254
gem5::ArmISA::SveDotProdOp::op1
IntRegIndex op1
Definition: sve.hh:901
gem5::ArmISA::SveIndexIIOp::SveIndexIIOp
SveIndexIIOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, int8_t _imm1, int8_t _imm2)
Definition: sve.hh:67
gem5::ArmISA::SvePredCountPredOp::SvePredCountPredOp
SvePredCountPredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp)
Definition: sve.hh:156
gem5::ArmISA::SveWhileOp::srcIs32b
bool srcIs32b
Definition: sve.hh:171
gem5::ArmISA::SvePartBrkOp
Partition break SVE instruction.
Definition: sve.hh:635
gem5::ArmISA::SveBinConstrPredOp::gp
IntRegIndex gp
Definition: sve.hh:343
gem5::ArmISA::SveBinImmUnpredConstrOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:230
gem5::ArmISA::SvePredType::NONE
@ NONE
gem5::ArmISA::SveWhileOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:146
gem5::ArmISA::SvePredCountOp::srcIs32b
bool srcIs32b
Definition: sve.hh:134
gem5::ArmISA::SvePartBrkPropOp::op2
IntRegIndex op2
Definition: sve.hh:659
gem5::ArmISA::svePredTypeToStr
const char * svePredTypeToStr(SvePredType pt)
Returns the specifier for the predication type pt as a string.
Definition: sve.cc:48
gem5::ArmISA::SvePredType::SELECT
@ SELECT
gem5::ArmISA::SvePartBrkOp::gp
IntRegIndex gp
Definition: sve.hh:639
gem5::ArmISA::SveUnaryPredOp::gp
IntRegIndex gp
Definition: sve.hh:202
gem5::ArmISA::SveWhileOp::op2
IntRegIndex op2
Definition: sve.hh:170
gem5::ArmISA::SveBinImmIdxUnpredOp::imm
uint64_t imm
Definition: sve.hh:846
gem5::ArmISA::SveBinImmIdxUnpredOp::SveBinImmIdxUnpredOp
SveBinImmIdxUnpredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm)
Definition: sve.hh:848
gem5::ArmISA::SveBinWideImmUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:260
gem5::ArmISA::SveTerImmUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:421
gem5::ArmISA::SvePredCountPredOp
Definition: sve.hh:149
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::SveBinImmUnpredDestrOp::imm
uint64_t imm
Definition: sve.hh:829
gem5::ArmISA::SvePredType
SvePredType
Definition: sve.hh:48
gem5::ArmISA::SveAdrOp::op1
IntRegIndex op1
Definition: sve.hh:596
gem5::ArmISA::SveElemCountOp::dest
IntRegIndex dest
Definition: sve.hh:616
gem5::ArmISA::SveUnpackOp::SveUnpackOp
SveUnpackOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1)
Definition: sve.hh:739
gem5::ArmISA::SveIntCmpOp::SveIntCmpOp
SveIntCmpOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _gp, bool _op2IsWide=false)
Definition: sve.hh:555
gem5::ArmISA::SveIntCmpImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:501
gem5::ArmISA::SveUnaryPredPredOp
SVE unary operation on predicate (predicated)
Definition: sve.hh:698
gem5::ArmISA::SvePredUnaryWImplicitSrcPredOp::SvePredUnaryWImplicitSrcPredOp
SvePredUnaryWImplicitSrcPredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp)
Definition: sve.hh:786
gem5::ArmISA::SveCmpImmOp::SveCmpImmOp
SveCmpImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm, IntRegIndex _gp)
Definition: sve.hh:451
gem5::ArmISA::SveCompTermOp
Compare and terminate loop SVE instruction.
Definition: sve.hh:184
gem5::ArmISA::SvePredCountPredOp::gp
IntRegIndex gp
Definition: sve.hh:154
gem5::ArmISA::SveTerImmUnpredOp::imm
uint64_t imm
Definition: sve.hh:484
gem5::ArmISA::SveElemCountOp::imm
uint8_t imm
Definition: sve.hh:618
gem5::ArmISA::SveElemCountOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:541
gem5::ArmISA::SveBinImmPredOp::gp
IntRegIndex gp
Definition: sve.hh:291
gem5::ArmISA::SveUnaryWideImmPredOp::dest
IntRegIndex dest
Definition: sve.hh:252
gem5::ArmISA::SvePartBrkPropOp
Partition break with propagation SVE instruction.
Definition: sve.hh:654
gem5::ArmISA::SveElemCountOp::esize
uint8_t esize
Definition: sve.hh:621
gem5::ArmISA::SveBinImmPredOp
Binary with immediate, destructive, predicated (merging) SVE instruction.
Definition: sve.hh:288
gem5::ArmISA::SveComplexIdxOp::SveComplexIdxOp
SveComplexIdxOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, uint8_t _rot, uint8_t _imm)
Definition: sve.hh:943
gem5::ArmISA::SveDotProdOp
SVE dot product instruction (vectors)
Definition: sve.hh:898
gem5::ArmISA::SveComplexOp::op2
IntRegIndex op2
Definition: sve.hh:920
gem5::ArmISA::SveSelectOp::dest
IntRegIndex dest
Definition: sve.hh:676
gem5::ArmISA::SveComplexIdxOp::rot
uint8_t rot
Definition: sve.hh:940
gem5::ArmISA::SveSelectOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:599
gem5::ArmISA::SveOrdReducOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:451
gem5::ArmISA::SveCmpOp
SVE compare instructions, predicated (zeroing).
Definition: sve.hh:428
gem5::ArmISA::SveComplexIdxOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:816
gem5::ArmISA::SveBinWideImmUnpredOp::SveBinWideImmUnpredOp
SveBinWideImmUnpredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, uint64_t _imm)
Definition: sve.hh:311
gem5::ArmISA::SveBinImmPredOp::SveBinImmPredOp
SveBinImmPredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, uint64_t _imm, IntRegIndex _gp)
Definition: sve.hh:294
gem5::ArmISA::SveUnaryPredOp::op1
IntRegIndex op1
Definition: sve.hh:202
gem5::ArmISA::SveDotProdIdxOp::op2
IntRegIndex op2
Definition: sve.hh:881
gem5::ArmISA::SveSelectOp::gp
IntRegIndex gp
Definition: sve.hh:678
gem5::ArmISA::SveCompTermOp::SveCompTermOp
SveCompTermOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2)
Definition: sve.hh:189
gem5::ArmISA::SvePredLogicalOp::op1
IntRegIndex op1
Definition: sve.hh:396
gem5::ArmISA::SveIndexRIOp::imm2
int8_t imm2
Definition: sve.hh:99
gem5::ArmISA::SveAdrOp::SveAdrOffsetPacked
@ SveAdrOffsetPacked
Definition: sve.hh:590
gem5::ArmISA::SveAdrOp::op2
IntRegIndex op2
Definition: sve.hh:596
gem5::ArmISA::SveIntCmpOp::gp
IntRegIndex gp
Definition: sve.hh:552
gem5::ArmISA::SveUnaryPredPredOp::SveUnaryPredPredOp
SveUnaryPredPredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp)
Definition: sve.hh:705
gem5::ArmISA::SveUnaryWideImmUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:234
gem5::ArmISA::SvePredTestOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:664
gem5::ArmISA::SveIntCmpImmOp
Integer compare with immediate SVE instruction.
Definition: sve.hh:566
gem5::ArmISA::SveIntCmpOp::op1
IntRegIndex op1
Definition: sve.hh:551
gem5::ArmISA::SveWhileOp::op1
IntRegIndex op1
Definition: sve.hh:170
gem5::ArmISA::SveTerPredOp::dest
IntRegIndex dest
Definition: sve.hh:466
gem5::ArmISA::SvePredTestOp
SVE predicate test.
Definition: sve.hh:749
gem5::ArmISA::SveUnaryPredOp::SveUnaryPredOp
SveUnaryPredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp)
Definition: sve.hh:204
gem5::ArmISA::SveBinImmUnpredConstrOp::SveBinImmUnpredConstrOp
SveBinImmUnpredConstrOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm)
Definition: sve.hh:276
gem5::ArmISA::SveBinDestrPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:274
gem5::ArmISA::SveTerPredOp::gp
IntRegIndex gp
Definition: sve.hh:466
gem5::ArmISA::SveComplexIdxOp
SVE Complex Instructions (indexed)
Definition: sve.hh:936
gem5::ArmISA::SveIntCmpImmOp::SveIntCmpImmOp
SveIntCmpImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, int64_t _imm, IntRegIndex _gp)
Definition: sve.hh:574
gem5::ArmISA::SveBinImmUnpredDestrOp::SveBinImmUnpredDestrOp
SveBinImmUnpredDestrOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm)
Definition: sve.hh:831
gem5::ArmISA::SveWhileOp::SveWhileOp
SveWhileOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, bool _srcIs32b)
Definition: sve.hh:173
gem5::ArmISA::SveBinImmUnpredConstrOp
Binary with immediate, destructive, unpredicated SVE instruction.
Definition: sve.hh:270
gem5::ArmISA::SveSelectOp::op1
IntRegIndex op1
Definition: sve.hh:677
gem5::ArmISA::SveAdrOp::SveAdrOffsetFormat
SveAdrOffsetFormat
Definition: sve.hh:588
gem5::ArmISA::SvePtrueOp::dest
IntRegIndex dest
Definition: sve.hh:533
gem5::ArmISA::SveBinDestrPredOp
Binary, destructive, predicated (merging) SVE instruction.
Definition: sve.hh:323
gem5::ArmISA::SvePredType::MERGE
@ MERGE
gem5::ArmISA::SvePredUnaryWImplicitSrcPredOp::dest
IntRegIndex dest
Definition: sve.hh:783
gem5::ArmISA::SveTerPredOp::op2
IntRegIndex op2
Definition: sve.hh:466
gem5::ArmISA::SvePredBinPermOp
Predicate binary permute instruction.
Definition: sve.hh:411
gem5::ArmISA::SveBinImmUnpredDestrOp
SVE vector - immediate binary operation.
Definition: sve.hh:824
gem5::ArmISA::SveIndexRIOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:119
gem5::ArmISA::SvePredType::ZERO
@ ZERO
gem5::ArmISA::SveUnarySca2VecUnpredOp::simdFp
bool simdFp
Definition: sve.hh:864
gem5::ArmISA::SveIndexIIOp::imm1
int8_t imm1
Definition: sve.hh:64
gem5::ArmISA::SveBinIdxUnpredOp
Binary, unpredicated SVE instruction.
Definition: sve.hh:375
gem5::ArmISA::SveCmpImmOp::gp
IntRegIndex gp
Definition: sve.hh:448
gem5::ArmISA::SveUnpackOp
SVE unpack and widen predicate.
Definition: sve.hh:733
gem5::ArmISA::SvePartBrkPropOp::gp
IntRegIndex gp
Definition: sve.hh:660
gem5::ArmISA::SvePredBinPermOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:360
gem5::ArmISA::sveExpandFpImmAddSub
uint64_t sveExpandFpImmAddSub(uint8_t imm, uint8_t size)
Expand 1-bit floating-point immediate to 0.5 or 1.0 (FADD, FSUB, FSUBR).
Definition: sve.cc:910
gem5::ArmISA::SveBinConstrPredOp::dest
IntRegIndex dest
Definition: sve.hh:343
gem5::ArmISA::SvePartBrkPropOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:583
gem5::ArmISA::SvePredUnaryWImplicitSrcOp::dest
IntRegIndex dest
Definition: sve.hh:768
gem5::ArmISA::SveCmpOp::op1
IntRegIndex op1
Definition: sve.hh:431
gem5::ArmISA::SveUnaryPredPredOp::op1
IntRegIndex op1
Definition: sve.hh:702
gem5::ArmISA::SveTblOp::SveTblOp
SveTblOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2)
Definition: sve.hh:723
gem5::ArmISA::SveComplexIdxOp::dest
IntRegIndex dest
Definition: sve.hh:939
gem5::ArmISA::SveBinConstrPredOp::op1
IntRegIndex op1
Definition: sve.hh:343
gem5::ArmISA::SveElemCountOp::SveElemCountOp
SveElemCountOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, uint8_t _pattern, uint8_t _imm, bool _dstIsVec, bool _dstIs32b)
Definition: sve.hh:623
gem5::ArmISA::SveDotProdIdxOp::op1
IntRegIndex op1
Definition: sve.hh:881
gem5::ArmISA::SveTblOp::op2
IntRegIndex op2
Definition: sve.hh:721
gem5::ArmISA::SveIndexRROp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:132
gem5::ArmISA::SveReducOp::SveReducOp
SveReducOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp)
Definition: sve.hh:503
gem5::ArmISA::SveComplexIdxOp::op2
IntRegIndex op2
Definition: sve.hh:939
gem5::ArmISA::SveReducOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:437
gem5::ArmISA::SveUnaryWideImmUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:203
gem5::ArmISA::SveTerPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:405
gem5::ArmISA::SveBinImmIdxUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:845
gem5::ArmISA::SveDotProdOp::esize
uint8_t esize
Definition: sve.hh:902
gem5::ArmISA::SveTerImmUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:483
gem5::ArmISA::SveIndexIIOp::dest
IntRegIndex dest
Definition: sve.hh:63
gem5::ArmISA::SveComplexOp::SveComplexOp
SveComplexOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _gp, uint8_t _rot)
Definition: sve.hh:924
gem5::ArmISA::SvePtrueOp
PTRUE, PTRUES.
Definition: sve.hh:530
gem5::ArmISA::SvePredTestOp::SvePredTestOp
SvePredTestOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _op1, IntRegIndex _gp)
Definition: sve.hh:755
gem5::ArmISA::SvePredBinPermOp::op2
IntRegIndex op2
Definition: sve.hh:414
gem5::ArmISA::SveIndexIIOp::imm2
int8_t imm2
Definition: sve.hh:65
gem5::ArmISA::SveBinUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:309
gem5::ArmISA::SveIntCmpOp::dest
IntRegIndex dest
Definition: sve.hh:550
gem5::ArmISA::SveUnaryPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:177
gem5::ArmISA::SveAdrOp::mult
uint8_t mult
Definition: sve.hh:597
gem5::ArmISA::SveCompTermOp::op1
IntRegIndex op1
Definition: sve.hh:187
gem5::ArmISA::SveIndexRIOp::SveIndexRIOp
SveIndexRIOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, int8_t _imm2)
Definition: sve.hh:101
gem5::ArmISA::SvePredUnaryWImplicitSrcOp::SvePredUnaryWImplicitSrcOp
SvePredUnaryWImplicitSrcOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest)
Definition: sve.hh:770
gem5::ArmISA::SveComplexOp::op1
IntRegIndex op1
Definition: sve.hh:920
gem5::ArmISA::SvePredTestOp::gp
IntRegIndex gp
Definition: sve.hh:753
gem5::ArmISA::SveTblOp::dest
IntRegIndex dest
Definition: sve.hh:719
gem5::ArmISA::SveUnaryWideImmPredOp::SveUnaryWideImmPredOp
SveUnaryWideImmPredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, uint64_t _imm, IntRegIndex _gp, bool _isMerging)
Definition: sve.hh:258
gem5::ArmISA::SvePartBrkPropOp::SvePartBrkPropOp
SvePartBrkPropOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _gp)
Definition: sve.hh:662
gem5::ArmISA::SveBinConstrPredOp::predType
SvePredType predType
Definition: sve.hh:344
gem5::ArmISA::SveIntCmpImmOp::gp
IntRegIndex gp
Definition: sve.hh:572
gem5::ArmISA::SvePredLogicalOp
Predicate logical instruction.
Definition: sve.hh:393
gem5::ArmISA::SveUnpackOp::op1
IntRegIndex op1
Definition: sve.hh:737
gem5::ArmISA::SveElemCountOp::dstIsVec
bool dstIsVec
Definition: sve.hh:619
gem5::ArmISA::SveElemCountOp::dstIs32b
bool dstIs32b
Definition: sve.hh:620
gem5::ArmISA::SveBinDestrPredOp::dest
IntRegIndex dest
Definition: sve.hh:326
gem5::ArmISA::SveUnaryUnpredOp::SveUnaryUnpredOp
SveUnaryUnpredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1)
Definition: sve.hh:220
gem5::ArmISA::SveIndexIROp::SveIndexIROp
SveIndexIROp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, int8_t _imm1, IntRegIndex _op2)
Definition: sve.hh:84
gem5::ArmISA::SveBinImmIdxUnpredOp
Binary with immediate index, destructive, unpredicated SVE instruction.
Definition: sve.hh:842
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::SvePredUnaryWImplicitSrcPredOp::gp
IntRegIndex gp
Definition: sve.hh:784
gem5::ArmISA::SveBinIdxUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:378
gem5::ArmISA::SveBinConstrPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:290
gem5::ArmISA::SveBinConstrPredOp
Binary, constructive, predicated SVE instruction.
Definition: sve.hh:340
gem5::ArmISA::SveUnaryPredPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:625
gem5::ArmISA::SveUnaryUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:191
gem5::ArmISA::SvePredCountOp::SvePredCountOp
SvePredCountOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, bool _srcIs32b=false, bool _destIsVec=false)
Definition: sve.hh:137
gem5::ArmISA::SvePartBrkOp::dest
IntRegIndex dest
Definition: sve.hh:638
gem5::ArmISA::SveUnaryWideImmUnpredOp
Unary with wide immediate, constructive, unpredicated SVE instruction.
Definition: sve.hh:231
gem5::ArmISA::SveUnpackOp::dest
IntRegIndex dest
Definition: sve.hh:736
gem5::ArmISA::SveWImplicitSrcDstOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:709
gem5::ArmISA::SveBinImmUnpredDestrOp::op1
IntRegIndex op1
Definition: sve.hh:828
gem5::ArmISA::SveComplexOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:796
gem5::ArmISA::SveUnaryWideImmPredOp
Unary with wide immediate, constructive, predicated SVE instruction.
Definition: sve.hh:249
gem5::ArmISA::SveBinIdxUnpredOp::SveBinIdxUnpredOp
SveBinIdxUnpredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, uint8_t _index)
Definition: sve.hh:381
gem5::ArmISA::SveCmpImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:389
gem5::ArmISA::SveCmpOp::SveCmpOp
SveCmpOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _gp)
Definition: sve.hh:433
gem5::ArmISA::SveSelectOp
Scalar element select SVE instruction.
Definition: sve.hh:673
gem5::ArmISA::SveDotProdIdxOp::esize
uint8_t esize
Definition: sve.hh:883
gem5::ArmISA::SveCompTermOp::op2
IntRegIndex op2
Definition: sve.hh:187
gem5::ArmISA::SvePredTestOp::op1
IntRegIndex op1
Definition: sve.hh:752
gem5::ArmISA::sveExpandFpImmMul
uint64_t sveExpandFpImmMul(uint8_t imm, uint8_t size)
Expand 1-bit floating-point immediate to 0.5 or 2.0 (FMUL).
Definition: sve.cc:951
gem5::ArmISA::SveTerPredOp::op1
IntRegIndex op1
Definition: sve.hh:466
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::SvePredUnaryWImplicitSrcPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:686
gem5::ArmISA::SveBinImmPredOp::dest
IntRegIndex dest
Definition: sve.hh:291
gem5::ArmISA::SvePredLogicalOp::SvePredLogicalOp
SvePredLogicalOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _gp, bool _isSel=false)
Definition: sve.hh:399
gem5::ArmISA::SvePartBrkPropOp::op1
IntRegIndex op1
Definition: sve.hh:658
gem5::ArmISA::SveCmpOp::gp
IntRegIndex gp
Definition: sve.hh:431
gem5::ArmISA::SvePredCountOp::destIsVec
bool destIsVec
Definition: sve.hh:135
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::SveAdrOp::SveAdrOp
SveAdrOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, uint8_t _mult, SveAdrOffsetFormat _offsetFormat)
Definition: sve.hh:600
gem5::ArmISA::SveSelectOp::simdFp
bool simdFp
Definition: sve.hh:681
gem5::ArmISA::SveIntCmpImmOp::imm
int64_t imm
Definition: sve.hh:571
gem5::ArmISA::SvePartBrkOp::SvePartBrkOp
SvePartBrkOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _op1, bool _isMerging)
Definition: sve.hh:643
gem5::ArmISA::SvePredUnaryWImplicitSrcPredOp
SVE unary predicate instructions, predicated, with implicit source operand.
Definition: sve.hh:780
gem5::ArmISA::SvePtrueOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:467
gem5::ArmISA::SvePartBrkOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:569
gem5::ArmISA::SvePredCountOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:75
gem5::ArmISA::SveIndexIROp::imm1
int8_t imm1
Definition: sve.hh:81
gem5::ArmISA::SveIndexRROp
Definition: sve.hh:111
gem5::ArmISA::SvePredCountOp
Definition: sve.hh:129
gem5::ArmISA::SveCompTermOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:165
gem5::ArmISA::SveAdrOp::SveAdrOffsetUnpackedSigned
@ SveAdrOffsetUnpackedSigned
Definition: sve.hh:591
gem5::ArmISA::SveBinUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:362
gem5::ArmISA::SveAdrOp
ADR.
Definition: sve.hh:585
gem5::ArmISA::SveBinUnpredOp::op2
IntRegIndex op2
Definition: sve.hh:362
static_inst.hh
gem5::ArmISA::SveCmpOp::dest
IntRegIndex dest
Definition: sve.hh:431
gem5::ArmISA::SveBinImmPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:244
gem5::ArmISA::SveCmpImmOp
SVE compare-with-immediate instructions, predicated (zeroing).
Definition: sve.hh:445
gem5::ArmISA::SveBinConstrPredOp::SveBinConstrPredOp
SveBinConstrPredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _gp, SvePredType _predType)
Definition: sve.hh:346
gem5::ArmISA::SveIndexRIOp
Definition: sve.hh:94
gem5::ArmISA::SveBinUnpredOp::SveBinUnpredOp
SveBinUnpredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2)
Definition: sve.hh:364
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::SveIntCmpImmOp::op1
IntRegIndex op1
Definition: sve.hh:570
gem5::ArmISA::SvePredLogicalOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:340
gem5::ArmISA::SvePredUnaryWImplicitDstOp::op1
IntRegIndex op1
Definition: sve.hh:800
gem5::ArmISA::SveIndexRROp::dest
IntRegIndex dest
Definition: sve.hh:114
gem5::ArmISA::SveBinDestrPredOp::gp
IntRegIndex gp
Definition: sve.hh:326
gem5::ArmISA::SveBinConstrPredOp::op2
IntRegIndex op2
Definition: sve.hh:343
gem5::ArmISA::SveCmpOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:374
gem5::ArmISA::SveUnaryWideImmPredOp::isMerging
bool isMerging
Definition: sve.hh:256
gem5::ArmISA::SveCmpImmOp::op1
IntRegIndex op1
Definition: sve.hh:448
gem5::ArmISA::SvePredUnaryWImplicitDstOp
SVE unary predicate instructions with implicit destination operand.
Definition: sve.hh:797
gem5::ArmISA::SveWImplicitSrcDstOp::SveWImplicitSrcDstOp
SveWImplicitSrcDstOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: sve.hh:815
gem5::ArmISA::SveComplexIdxOp::imm
uint8_t imm
Definition: sve.hh:940
gem5::ArmISA::SveOrdReducOp::gp
IntRegIndex gp
Definition: sve.hh:517
gem5::ArmISA::SveIntCmpImmOp::dest
IntRegIndex dest
Definition: sve.hh:569
gem5::ArmISA::SveUnaryUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:218
gem5::ArmISA::SvePredLogicalOp::op2
IntRegIndex op2
Definition: sve.hh:396
gem5::ArmISA::SvePredCountPredOp::op1
IntRegIndex op1
Definition: sve.hh:153
gem5::ArmISA::SveIndexIROp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:107
gem5::ArmISA::SveReducOp::op1
IntRegIndex op1
Definition: sve.hh:501
gem5::ArmISA::SveSelectOp::conditional
bool conditional
Definition: sve.hh:679
gem5::ArmISA::SveUnaryWideImmPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:215
gem5::ArmISA::SveBinIdxUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:323
gem5::ArmISA::SveUnarySca2VecUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:863
gem5::ArmISA::SveIntCmpOp::op2
IntRegIndex op2
Definition: sve.hh:551
gem5::ArmISA::SvePredCountPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:61
gem5::ArmISA::SveSelectOp::scalar_width
size_t scalar_width
Definition: sve.hh:682
gem5::ArmISA::SveComplexOp::rot
uint8_t rot
Definition: sve.hh:921
gem5::ArmISA::SveDotProdOp::op2
IntRegIndex op2
Definition: sve.hh:901
gem5::ArmISA::SveReducOp::dest
IntRegIndex dest
Definition: sve.hh:501
gem5::ArmISA::SveBinImmUnpredDestrOp::dest
IntRegIndex dest
Definition: sve.hh:827
gem5::ArmISA::SveUnaryWideImmPredOp::imm
uint64_t imm
Definition: sve.hh:253
gem5::ArmISA::SveUnarySca2VecUnpredOp::SveUnarySca2VecUnpredOp
SveUnarySca2VecUnpredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, bool _simdFp)
Definition: sve.hh:866
gem5::ArmISA::SveElemCountOp::pattern
uint8_t pattern
Definition: sve.hh:617
gem5::ArmISA::SveComplexIdxOp::op1
IntRegIndex op1
Definition: sve.hh:939
gem5::ArmISA::SvePredUnaryWImplicitSrcOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:676
gem5::ArmISA::SveCmpImmOp::dest
IntRegIndex dest
Definition: sve.hh:448
gem5::ArmISA::SveBinIdxUnpredOp::op2
IntRegIndex op2
Definition: sve.hh:378
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::SveUnpackOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:652
gem5::ArmISA::SvePredCountOp::dest
IntRegIndex dest
Definition: sve.hh:132
gem5::ArmISA::SveUnaryPredPredOp::dest
IntRegIndex dest
Definition: sve.hh:701
gem5::ArmISA::SveOrdReducOp::SveOrdReducOp
SveOrdReducOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp)
Definition: sve.hh:519
gem5::ArmISA::SvePredCountOp::gp
IntRegIndex gp
Definition: sve.hh:133
gem5::ArmISA::SveUnarySca2VecUnpredOp
Unary unpredicated scalar to vector instruction.
Definition: sve.hh:860
gem5::ArmISA::SvePredUnaryWImplicitDstOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:699
gem5::ArmISA::SveBinImmUnpredConstrOp::op1
IntRegIndex op1
Definition: sve.hh:273
gem5::ArmISA::SveBinWideImmUnpredOp
Binary with wide immediate, destructive, unpredicated SVE instruction.
Definition: sve.hh:305
gem5::ArmISA::SveComplexOp::gp
IntRegIndex gp
Definition: sve.hh:920
gem5::ArmISA::SveTerImmUnpredOp::SveTerImmUnpredOp
SveTerImmUnpredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op2, uint64_t _imm)
Definition: sve.hh:486
gem5::ArmISA::SveUnaryUnpredOp::op1
IntRegIndex op1
Definition: sve.hh:218
gem5::ArmISA::SveBinImmUnpredDestrOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:718
gem5::ArmISA::SvePartBrkPropOp::dest
IntRegIndex dest
Definition: sve.hh:657
gem5::ArmISA::SveWhileOp::dest
IntRegIndex dest
Definition: sve.hh:170
gem5::ArmISA::SvePredUnaryWImplicitSrcOp
SVE unary predicate instructions with implicit source operand.
Definition: sve.hh:765
gem5::ArmISA::SveIndexIROp::dest
IntRegIndex dest
Definition: sve.hh:80
gem5::ArmISA::SvePredLogicalOp::isSel
bool isSel
Definition: sve.hh:397
gem5::ArmISA::SveUnarySca2VecUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:749
gem5::ArmISA::SvePartBrkOp::isMerging
bool isMerging
Definition: sve.hh:641
gem5::ArmISA::SveOrdReducOp::op1
IntRegIndex op1
Definition: sve.hh:517
gem5::ArmISA::SveBinDestrPredOp::SveBinDestrPredOp
SveBinDestrPredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op2, IntRegIndex _gp)
Definition: sve.hh:328
gem5::ArmISA::SveSelectOp::SveSelectOp
SveSelectOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp, bool _conditional, bool _scalar, bool _simdFp)
Definition: sve.hh:684
gem5::ArmISA::SveDotProdOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:782
gem5::ArmISA::SveBinIdxUnpredOp::op1
IntRegIndex op1
Definition: sve.hh:378
gem5::ArmISA::SveAdrOp::SveAdrOffsetUnpackedUnsigned
@ SveAdrOffsetUnpackedUnsigned
Definition: sve.hh:592
gem5::ArmISA::SveReducOp::gp
IntRegIndex gp
Definition: sve.hh:501
gem5::ArmISA::SveDotProdOp::dest
IntRegIndex dest
Definition: sve.hh:901
gem5::ArmISA::SveBinWideImmUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:308
gem5::ArmISA::SveIntCmpOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:481
gem5::ArmISA::SvePredBinPermOp::SvePredBinPermOp
SvePredBinPermOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2)
Definition: sve.hh:416
gem5::ArmISA::SveOrdReducOp::dest
IntRegIndex dest
Definition: sve.hh:517
gem5::ArmISA::SveDotProdIdxOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:765
gem5::ArmISA::SveDotProdIdxOp
SVE dot product instruction (indexed)
Definition: sve.hh:878
gem5::ArmISA::SveTerPredOp
Ternary, destructive, predicated (merging) SVE instruction.
Definition: sve.hh:463
gem5::ArmISA::SveUnaryUnpredOp
Unary, constructive, unpredicated SVE instruction.
Definition: sve.hh:215
gem5::ArmISA::SveComplexOp
SVE Complex Instructions (vectors)
Definition: sve.hh:917
gem5::ArmISA::SveOrdReducOp
SVE ordered reductions.
Definition: sve.hh:514
gem5::ArmISA::SvePredLogicalOp::dest
IntRegIndex dest
Definition: sve.hh:396
gem5::ArmISA::SveTerPredOp::SveTerPredOp
SveTerPredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _gp)
Definition: sve.hh:468
gem5::ArmISA::SveIndexIROp
Definition: sve.hh:77
gem5::ArmISA::SveDotProdIdxOp::dest
IntRegIndex dest
Definition: sve.hh:881
gem5::ArmISA::SveElemCountOp
Element count SVE instruction.
Definition: sve.hh:613
gem5::ArmISA::SveCmpImmOp::imm
uint64_t imm
Definition: sve.hh:449
gem5::ArmISA::SveDotProdIdxOp::SveDotProdIdxOp
SveDotProdIdxOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm)
Definition: sve.hh:886
gem5::ArmISA::SveIntCmpOp::op2IsWide
bool op2IsWide
Definition: sve.hh:553

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