gem5  v21.1.0.2
sve.cc
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1 /*
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37 
38 // TODO: add support for suffixes of register specifiers in disasm strings.
39 
40 #include "arch/arm/insts/sve.hh"
41 
42 namespace gem5
43 {
44 
45 namespace ArmISA {
46 
47 const char*
49 {
50  switch (pt) {
51  case SvePredType::MERGE:
52  return "m";
53  case SvePredType::ZERO:
54  return "z";
55  default:
56  return "";
57  }
58 }
59 
60 std::string
62  const loader::SymbolTable *symtab) const
63 {
64  std::stringstream ss;
65  printMnemonic(ss, "", false);
67  ccprintf(ss, ", ");
69  ccprintf(ss, ", ");
71  return ss.str();
72 }
73 
74 std::string
76  Addr pc, const loader::SymbolTable *symtab) const
77 {
78  std::stringstream ss;
79  printMnemonic(ss, "", false);
80  if (destIsVec) {
81  printVecReg(ss, dest, true);
82  } else {
84  }
85  ccprintf(ss, ", ");
86  uint8_t opWidth = 64;
88  ccprintf(ss, ", ");
89  if (srcIs32b)
90  opWidth = 32;
91  printIntReg(ss, dest, opWidth);
92  return ss.str();
93 }
94 
95 std::string
97  Addr pc, const loader::SymbolTable *symtab) const
98 {
99  std::stringstream ss;
100  printMnemonic(ss, "", false);
101  printVecReg(ss, dest, true);
102  ccprintf(ss, ", #%d, #%d", imm1, imm2);
103  return ss.str();
104 }
105 
106 std::string
108  Addr pc, const loader::SymbolTable *symtab) const
109 {
110  std::stringstream ss;
111  printMnemonic(ss, "", false);
112  printVecReg(ss, dest, true);
113  ccprintf(ss, ", #%d, ", imm1);
114  printIntReg(ss, op2);
115  return ss.str();
116 }
117 
118 std::string
120  Addr pc, const loader::SymbolTable *symtab) const
121 {
122  std::stringstream ss;
123  printMnemonic(ss, "", false);
124  printVecReg(ss, dest, true);
125  ccprintf(ss, ", ");
126  printIntReg(ss, op1);
127  ccprintf(ss, ", #%d", imm2);
128  return ss.str();
129 }
130 
131 std::string
133  Addr pc, const loader::SymbolTable *symtab) const
134 {
135  std::stringstream ss;
136  printMnemonic(ss, "", false);
137  printVecReg(ss, dest, true);
138  ccprintf(ss, ", ");
139  printIntReg(ss, op1);
140  ccprintf(ss, ", ");
141  printIntReg(ss, op2);
142  return ss.str();
143 }
144 
145 std::string
147  Addr pc, const loader::SymbolTable *symtab) const
148 {
149  std::stringstream ss;
150  printMnemonic(ss, "", false);
152  ccprintf(ss, ", ");
153  uint8_t opWidth;
154  if (srcIs32b)
155  opWidth = 32;
156  else
157  opWidth = 64;
158  printIntReg(ss, op1, opWidth);
159  ccprintf(ss, ", ");
160  printIntReg(ss, op2, opWidth);
161  return ss.str();
162 }
163 
164 std::string
166  Addr pc, const loader::SymbolTable *symtab) const
167 {
168  std::stringstream ss;
169  printMnemonic(ss, "", false);
170  printIntReg(ss, op1);
171  ccprintf(ss, ", ");
172  printIntReg(ss, op2);
173  return ss.str();
174 }
175 
176 std::string
178  Addr pc, const loader::SymbolTable *symtab) const
179 {
180  std::stringstream ss;
181  printMnemonic(ss, "", false);
182  printVecReg(ss, dest, true);
183  ccprintf(ss, ", ");
185  ccprintf(ss, "/m, ");
186  printVecReg(ss, op1, true);
187  return ss.str();
188 }
189 
190 std::string
192  Addr pc, const loader::SymbolTable *symtab) const
193 {
194  std::stringstream ss;
195  printMnemonic(ss, "", false);
196  printVecReg(ss, dest, true);
197  ccprintf(ss, ", ");
198  printVecReg(ss, op1, true);
199  return ss.str();
200 }
201 
202 std::string
204  Addr pc, const loader::SymbolTable *symtab) const
205 {
206  std::stringstream ss;
207  printMnemonic(ss, "", false);
208  printVecReg(ss, dest, true);
209  ccprintf(ss, ", #");
210  ss << imm;
211  return ss.str();
212 }
213 
214 std::string
216  Addr pc, const loader::SymbolTable *symtab) const
217 {
218  std::stringstream ss;
219  printMnemonic(ss, "", false);
220  printVecReg(ss, dest, true);
221  ccprintf(ss, ", ");
223  ccprintf(ss, (isMerging ? "/m" : "/z"));
224  ccprintf(ss, ", #");
225  ss << imm;
226  return ss.str();
227 }
228 
229 std::string
231  Addr pc, const loader::SymbolTable *symtab) const
232 {
233  std::stringstream ss;
234  printMnemonic(ss, "", false);
235  printVecReg(ss, dest, true);
236  ccprintf(ss, ", ");
238  ccprintf(ss, ", #");
239  ss << imm;
240  return ss.str();
241 }
242 
243 std::string
245  Addr pc, const loader::SymbolTable *symtab) const
246 {
247  std::stringstream ss;
248  printMnemonic(ss, "", false);
249  printVecReg(ss, dest, true);
250  ccprintf(ss, ", ");
252  ccprintf(ss, "/m, ");
253  printVecReg(ss, dest, true);
254  ccprintf(ss, ", #");
255  ss << imm;
256  return ss.str();
257 }
258 
259 std::string
261  Addr pc, const loader::SymbolTable *symtab) const
262 {
263  std::stringstream ss;
264  printMnemonic(ss, "", false);
265  printVecReg(ss, dest, true);
266  ccprintf(ss, ", ");
267  printVecReg(ss, dest, true);
268  ccprintf(ss, ", #");
269  ss << imm;
270  return ss.str();
271 }
272 
273 std::string
275  Addr pc, const loader::SymbolTable *symtab) const
276 {
277  std::stringstream ss;
278  printMnemonic(ss, "", false);
279  printVecReg(ss, dest, true);
280  ccprintf(ss, ", ");
282  ccprintf(ss, "/m, ");
283  printVecReg(ss, dest, true);
284  ccprintf(ss, ", ");
285  printVecReg(ss, op2, true);
286  return ss.str();
287 }
288 
289 std::string
291  Addr pc, const loader::SymbolTable *symtab) const
292 {
293  std::stringstream ss;
294  printMnemonic(ss, "", false);
295  printVecReg(ss, dest, true);
296  ccprintf(ss, ", ");
300  }
301  ccprintf(ss, ", ");
302  printVecReg(ss, op1, true);
303  ccprintf(ss, ", ");
304  printVecReg(ss, op2, true);
305  return ss.str();
306 }
307 
308 std::string
310  Addr pc, const loader::SymbolTable *symtab) const
311 {
312  std::stringstream ss;
313  printMnemonic(ss, "", false);
314  printVecReg(ss, dest, true);
315  ccprintf(ss, ", ");
316  printVecReg(ss, op1, true);
317  ccprintf(ss, ", ");
318  printVecReg(ss, op2, true);
319  return ss.str();
320 }
321 
322 std::string
324  Addr pc, const loader::SymbolTable *symtab) const
325 {
326  std::stringstream ss;
327  printMnemonic(ss, "", false);
328  printVecReg(ss, dest, true);
329  ccprintf(ss, ", ");
330  printVecReg(ss, op1, true);
331  ccprintf(ss, ", ");
332  printVecReg(ss, op2, true);
333  ccprintf(ss, "[");
334  ss << (uint64_t)index;
335  ccprintf(ss, "]");
336  return ss.str();
337 }
338 
339 std::string
341  Addr pc, const loader::SymbolTable *symtab) const
342 {
343  std::stringstream ss;
344  printMnemonic(ss, "", false);
345  printVecReg(ss, dest, true);
346  ccprintf(ss, ", ");
348  if (isSel) {
349  ccprintf(ss, ", ");
350  } else {
351  ccprintf(ss, "/z, ");
352  }
354  ccprintf(ss, ", ");
356  return ss.str();
357 }
358 
359 std::string
361  Addr pc, const loader::SymbolTable *symtab) const
362 {
363  std::stringstream ss;
364  printMnemonic(ss, "", false);
366  ccprintf(ss, ", ");
368  ccprintf(ss, ", ");
370  return ss.str();
371 }
372 
373 std::string
375 {
376  std::stringstream ss;
377  printMnemonic(ss, "", false);
379  ccprintf(ss, ", ");
381  ccprintf(ss, "/z, ");
382  printVecReg(ss, op1, true);
383  ccprintf(ss, ", ");
384  printVecReg(ss, op2, true);
385  return ss.str();
386 }
387 
388 std::string
390  Addr pc, const loader::SymbolTable *symtab) const
391 {
392  std::stringstream ss;
393  printMnemonic(ss, "", false);
395  ccprintf(ss, ", ");
397  ccprintf(ss, "/z, ");
398  printVecReg(ss, op1, true);
399  ccprintf(ss, ", #");
400  ss << imm;
401  return ss.str();
402 }
403 
404 std::string
406  Addr pc, const loader::SymbolTable *symtab) const
407 {
408  std::stringstream ss;
409  printMnemonic(ss, "", false);
410  printVecReg(ss, dest, true);
411  ccprintf(ss, ", ");
413  ccprintf(ss, "/m, ");
414  printVecReg(ss, op1, true);
415  ccprintf(ss, ", ");
416  printVecReg(ss, op2, true);
417  return ss.str();
418 }
419 
420 std::string
422  Addr pc, const loader::SymbolTable *symtab) const
423 {
424  std::stringstream ss;
425  printMnemonic(ss, "", false);
426  printVecReg(ss, dest, true);
427  ccprintf(ss, ", ");
428  printVecReg(ss, dest, true);
429  ccprintf(ss, ", ");
430  printVecReg(ss, op2, true);
431  ccprintf(ss, ", #");
432  ss << imm;
433  return ss.str();
434 }
435 
436 std::string
438  Addr pc, const loader::SymbolTable *symtab) const
439 {
440  std::stringstream ss;
441  printMnemonic(ss, "", false);
443  ccprintf(ss, ", ");
445  ccprintf(ss, ", ");
446  printVecReg(ss, op1, true);
447  return ss.str();
448 }
449 
450 std::string
452  Addr pc, const loader::SymbolTable *symtab) const
453 {
454  std::stringstream ss;
455  printMnemonic(ss, "", false);
457  ccprintf(ss, ", ");
459  ccprintf(ss, ", ");
461  ccprintf(ss, ", ");
462  printVecReg(ss, op1, true);
463  return ss.str();
464 }
465 
466 std::string
468  Addr pc, const loader::SymbolTable *symtab) const
469 {
470  std::stringstream ss;
471  printMnemonic(ss, "", false);
473  if (imm != 0x1f) {
474  ccprintf(ss, ", ");
476  }
477  return ss.str();
478 }
479 
480 std::string
482  Addr pc, const loader::SymbolTable *symtab) const
483 {
484  std::stringstream ss;
485  printMnemonic(ss, "", false);
487  ccprintf(ss, ", ");
489  ccprintf(ss, "/z, ");
490  printVecReg(ss, op1, true);
491  ccprintf(ss, ", ");
492  if (op2IsWide) {
493  printVecReg(ss, op2, true);
494  } else {
495  printVecReg(ss, op2, true);
496  }
497  return ss.str();
498 }
499 
500 std::string
502  Addr pc, const loader::SymbolTable *symtab) const
503 {
504  std::stringstream ss;
505  printMnemonic(ss, "", false);
507  ccprintf(ss, "/z, ");
509  ccprintf(ss, ", ");
510  printVecReg(ss, op1, true);
511  ccprintf(ss, ", #");
512  ss << imm;
513  return ss.str();
514 }
515 
516 std::string
518 {
519  std::stringstream ss;
520  printMnemonic(ss, "", false);
521  printVecReg(ss, dest, true);
522  ccprintf(ss, ", [");
523  printVecReg(ss, op1, true);
524  ccprintf(ss, ", ");
525  printVecReg(ss, op2, true);
527  ccprintf(ss, ", sxtw");
529  ccprintf(ss, ", uxtw");
530  } else if (mult != 1) {
531  ccprintf(ss, ", lsl");
532  }
533  if (mult != 1) {
534  ss << __builtin_ctz(mult);
535  }
536  ccprintf(ss, "]");
537  return ss.str();
538 }
539 
540 std::string
542  Addr pc, const loader::SymbolTable *symtab) const
543 {
544  static const char suffix[9] =
545  {'\0', 'b', 'h', '\0', 'w', '\0', '\0', '\0', 'd'};
546  std::stringstream ss;
547  ss << " " << mnemonic << suffix[esize] << " ";
548  if (dstIsVec) {
549  printVecReg(ss, dest, true);
550  } else {
551  if (dstIs32b) {
552  printIntReg(ss, dest, 32);
553  } else {
554  printIntReg(ss, dest, 64);
555  }
556  }
557  if (pattern != 0x1f) {
558  ccprintf(ss, ", ");
560  if (imm != 1) {
561  ccprintf(ss, ", mul #");
562  ss << std::to_string(imm);
563  }
564  }
565  return ss.str();
566 }
567 
568 std::string
570  Addr pc, const loader::SymbolTable *symtab) const
571 {
572  std::stringstream ss;
573  printMnemonic(ss, "", false);
575  ccprintf(ss, ", ");
577  ccprintf(ss, isMerging ? "/m, " : "/z, ");
579  return ss.str();
580 }
581 
582 std::string
584  Addr pc, const loader::SymbolTable *symtab) const
585 {
586  std::stringstream ss;
587  printMnemonic(ss, "", false);
589  ccprintf(ss, ", ");
591  ccprintf(ss, "/z, ");
593  ccprintf(ss, ", ");
595  return ss.str();
596 }
597 
598 std::string
600  Addr pc, const loader::SymbolTable *symtab) const
601 {
602  std::stringstream ss;
603  printMnemonic(ss, "", false);
604  if (scalar)
606  else if (simdFp)
608  else
609  printVecReg(ss, dest, true);
610  ccprintf(ss, ", ");
612  if (conditional) {
613  ccprintf(ss, ", ");
614  if (scalar)
616  else
617  printVecReg(ss, dest, true);
618  }
619  ccprintf(ss, ", ");
620  printVecReg(ss, op1, true);
621  return ss.str();
622 }
623 
624 std::string
626  Addr pc, const loader::SymbolTable *symtab) const
627 {
628  std::stringstream ss;
629  printMnemonic(ss, "", false);
631  ccprintf(ss, ", ");
633  ccprintf(ss, ", ");
635  return ss.str();
636 }
637 
638 std::string
640 {
641  std::stringstream ss;
642  printMnemonic(ss, "", false);
643  printVecReg(ss, dest, true);
644  ccprintf(ss, ", { ");
645  printVecReg(ss, op1, true);
646  ccprintf(ss, " }, ");
647  printVecReg(ss, op2, true);
648  return ss.str();
649 }
650 
651 std::string
653  Addr pc, const loader::SymbolTable *symtab) const
654 {
655  std::stringstream ss;
656  printMnemonic(ss, "", false);
658  ccprintf(ss, ", ");
660  return ss.str();
661 }
662 
663 std::string
665  Addr pc, const loader::SymbolTable *symtab) const
666 {
667  std::stringstream ss;
668  printMnemonic(ss, "", false);
670  ccprintf(ss, ", ");
672  return ss.str();
673 }
674 
675 std::string
677  Addr pc, const loader::SymbolTable *symtab) const
678 {
679  std::stringstream ss;
680  printMnemonic(ss, "", false);
682  return ss.str();
683 }
684 
685 std::string
687  Addr pc, const loader::SymbolTable *symtab) const
688 {
689  std::stringstream ss;
690  printMnemonic(ss, "", false);
692  ccprintf(ss, ", ");
694  ccprintf(ss, "/z, ");
695  return ss.str();
696 }
697 
698 std::string
700  Addr pc, const loader::SymbolTable *symtab) const
701 {
702  std::stringstream ss;
703  printMnemonic(ss, "", false);
705  return ss.str();
706 }
707 
708 std::string
710  Addr pc, const loader::SymbolTable *symtab) const
711 {
712  std::stringstream ss;
713  printMnemonic(ss, "", false);
714  return ss.str();
715 }
716 
717 std::string
719  Addr pc, const loader::SymbolTable *symtab) const
720 {
721  std::stringstream ss;
722  printMnemonic(ss, "", false);
723  printVecReg(ss, dest, true);
724  ccprintf(ss, ", ");
725  printVecReg(ss, dest, true);
726  ccprintf(ss, ", ");
727  printVecReg(ss, op1, true);
728  ccprintf(ss, ", #");
729  ss << imm;
730  return ss.str();
731 }
732 
733 std::string
735  Addr pc, const loader::SymbolTable *symtab) const
736 {
737  std::stringstream ss;
738  printMnemonic(ss, "", false);
739  printVecReg(ss, dest, true);
740  ccprintf(ss, ", ");
741  printVecReg(ss, op1, true);
742  ccprintf(ss, "[");
743  ss << imm;
744  ccprintf(ss, "]");
745  return ss.str();
746 }
747 
748 std::string
750  Addr pc, const loader::SymbolTable *symtab) const
751 {
752  std::stringstream ss;
753  printMnemonic(ss, "", false);
754  printVecReg(ss, dest, true);
755  ccprintf(ss, ", ");
756  if (simdFp) {
757  printFloatReg(ss, op1);
758  } else {
759  printIntReg(ss, op1);
760  }
761  return ss.str();
762 }
763 
764 std::string
766  Addr pc, const loader::SymbolTable *symtab) const
767 {
768  std::stringstream ss;
769  printMnemonic(ss, "", false);
770  printVecReg(ss, dest, true);
771  ccprintf(ss, ", ");
772  printVecReg(ss, op1, true);
773  ccprintf(ss, ", ");
774  printVecReg(ss, op2, true);
775  ccprintf(ss, "[");
776  ccprintf(ss, "%lu", imm);
777  ccprintf(ss, "]");
778  return ss.str();
779 }
780 
781 std::string
783  Addr pc, const loader::SymbolTable *symtab) const
784 {
785  std::stringstream ss;
786  printMnemonic(ss, "", false);
787  printVecReg(ss, dest, true);
788  ccprintf(ss, ", ");
789  printVecReg(ss, op1, true);
790  ccprintf(ss, ", ");
791  printVecReg(ss, op2, true);
792  return ss.str();
793 }
794 
795 std::string
797  Addr pc, const loader::SymbolTable *symtab) const
798 {
799  std::stringstream ss;
800  printMnemonic(ss, "", false);
802  ccprintf(ss, ", ");
804  ccprintf(ss, "/m, ");
806  ccprintf(ss, ", ");
808  ccprintf(ss, ", #");
809  const char* rotstr[4] = {"0", "90", "180", "270"};
810  ccprintf(ss, rotstr[rot]);
811 
812  return ss.str();
813 }
814 
815 std::string
817  Addr pc, const loader::SymbolTable *symtab) const
818 {
819  std::stringstream ss;
820  printMnemonic(ss, "", false);
822  ccprintf(ss, ", ");
824  ccprintf(ss, ", ");
826  ccprintf(ss, "[");
827  ss << imm;
828  ccprintf(ss, "], #");
829  const char* rotstr[4] = {"0", "90", "180", "270"};
830  ccprintf(ss, rotstr[rot]);
831  return ss.str();
832 }
833 
834 std::string
836 {
837  switch (imm) {
838  case 0x0:
839  return "POW2";
840  case 0x1:
841  case 0x2:
842  case 0x3:
843  case 0x4:
844  case 0x5:
845  case 0x6:
846  case 0x7:
847  return "VL" + std::to_string(imm);
848  case 0x8:
849  case 0x9:
850  case 0xa:
851  case 0xb:
852  case 0xc:
853  case 0xd:
854  return "VL" + std::to_string(1 << ((imm & 0x7) + 3));
855  case 0x1d:
856  return "MUL4";
857  case 0x1e:
858  return "MUL3";
859  case 0x1f:
860  return "ALL";
861  default:
862  return "#" + std::to_string(imm);
863  }
864 }
865 
866 unsigned int
867 sveDecodePredCount(uint8_t imm, unsigned int num_elems)
868 {
869  assert(num_elems > 0);
870 
871  switch (imm) {
872  case 0x0:
873  // POW2
874  return 1 << (31 - __builtin_clz((uint32_t) num_elems));
875  case 0x1:
876  case 0x2:
877  case 0x3:
878  case 0x4:
879  case 0x5:
880  case 0x6:
881  case 0x7:
882  // VL1, VL2, VL3, VL4, VL5, VL6, VL7
883  return (num_elems >= imm) ? imm : 0;
884  case 0x8:
885  case 0x9:
886  case 0xa:
887  case 0xb:
888  case 0xc:
889  case 0xd:
890  // VL8, VL16, VL32, VL64, VL128, VL256
891  {
892  unsigned int pcount = 1 << ((imm & 0x7) + 3);
893  return (num_elems >= pcount) ? pcount : 0;
894  }
895  case 0x1d:
896  // MUL4
897  return num_elems - (num_elems % 4);
898  case 0x1e:
899  // MUL3
900  return num_elems - (num_elems % 3);
901  case 0x1f:
902  // ALL
903  return num_elems;
904  default:
905  return 0;
906  }
907 }
908 
909 uint64_t
910 sveExpandFpImmAddSub(uint8_t imm, uint8_t size)
911 {
912  static constexpr uint16_t fpOne16 = 0x3c00;
913  static constexpr uint16_t fpPointFive16 = 0x3800;
914  static constexpr uint32_t fpOne32 = 0x3f800000;
915  static constexpr uint32_t fpPointFive32 = 0x3f000000;
916  static constexpr uint64_t fpOne64 = 0x3ff0000000000000;
917  static constexpr uint64_t fpPointFive64 = 0x3fe0000000000000;
918 
919  switch (size) {
920  case 0x1:
921  return imm ? fpOne16 : fpPointFive16;
922  case 0x2:
923  return imm ? fpOne32 : fpPointFive32;
924  case 0x3:
925  return imm ? fpOne64 : fpPointFive64;
926  default:
927  panic("Unsupported size");
928  }
929 }
930 
931 uint64_t
932 sveExpandFpImmMaxMin(uint8_t imm, uint8_t size)
933 {
934  static constexpr uint16_t fpOne16 = 0x3c00;
935  static constexpr uint32_t fpOne32 = 0x3f800000;
936  static constexpr uint64_t fpOne64 = 0x3ff0000000000000;
937 
938  switch (size) {
939  case 0x1:
940  return imm ? fpOne16 : 0x0;
941  case 0x2:
942  return imm ? fpOne32 : 0x0;
943  case 0x3:
944  return imm ? fpOne64 : 0x0;
945  default:
946  panic("Unsupported size");
947  }
948 }
949 
950 uint64_t
951 sveExpandFpImmMul(uint8_t imm, uint8_t size)
952 {
953  static constexpr uint16_t fpTwo16 = 0x4000;
954  static constexpr uint16_t fpPointFive16 = 0x3800;
955  static constexpr uint32_t fpTwo32 = 0x40000000;
956  static constexpr uint32_t fpPointFive32 = 0x3f000000;
957  static constexpr uint64_t fpTwo64 = 0x4000000000000000;
958  static constexpr uint64_t fpPointFive64 = 0x3fe0000000000000;
959 
960  switch (size) {
961  case 0x1:
962  return imm ? fpTwo16 : fpPointFive16;
963  case 0x2:
964  return imm ? fpTwo32 : fpPointFive32;
965  case 0x3:
966  return imm ? fpTwo64 : fpPointFive64;
967  default:
968  panic("Unsupported size");
969  }
970 }
971 
972 } // namespace ArmISA
973 } // namespace gem5
gem5::ArmISA::SveAdrOp::dest
IntRegIndex dest
Definition: sve.hh:596
gem5::ArmISA::SveBinImmPredOp::imm
uint64_t imm
Definition: sve.hh:292
gem5::ArmISA::SveUnaryWideImmUnpredOp::imm
uint64_t imm
Definition: sve.hh:235
gem5::ArmISA::SveBinImmUnpredConstrOp::dest
IntRegIndex dest
Definition: sve.hh:273
gem5::ArmISA::SveTerImmUnpredOp::op2
IntRegIndex op2
Definition: sve.hh:483
gem5::ArmISA::ArmStaticInst::printVecReg
void printVecReg(std::ostream &os, RegIndex reg_idx, bool isSveVecReg=false) const
Definition: static_inst.cc:351
gem5::ArmISA::SveTblOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:639
gem5::ArmISA::SveUnaryPredOp::dest
IntRegIndex dest
Definition: sve.hh:202
gem5::ArmISA::sveExpandFpImmMaxMin
uint64_t sveExpandFpImmMaxMin(uint8_t imm, uint8_t size)
Expand 1-bit floating-point immediate to 0.0 or 1.0 (FMAX, FMAXNM, FMIN, FMINNM).
Definition: sve.cc:932
gem5::ArmISA::SveIndexRIOp::op1
IntRegIndex op1
Definition: sve.hh:98
gem5::ArmISA::SvePtrueOp::imm
uint8_t imm
Definition: sve.hh:534
gem5::ArmISA::SvePredCountPredOp::dest
IntRegIndex dest
Definition: sve.hh:152
gem5::ArmISA::sveDisasmPredCountImm
std::string sveDisasmPredCountImm(uint8_t imm)
Returns the symbolic name associated with pattern imm for PTRUE(S) instructions.
Definition: sve.cc:835
gem5::ArmISA::SveCmpOp::op2
IntRegIndex op2
Definition: sve.hh:431
gem5::ArmISA::SveTblOp::op1
IntRegIndex op1
Definition: sve.hh:720
gem5::ArmISA::SveDotProdIdxOp::imm
uint64_t imm
Definition: sve.hh:882
gem5::ArmISA::SveBinIdxUnpredOp::index
uint8_t index
Definition: sve.hh:379
gem5::ArmISA::SveIndexRROp::op2
IntRegIndex op2
Definition: sve.hh:116
gem5::ArmISA::SveAdrOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:517
gem5::ArmISA::SveBinImmUnpredConstrOp::imm
uint64_t imm
Definition: sve.hh:274
gem5::ArmISA::SveUnarySca2VecUnpredOp::op1
IntRegIndex op1
Definition: sve.hh:863
gem5::ArmISA::SveBinImmIdxUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:734
gem5::ArmISA::SveIndexIIOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:96
gem5::ArmISA::SveComplexOp::dest
IntRegIndex dest
Definition: sve.hh:920
gem5::ArmISA::SveAdrOp::offsetFormat
SveAdrOffsetFormat offsetFormat
Definition: sve.hh:598
gem5::ArmISA::SvePartBrkOp::op1
IntRegIndex op1
Definition: sve.hh:640
gem5::ArmISA::SveIndexRIOp::dest
IntRegIndex dest
Definition: sve.hh:97
gem5::ArmISA::SveIndexRROp::op1
IntRegIndex op1
Definition: sve.hh:115
gem5::ArmISA::SvePredLogicalOp::gp
IntRegIndex gp
Definition: sve.hh:396
gem5::ArmISA::SveBinDestrPredOp::op2
IntRegIndex op2
Definition: sve.hh:326
gem5::ArmISA::SveBinUnpredOp::op1
IntRegIndex op1
Definition: sve.hh:362
gem5::ArmISA::SvePredBinPermOp::op1
IntRegIndex op1
Definition: sve.hh:414
gem5::ArmISA::sveDecodePredCount
unsigned int sveDecodePredCount(uint8_t imm, unsigned int num_elems)
Returns the actual number of elements active for PTRUE(S) instructions.
Definition: sve.cc:867
gem5::ArmISA::SveBinImmIdxUnpredOp::op1
IntRegIndex op1
Definition: sve.hh:845
gem5::ArmISA::SveSelectOp::scalar
bool scalar
Definition: sve.hh:680
gem5::ArmISA::SveUnaryPredPredOp::gp
IntRegIndex gp
Definition: sve.hh:703
gem5::ArmISA::SveBinWideImmUnpredOp::imm
uint64_t imm
Definition: sve.hh:309
gem5::ArmISA::SveIndexIROp::op2
IntRegIndex op2
Definition: sve.hh:82
gem5::ArmISA::SvePredBinPermOp::dest
IntRegIndex dest
Definition: sve.hh:414
gem5::ArmISA::SveUnaryWideImmPredOp::gp
IntRegIndex gp
Definition: sve.hh:254
gem5::ArmISA::SveDotProdOp::op1
IntRegIndex op1
Definition: sve.hh:901
gem5::ArmISA::ArmStaticInst::printMnemonic
void printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
Definition: static_inst.cc:377
sc_dt::to_string
const std::string to_string(sc_enc enc)
Definition: sc_fxdefs.cc:91
gem5::ArmISA::SveWhileOp::srcIs32b
bool srcIs32b
Definition: sve.hh:171
gem5::ArmISA::SveBinConstrPredOp::gp
IntRegIndex gp
Definition: sve.hh:343
gem5::ArmISA::SveBinImmUnpredConstrOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:230
gem5::ArmISA::SveWhileOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:146
gem5::ArmISA::SvePredCountOp::srcIs32b
bool srcIs32b
Definition: sve.hh:134
gem5::ArmISA::SvePartBrkPropOp::op2
IntRegIndex op2
Definition: sve.hh:659
gem5::ArmISA::svePredTypeToStr
const char * svePredTypeToStr(SvePredType pt)
Returns the specifier for the predication type pt as a string.
Definition: sve.cc:48
gem5::ArmISA::SvePartBrkOp::gp
IntRegIndex gp
Definition: sve.hh:639
gem5::ArmISA::SveUnaryPredOp::gp
IntRegIndex gp
Definition: sve.hh:202
gem5::ArmISA::SveWhileOp::op2
IntRegIndex op2
Definition: sve.hh:170
gem5::ArmISA::SveBinImmIdxUnpredOp::imm
uint64_t imm
Definition: sve.hh:846
gem5::ArmISA::SveBinWideImmUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:260
gem5::ArmISA::SveTerImmUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:421
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::SveBinImmUnpredDestrOp::imm
uint64_t imm
Definition: sve.hh:829
gem5::ArmISA::SvePredType
SvePredType
Definition: sve.hh:48
gem5::ArmISA::SveAdrOp::op1
IntRegIndex op1
Definition: sve.hh:596
gem5::ArmISA::SveElemCountOp::dest
IntRegIndex dest
Definition: sve.hh:616
gem5::ArmISA::SveIntCmpImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:501
gem5::ArmISA::SvePredCountPredOp::gp
IntRegIndex gp
Definition: sve.hh:154
gem5::ArmISA::SveTerImmUnpredOp::imm
uint64_t imm
Definition: sve.hh:484
gem5::ArmISA::SveElemCountOp::imm
uint8_t imm
Definition: sve.hh:618
gem5::ArmISA::SveElemCountOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:541
gem5::ArmISA::SveBinImmPredOp::gp
IntRegIndex gp
Definition: sve.hh:291
gem5::ArmISA::SveUnaryWideImmPredOp::dest
IntRegIndex dest
Definition: sve.hh:252
gem5::ArmISA::SveElemCountOp::esize
uint8_t esize
Definition: sve.hh:621
gem5::ArmISA::SveComplexOp::op2
IntRegIndex op2
Definition: sve.hh:920
gem5::ArmISA::SveSelectOp::dest
IntRegIndex dest
Definition: sve.hh:676
gem5::ArmISA::SveComplexIdxOp::rot
uint8_t rot
Definition: sve.hh:940
gem5::ArmISA::SveSelectOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:599
gem5::ArmISA::SveOrdReducOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:451
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ArmISA::SveComplexIdxOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:816
gem5::ArmISA::SveUnaryPredOp::op1
IntRegIndex op1
Definition: sve.hh:202
gem5::ArmISA::SveDotProdIdxOp::op2
IntRegIndex op2
Definition: sve.hh:881
gem5::ArmISA::SveSelectOp::gp
IntRegIndex gp
Definition: sve.hh:678
gem5::ArmISA::SvePredLogicalOp::op1
IntRegIndex op1
Definition: sve.hh:396
gem5::ArmISA::SveIndexRIOp::imm2
int8_t imm2
Definition: sve.hh:99
gem5::ArmISA::SveAdrOp::op2
IntRegIndex op2
Definition: sve.hh:596
gem5::ArmISA::SveIntCmpOp::gp
IntRegIndex gp
Definition: sve.hh:552
gem5::ArmISA::SveUnaryWideImmUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:234
gem5::ArmISA::SvePredTestOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:664
gem5::ArmISA::SveIntCmpOp::op1
IntRegIndex op1
Definition: sve.hh:551
gem5::ArmISA::SveWhileOp::op1
IntRegIndex op1
Definition: sve.hh:170
gem5::ArmISA::SveTerPredOp::dest
IntRegIndex dest
Definition: sve.hh:466
gem5::ArmISA::SveBinDestrPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:274
sve.hh
gem5::ArmISA::SveTerPredOp::gp
IntRegIndex gp
Definition: sve.hh:466
gem5::ArmISA::SveSelectOp::op1
IntRegIndex op1
Definition: sve.hh:677
gem5::ArmISA::SvePtrueOp::dest
IntRegIndex dest
Definition: sve.hh:533
gem5::ArmISA::SvePredType::MERGE
@ MERGE
gem5::ArmISA::SvePredUnaryWImplicitSrcPredOp::dest
IntRegIndex dest
Definition: sve.hh:783
gem5::ArmISA::SveTerPredOp::op2
IntRegIndex op2
Definition: sve.hh:466
gem5::ArmISA::SveIndexRIOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:119
gem5::ArmISA::SvePredType::ZERO
@ ZERO
gem5::ArmISA::SveUnarySca2VecUnpredOp::simdFp
bool simdFp
Definition: sve.hh:864
gem5::ArmISA::SveIndexIIOp::imm1
int8_t imm1
Definition: sve.hh:64
gem5::ArmISA::SveCmpImmOp::gp
IntRegIndex gp
Definition: sve.hh:448
gem5::ArmISA::SvePartBrkPropOp::gp
IntRegIndex gp
Definition: sve.hh:660
gem5::ArmISA::SvePredBinPermOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:360
gem5::ArmISA::sveExpandFpImmAddSub
uint64_t sveExpandFpImmAddSub(uint8_t imm, uint8_t size)
Expand 1-bit floating-point immediate to 0.5 or 1.0 (FADD, FSUB, FSUBR).
Definition: sve.cc:910
gem5::ArmISA::SveBinConstrPredOp::dest
IntRegIndex dest
Definition: sve.hh:343
gem5::ArmISA::SvePartBrkPropOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:583
gem5::ArmISA::SvePredUnaryWImplicitSrcOp::dest
IntRegIndex dest
Definition: sve.hh:768
gem5::ArmISA::SveCmpOp::op1
IntRegIndex op1
Definition: sve.hh:431
gem5::ArmISA::SveUnaryPredPredOp::op1
IntRegIndex op1
Definition: sve.hh:702
gem5::ArmISA::SveComplexIdxOp::dest
IntRegIndex dest
Definition: sve.hh:939
gem5::ArmISA::SveBinConstrPredOp::op1
IntRegIndex op1
Definition: sve.hh:343
gem5::ArmISA::SveDotProdIdxOp::op1
IntRegIndex op1
Definition: sve.hh:881
gem5::ArmISA::SveTblOp::op2
IntRegIndex op2
Definition: sve.hh:721
gem5::ArmISA::SveIndexRROp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:132
gem5::ArmISA::SveComplexIdxOp::op2
IntRegIndex op2
Definition: sve.hh:939
gem5::ArmISA::SveReducOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:437
gem5::ArmISA::SveUnaryWideImmUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:203
gem5::ArmISA::SveTerPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:405
gem5::ArmISA::SveBinImmIdxUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:845
gem5::ArmISA::SveTerImmUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:483
gem5::ArmISA::SveIndexIIOp::dest
IntRegIndex dest
Definition: sve.hh:63
gem5::ArmISA::SvePredBinPermOp::op2
IntRegIndex op2
Definition: sve.hh:414
gem5::ArmISA::SveIndexIIOp::imm2
int8_t imm2
Definition: sve.hh:65
gem5::ArmISA::SveBinUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:309
gem5::ArmISA::SveIntCmpOp::dest
IntRegIndex dest
Definition: sve.hh:550
gem5::ArmISA::SveUnaryPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:177
gem5::ArmISA::SveAdrOp::mult
uint8_t mult
Definition: sve.hh:597
gem5::ArmISA::SveCompTermOp::op1
IntRegIndex op1
Definition: sve.hh:187
gem5::ArmISA::SveComplexOp::op1
IntRegIndex op1
Definition: sve.hh:920
gem5::ArmISA::SvePredTestOp::gp
IntRegIndex gp
Definition: sve.hh:753
gem5::ArmISA::ArmStaticInst::printVecPredReg
void printVecPredReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:358
gem5::ArmISA::SveTblOp::dest
IntRegIndex dest
Definition: sve.hh:719
gem5::ArmISA::SveBinConstrPredOp::predType
SvePredType predType
Definition: sve.hh:344
gem5::ArmISA::SveIntCmpImmOp::gp
IntRegIndex gp
Definition: sve.hh:572
gem5::ArmISA::SveUnpackOp::op1
IntRegIndex op1
Definition: sve.hh:737
gem5::ArmISA::SveElemCountOp::dstIsVec
bool dstIsVec
Definition: sve.hh:619
gem5::ArmISA::SveElemCountOp::dstIs32b
bool dstIs32b
Definition: sve.hh:620
gem5::ArmISA::SveBinDestrPredOp::dest
IntRegIndex dest
Definition: sve.hh:326
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::SvePredUnaryWImplicitSrcPredOp::gp
IntRegIndex gp
Definition: sve.hh:784
gem5::ArmISA::SveBinIdxUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:378
gem5::ArmISA::SveBinConstrPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:290
gem5::ArmISA::SveUnaryPredPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:625
gem5::ArmISA::SveUnaryUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:191
gem5::ArmISA::SvePartBrkOp::dest
IntRegIndex dest
Definition: sve.hh:638
gem5::ArmISA::SveUnpackOp::dest
IntRegIndex dest
Definition: sve.hh:736
gem5::ArmISA::SveWImplicitSrcDstOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:709
gem5::ArmISA::SveBinImmUnpredDestrOp::op1
IntRegIndex op1
Definition: sve.hh:828
gem5::ArmISA::SveComplexOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:796
gem5::ArmISA::SveCmpImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:389
gem5::ArmISA::SveCompTermOp::op2
IntRegIndex op2
Definition: sve.hh:187
gem5::ArmISA::SvePredTestOp::op1
IntRegIndex op1
Definition: sve.hh:752
gem5::ArmISA::sveExpandFpImmMul
uint64_t sveExpandFpImmMul(uint8_t imm, uint8_t size)
Expand 1-bit floating-point immediate to 0.5 or 2.0 (FMUL).
Definition: sve.cc:951
gem5::ArmISA::SveTerPredOp::op1
IntRegIndex op1
Definition: sve.hh:466
gem5::ArmISA::SvePredUnaryWImplicitSrcPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:686
gem5::ArmISA::SveBinImmPredOp::dest
IntRegIndex dest
Definition: sve.hh:291
gem5::ArmISA::SvePartBrkPropOp::op1
IntRegIndex op1
Definition: sve.hh:658
gem5::ArmISA::SveCmpOp::gp
IntRegIndex gp
Definition: sve.hh:431
gem5::ArmISA::SvePredCountOp::destIsVec
bool destIsVec
Definition: sve.hh:135
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::SveSelectOp::simdFp
bool simdFp
Definition: sve.hh:681
gem5::ArmISA::SveIntCmpImmOp::imm
int64_t imm
Definition: sve.hh:571
gem5::ArmISA::SvePtrueOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:467
gem5::ArmISA::SvePartBrkOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:569
gem5::ArmISA::ArmStaticInst::printFloatReg
void printFloatReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:345
gem5::ArmISA::SvePredCountOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:75
gem5::ArmISA::SveIndexIROp::imm1
int8_t imm1
Definition: sve.hh:81
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:59
gem5::ArmISA::SveCompTermOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:165
gem5::ArmISA::SveAdrOp::SveAdrOffsetUnpackedSigned
@ SveAdrOffsetUnpackedSigned
Definition: sve.hh:591
gem5::ArmISA::SveBinUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:362
gem5::ArmISA::SveBinUnpredOp::op2
IntRegIndex op2
Definition: sve.hh:362
gem5::ArmISA::SveCmpOp::dest
IntRegIndex dest
Definition: sve.hh:431
gem5::ArmISA::SveBinImmPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:244
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::SveIntCmpImmOp::op1
IntRegIndex op1
Definition: sve.hh:570
gem5::ArmISA::SvePredLogicalOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:340
gem5::ArmISA::SvePredUnaryWImplicitDstOp::op1
IntRegIndex op1
Definition: sve.hh:800
gem5::ArmISA::SveIndexRROp::dest
IntRegIndex dest
Definition: sve.hh:114
gem5::ArmISA::SveBinDestrPredOp::gp
IntRegIndex gp
Definition: sve.hh:326
gem5::ArmISA::SveBinConstrPredOp::op2
IntRegIndex op2
Definition: sve.hh:343
gem5::ArmISA::SveCmpOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:374
gem5::ArmISA::SveUnaryWideImmPredOp::isMerging
bool isMerging
Definition: sve.hh:256
gem5::ArmISA::SveCmpImmOp::op1
IntRegIndex op1
Definition: sve.hh:448
gem5::ArmISA::SveComplexIdxOp::imm
uint8_t imm
Definition: sve.hh:940
gem5::ArmISA::SveOrdReducOp::gp
IntRegIndex gp
Definition: sve.hh:517
gem5::ArmISA::SveIntCmpImmOp::dest
IntRegIndex dest
Definition: sve.hh:569
gem5::ArmISA::SveUnaryUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:218
gem5::ArmISA::SvePredLogicalOp::op2
IntRegIndex op2
Definition: sve.hh:396
gem5::ArmISA::SvePredCountPredOp::op1
IntRegIndex op1
Definition: sve.hh:153
gem5::ArmISA::SveIndexIROp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:107
gem5::ArmISA::SveReducOp::op1
IntRegIndex op1
Definition: sve.hh:501
gem5::ArmISA::SveSelectOp::conditional
bool conditional
Definition: sve.hh:679
gem5::ArmISA::SveUnaryWideImmPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:215
gem5::ArmISA::SveBinIdxUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:323
gem5::ArmISA::SveUnarySca2VecUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:863
gem5::ArmISA::SveIntCmpOp::op2
IntRegIndex op2
Definition: sve.hh:551
gem5::ArmISA::SvePredCountPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:61
gem5::ArmISA::SveSelectOp::scalar_width
size_t scalar_width
Definition: sve.hh:682
gem5::ArmISA::SveComplexOp::rot
uint8_t rot
Definition: sve.hh:921
gem5::ArmISA::SveDotProdOp::op2
IntRegIndex op2
Definition: sve.hh:901
gem5::ArmISA::SveReducOp::dest
IntRegIndex dest
Definition: sve.hh:501
gem5::ArmISA::SveBinImmUnpredDestrOp::dest
IntRegIndex dest
Definition: sve.hh:827
gem5::ArmISA::SveUnaryWideImmPredOp::imm
uint64_t imm
Definition: sve.hh:253
gem5::ArmISA::SveElemCountOp::pattern
uint8_t pattern
Definition: sve.hh:617
gem5::ArmISA::ArmStaticInst::printIntReg
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:299
gem5::ArmISA::SveComplexIdxOp::op1
IntRegIndex op1
Definition: sve.hh:939
gem5::ArmISA::SvePredUnaryWImplicitSrcOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:676
gem5::ArmISA::SveCmpImmOp::dest
IntRegIndex dest
Definition: sve.hh:448
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5::ArmISA::SveBinIdxUnpredOp::op2
IntRegIndex op2
Definition: sve.hh:378
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::SveUnpackOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:652
gem5::ArmISA::SvePredCountOp::dest
IntRegIndex dest
Definition: sve.hh:132
gem5::ArmISA::SveUnaryPredPredOp::dest
IntRegIndex dest
Definition: sve.hh:701
gem5::ArmISA::SvePredCountOp::gp
IntRegIndex gp
Definition: sve.hh:133
gem5::ArmISA::SvePredUnaryWImplicitDstOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:699
gem5::ArmISA::SveBinImmUnpredConstrOp::op1
IntRegIndex op1
Definition: sve.hh:273
gem5::ArmISA::SveComplexOp::gp
IntRegIndex gp
Definition: sve.hh:920
gem5::ArmISA::SveUnaryUnpredOp::op1
IntRegIndex op1
Definition: sve.hh:218
gem5::ArmISA::SveBinImmUnpredDestrOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:718
gem5::ArmISA::SvePartBrkPropOp::dest
IntRegIndex dest
Definition: sve.hh:657
gem5::ArmISA::SveWhileOp::dest
IntRegIndex dest
Definition: sve.hh:170
gem5::ArmISA::SveIndexIROp::dest
IntRegIndex dest
Definition: sve.hh:80
gem5::ArmISA::SvePredLogicalOp::isSel
bool isSel
Definition: sve.hh:397
gem5::ArmISA::SveUnarySca2VecUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:749
gem5::ArmISA::SvePartBrkOp::isMerging
bool isMerging
Definition: sve.hh:641
gem5::ArmISA::SveOrdReducOp::op1
IntRegIndex op1
Definition: sve.hh:517
gem5::ArmISA::SveDotProdOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:782
gem5::ArmISA::SveBinIdxUnpredOp::op1
IntRegIndex op1
Definition: sve.hh:378
gem5::ArmISA::SveAdrOp::SveAdrOffsetUnpackedUnsigned
@ SveAdrOffsetUnpackedUnsigned
Definition: sve.hh:592
gem5::ArmISA::SveReducOp::gp
IntRegIndex gp
Definition: sve.hh:501
gem5::ArmISA::SveDotProdOp::dest
IntRegIndex dest
Definition: sve.hh:901
gem5::ArmISA::SveBinWideImmUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:308
gem5::ArmISA::SveIntCmpOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:481
gem5::ArmISA::SveOrdReducOp::dest
IntRegIndex dest
Definition: sve.hh:517
gem5::ArmISA::SveDotProdIdxOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:765
gem5::ArmISA::SvePredLogicalOp::dest
IntRegIndex dest
Definition: sve.hh:396
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::SveDotProdIdxOp::dest
IntRegIndex dest
Definition: sve.hh:881
gem5::ArmISA::SveCmpImmOp::imm
uint64_t imm
Definition: sve.hh:449
gem5::ArmISA::SveIntCmpOp::op2IsWide
bool op2IsWide
Definition: sve.hh:553

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