gem5  v22.0.0.1
static_inst.hh
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40 
41 #ifndef __ARCH_ARM_INSTS_STATICINST_HH__
42 #define __ARCH_ARM_INSTS_STATICINST_HH__
43 
44 #include <memory>
45 
46 #include "arch/arm/faults.hh"
47 #include "arch/arm/utility.hh"
48 #include "arch/arm/isa.hh"
49 #include "arch/arm/pcstate.hh"
50 #include "arch/arm/self_debug.hh"
51 #include "arch/arm/system.hh"
52 #include "base/trace.hh"
53 #include "cpu/exec_context.hh"
54 #include "cpu/static_inst.hh"
55 #include "cpu/thread_context.hh"
56 #include "sim/byteswap.hh"
57 #include "sim/full_system.hh"
58 
59 namespace gem5
60 {
61 
62 namespace ArmISA
63 {
64 
65 class ArmStaticInst : public StaticInst
66 {
67  protected:
68  bool aarch64;
69  uint8_t intWidth;
70 
71  int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
72  uint32_t type, uint32_t cfval) const;
73  int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
74  uint32_t type, uint32_t cfval) const;
75 
76  bool shift_carry_imm(uint32_t base, uint32_t shamt,
77  uint32_t type, uint32_t cfval) const;
78  bool shift_carry_rs(uint32_t base, uint32_t shamt,
79  uint32_t type, uint32_t cfval) const;
80 
81  int64_t shiftReg64(uint64_t base, uint64_t shiftAmt,
82  ArmShiftType type, uint8_t width) const;
83  int64_t extendReg64(uint64_t base, ArmExtendType type,
84  uint64_t shiftAmt, uint8_t width) const;
85 
86  template<int width>
87  static inline bool
88  saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
89  {
90  int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
91  if (bits(midRes, width) != bits(midRes, width - 1)) {
92  if (midRes > 0)
93  res = (1LL << (width - 1)) - 1;
94  else
95  res = -(1LL << (width - 1));
96  return true;
97  } else {
98  res = midRes;
99  return false;
100  }
101  }
102 
103  static inline bool
104  satInt(int32_t &res, int64_t op, int width)
105  {
106  width--;
107  if (op >= (1LL << width)) {
108  res = (1LL << width) - 1;
109  return true;
110  } else if (op < -(1LL << width)) {
111  res = -(1LL << width);
112  return true;
113  } else {
114  res = op;
115  return false;
116  }
117  }
118 
119  template<int width>
120  static inline bool
121  uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)
122  {
123  int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
124  if (midRes >= (1LL << width)) {
125  res = (1LL << width) - 1;
126  return true;
127  } else if (midRes < 0) {
128  res = 0;
129  return true;
130  } else {
131  res = midRes;
132  return false;
133  }
134  }
135 
136  static inline bool
137  uSatInt(int32_t &res, int64_t op, int width)
138  {
139  if (op >= (1LL << width)) {
140  res = (1LL << width) - 1;
141  return true;
142  } else if (op < 0) {
143  res = 0;
144  return true;
145  } else {
146  res = op;
147  return false;
148  }
149  }
150 
152 
153  // Constructor
154  ArmStaticInst(const char *mnem, ExtMachInst _machInst,
155  OpClass __opClass)
156  : StaticInst(mnem, __opClass), machInst(_machInst)
157  {
158  aarch64 = machInst.aarch64;
159  if (bits(machInst, 28, 24) == 0x10)
160  intWidth = 64; // Force 64-bit width for ADR/ADRP
161  else
162  intWidth = (aarch64 && bits(machInst, 31)) ? 64 : 32;
163  }
164 
167  void printIntReg(std::ostream &os, RegIndex reg_idx,
168  uint8_t opWidth = 0) const;
169  void printFloatReg(std::ostream &os, RegIndex reg_idx) const;
170  void printVecReg(std::ostream &os, RegIndex reg_idx,
171  bool isSveVecReg = false) const;
172  void printVecPredReg(std::ostream &os, RegIndex reg_idx) const;
173  void printCCReg(std::ostream &os, RegIndex reg_idx) const;
174  void printMiscReg(std::ostream &os, RegIndex reg_idx) const;
175  void printMnemonic(std::ostream &os,
176  const std::string &suffix = "",
177  bool withPred = true,
178  bool withCond64 = false,
179  ConditionCode cond64 = COND_UC) const;
180  void printTarget(std::ostream &os, Addr target,
181  const loader::SymbolTable *symtab) const;
182  void printCondition(std::ostream &os, unsigned code,
183  bool noImplicit=false) const;
184  void printMemSymbol(std::ostream &os, const loader::SymbolTable *symtab,
185  const std::string &prefix, const Addr addr,
186  const std::string &suffix) const;
187  void printShiftOperand(std::ostream &os, RegIndex rm,
188  bool immShift, uint32_t shiftAmt,
189  RegIndex rs, ArmShiftType type) const;
190  void printExtendOperand(bool firstOperand, std::ostream &os,
192  int64_t shiftAmt) const;
193  void printPFflags(std::ostream &os, int flag) const;
194 
195  void printDataInst(std::ostream &os, bool withImm) const;
196  void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
198  RegIndex rs, uint32_t shiftAmt, ArmShiftType type,
199  uint64_t imm) const;
200 
201  void
202  advancePC(PCStateBase &pcState) const override
203  {
204  pcState.as<PCState>().advance();
205  }
206 
207  void
208  advancePC(ThreadContext *tc) const override
209  {
210  PCState pc = tc->pcState().as<PCState>();
211  pc.advance();
212  tc->pcState(pc);
213  }
214 
215  uint64_t getEMI() const override { return machInst; }
216 
217  std::unique_ptr<PCStateBase>
218  buildRetPC(const PCStateBase &cur_pc,
219  const PCStateBase &call_pc) const override
220  {
221  PCStateBase *ret_pc = call_pc.clone();
222  ret_pc->as<PCState>().uEnd();
223  return std::unique_ptr<PCStateBase>{ret_pc};
224  }
225 
226  std::string generateDisassembly(
227  Addr pc, const loader::SymbolTable *symtab) const override;
228 
229  static void
231  {
233  sd->activateDebug();
234  }
235 
236  static inline uint32_t
237  cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr,
238  uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)
239  {
240  bool privileged = (cpsr.mode != MODE_USER);
241  bool haveVirt = ArmSystem::haveEL(tc, EL2);
242  bool isSecure = ArmISA::isSecure(tc);
243 
244  uint32_t bitMask = 0;
245 
246  if (affectState && byteMask==0xF){
247  activateBreakpoint(tc);
248  }
249  if (bits(byteMask, 3)) {
250  unsigned lowIdx = affectState ? 24 : 27;
251  bitMask = bitMask | mask(31, lowIdx);
252  }
253  if (bits(byteMask, 2)) {
254  bitMask = bitMask | mask(19, 16);
255  }
256  if (bits(byteMask, 1)) {
257  unsigned highIdx = affectState ? 15 : 9;
258  unsigned lowIdx = (privileged && (isSecure || scr.aw || haveVirt))
259  ? 8 : 9;
260  bitMask = bitMask | mask(highIdx, lowIdx);
261  }
262  if (bits(byteMask, 0)) {
263  if (privileged) {
264  bitMask |= 1 << 7;
265  if ( (!nmfi || !((val >> 6) & 0x1)) &&
266  (isSecure || scr.fw || haveVirt) ) {
267  bitMask |= 1 << 6;
268  }
269  // Now check the new mode is allowed
270  OperatingMode newMode = (OperatingMode) (val & mask(5));
271  OperatingMode oldMode = (OperatingMode)(uint32_t)cpsr.mode;
272  if (!badMode(tc, newMode)) {
273  bool validModeChange = true;
274  // Check for attempts to enter modes only permitted in
275  // Secure state from Non-secure state. These are Monitor
276  // mode ('10110'), and FIQ mode ('10001') if the Security
277  // Extensions have reserved it.
278  if (!isSecure && newMode == MODE_MON)
279  validModeChange = false;
280  if (!isSecure && newMode == MODE_FIQ && nsacr.rfr == '1')
281  validModeChange = false;
282  // There is no Hyp mode ('11010') in Secure state, so that
283  // is UNPREDICTABLE
284  if (scr.ns == 0 && newMode == MODE_HYP)
285  validModeChange = false;
286  // Cannot move into Hyp mode directly from a Non-secure
287  // PL1 mode
288  if (!isSecure && oldMode != MODE_HYP && newMode == MODE_HYP)
289  validModeChange = false;
290  // Cannot move out of Hyp mode with this function except
291  // on an exception return
292  if (oldMode == MODE_HYP && newMode != MODE_HYP && !affectState)
293  validModeChange = false;
294  // Must not change to 64 bit when running in 32 bit mode
295  if (!opModeIs64(oldMode) && opModeIs64(newMode))
296  validModeChange = false;
297 
298  // If we passed all of the above then set the bit mask to
299  // copy the mode accross
300  if (validModeChange) {
301  bitMask = bitMask | mask(5);
302  } else {
303  warn_once("Illegal change to CPSR mode attempted\n");
304  }
305  } else {
306  warn_once("Ignoring write of bad mode to CPSR.\n");
307  }
308  }
309  if (affectState)
310  bitMask = bitMask | (1 << 5);
311  }
312 
313  return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
314  }
315 
316  static inline uint32_t
317  spsrWriteByInstr(uint32_t spsr, uint32_t val,
318  uint8_t byteMask, bool affectState)
319  {
320  uint32_t bitMask = 0;
321 
322  if (bits(byteMask, 3))
323  bitMask = bitMask | mask(31, 24);
324  if (bits(byteMask, 2))
325  bitMask = bitMask | mask(19, 16);
326  if (bits(byteMask, 1))
327  bitMask = bitMask | mask(15, 8);
328  if (bits(byteMask, 0))
329  bitMask = bitMask | mask(7, 0);
330 
331  return ((spsr & ~bitMask) | (val & bitMask));
332  }
333 
334  static inline Addr
336  {
337  return xc->pcState().as<PCState>().instPC();
338  }
339 
340  static inline void
342  {
343  PCState pc = xc->pcState().as<PCState>();
344  pc.instNPC(val);
345  xc->pcState(pc);
346  }
347 
348  template<class T>
349  static inline T
350  cSwap(T val, bool big)
351  {
352  if (big) {
353  return letobe(val);
354  } else {
355  return val;
356  }
357  }
358 
359  template<class T, class E>
360  static inline T
361  cSwap(T val, bool big)
362  {
363  const unsigned count = sizeof(T) / sizeof(E);
364  union
365  {
366  T tVal;
367  E eVals[count];
368  } conv;
369  conv.tVal = htole(val);
370  if (big) {
371  for (unsigned i = 0; i < count; i++) {
372  conv.eVals[i] = letobe(conv.eVals[i]);
373  }
374  } else {
375  for (unsigned i = 0; i < count; i++) {
376  conv.eVals[i] = conv.eVals[i];
377  }
378  }
379  return letoh(conv.tVal);
380  }
381 
382  // Perform an interworking branch.
383  static inline void
385  {
386  PCState pc = xc->pcState().as<PCState>();
387  pc.instIWNPC(val);
388  xc->pcState(pc);
389  }
390 
391  // Perform an interworking branch in ARM mode, a regular branch
392  // otherwise.
393  static inline void
395  {
396  PCState pc = xc->pcState().as<PCState>();
397  pc.instAIWNPC(val);
398  xc->pcState(pc);
399  }
400 
401  inline Fault
403  {
404  return std::make_shared<UndefinedInstruction>(machInst, false,
405  mnemonic, true);
406  }
407 
408  // Utility function used by checkForWFxTrap32 and checkForWFxTrap64
409  // Returns true if processor has to trap a WFI/WFE instruction.
410  bool isWFxTrapping(ThreadContext *tc,
411  ExceptionLevel targetEL, bool isWfe) const;
412 
419  Fault softwareBreakpoint32(ExecContext *xc, uint16_t imm) const;
420 
431 
432 
439  Fault checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const;
440 
449  CPSR cpsr, CPACR cpacr) const;
450 
458  CPSR cpsr, CPACR cpacr,
459  NSACR nsacr, FPEXC fpexc,
460  bool fpexc_check, bool advsimd) const;
461 
469  ExceptionLevel tgtEl, bool isWfe) const;
470 
478  ExceptionLevel tgtEl, bool isWfe) const;
479 
483  Fault trapWFx(ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) const;
484 
491  Fault checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const;
492 
500 
508 
515 
519  Fault checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const;
520 
528  CPSR getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const;
529 
539  ExceptionLevel pstateEL) const;
540 
541  public:
542  virtual void
544 
545  uint8_t
546  getIntWidth() const
547  {
548  return intWidth;
549  }
550 
552  ssize_t
553  instSize() const
554  {
555  return (!machInst.thumb || machInst.bigThumb) ? 4 : 2;
556  }
557 
564  MachInst
565  encoding() const
566  {
567  return static_cast<MachInst>(machInst & (mask(instSize() * 8)));
568  }
569 
570  size_t
571  asBytes(void *buf, size_t max_size) override
572  {
573  return simpleAsBytes(buf, max_size, machInst);
574  }
575 
576  static unsigned getCurSveVecLenInBits(ThreadContext *tc);
577 
578  static unsigned
580  {
581  return getCurSveVecLenInBits(tc) >> 6;
582  }
583 
584  template<typename T>
585  static unsigned
587  {
588  return getCurSveVecLenInBits(tc) / (8 * sizeof(T));
589  }
590 };
591 
592 } // namespace ArmISA
593 } // namespace gem5
594 
595 #endif //__ARCH_ARM_INSTS_STATICINST_HH__
gem5::ArmISA::ArmStaticInst::setNextPC
static void setNextPC(ExecContext *xc, Addr val)
Definition: static_inst.hh:341
gem5::ArmISA::ArmStaticInst::printVecReg
void printVecReg(std::ostream &os, RegIndex reg_idx, bool isSveVecReg=false) const
Definition: static_inst.cc:351
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:292
gem5::ArmISA::ArmStaticInst::advSIMDFPAccessTrap64
Fault advSIMDFPAccessTrap64(ExceptionLevel el) const
Trap an access to Advanced SIMD or FP registers due to access control bits.
Definition: static_inst.cc:655
gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR
CPSR getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const
Get the new PSTATE from a SPSR register in preparation for an exception return.
Definition: static_inst.cc:1147
gem5::ArmISA::ArmStaticInst::uSatInt
static bool uSatInt(int32_t &res, int64_t op, int width)
Definition: static_inst.hh:137
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:289
gem5::ArmISA::SelfDebug
Definition: self_debug.hh:277
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:65
gem5::ArmISA::advsimd
Bitfield< 23, 20 > advsimd
Definition: misc_types.hh:176
gem5::ArmISA::ArmStaticInst::printShiftOperand
void printShiftOperand(std::ostream &os, RegIndex rm, bool immShift, uint32_t shiftAmt, RegIndex rs, ArmShiftType type) const
Definition: static_inst.cc:498
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmISA::ArmStaticInst::cSwap
static T cSwap(T val, bool big)
Definition: static_inst.hh:361
gem5::ArmISA::ArmStaticInst::undefinedFault32
Fault undefinedFault32(ThreadContext *tc, ExceptionLevel el) const
UNDEFINED behaviour in AArch32.
Definition: static_inst.cc:960
gem5::ArmISA::ArmStaticInst::setIWNextPC
static void setIWNextPC(ExecContext *xc, Addr val)
Definition: static_inst.hh:384
warn_once
#define warn_once(...)
Definition: logging.hh:250
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ArmISA::ArmStaticInst::shift_carry_imm
bool shift_carry_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
Definition: static_inst.cc:220
gem5::ArmISA::ArmStaticInst::printMnemonic
void printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
Definition: static_inst.cc:377
gem5::ArmISA::ArmStaticInst::getCurSveVecLenInQWords
static unsigned getCurSveVecLenInQWords(ThreadContext *tc)
Definition: static_inst.hh:579
gem5::StaticInst::simpleAsBytes
size_t simpleAsBytes(void *buf, size_t max_size, const T &t)
Definition: static_inst.hh:356
gem5::ArmISA::ArmStaticInst::getEMI
uint64_t getEMI() const override
Definition: static_inst.hh:215
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::ArmISA::ArmExtendType
ArmExtendType
Definition: types.hh:222
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::ArmStaticInst::disabledFault
Fault disabledFault() const
Definition: static_inst.hh:402
gem5::ArmISA::ArmStaticInst::getCurSveVecLenInBits
static unsigned getCurSveVecLenInBits(ThreadContext *tc)
Definition: static_inst.cc:1219
gem5::ArmISA::ArmStaticInst::printCCReg
void printCCReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:364
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::ArmISA::badMode
bool badMode(ThreadContext *tc, OperatingMode mode)
badMode is checking if the execution mode provided as an argument is valid and implemented.
Definition: utility.cc:403
system.hh
gem5::ArmISA::ArmStaticInst::encoding
MachInst encoding() const
Returns the real encoding of the instruction: the machInst field is in fact always 64 bit wide and co...
Definition: static_inst.hh:565
gem5::ArmISA::ArmStaticInst::advancePC
void advancePC(ThreadContext *tc) const override
Definition: static_inst.hh:208
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ArmISA::ArmStaticInst::trapWFx
Fault trapWFx(ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) const
WFE/WFI trapping helper function.
Definition: static_inst.cc:902
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::ArmStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:151
gem5::ArmISA::ArmStaticInst::shift_rm_rs
int32_t shift_rm_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
Definition: static_inst.cc:180
gem5::ArmISA::ArmStaticInst::softwareBreakpoint32
Fault softwareBreakpoint32(ExecContext *xc, uint16_t imm) const
Trigger a Software Breakpoint.
Definition: static_inst.cc:635
gem5::ArmISA::ArmStaticInst::printTarget
void printTarget(std::ostream &os, Addr target, const loader::SymbolTable *symtab) const
Definition: static_inst.cc:398
gem5::ArmISA::ArmStaticInst::saturateOp
static bool saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
Definition: static_inst.hh:88
gem5::letoh
T letoh(T value)
Definition: byteswap.hh:173
gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32
Fault checkAdvSIMDOrFPEnabled32(ThreadContext *tc, CPSR cpsr, CPACR cpacr, NSACR nsacr, FPEXC fpexc, bool fpexc_check, bool advsimd) const
Check if a VFP/SIMD access from aarch32 should be allowed.
Definition: static_inst.cc:726
gem5::ArmISA::ArmStaticInst::cpsrWriteByInstr
static uint32_t cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)
Definition: static_inst.hh:237
gem5::ArmISA::ArmStaticInst::printCondition
void printCondition(std::ostream &os, unsigned code, bool noImplicit=false) const
Definition: static_inst.cc:417
gem5::ArmISA::ArmStaticInst::readPC
static Addr readPC(ExecContext *xc)
Definition: static_inst.hh:335
gem5::ArmISA::ArmStaticInst::asBytes
size_t asBytes(void *buf, size_t max_size) override
Instruction classes can override this function to return a a representation of themselves as a blob o...
Definition: static_inst.hh:571
gem5::ArmISA::ArmStaticInst::checkSETENDEnabled
Fault checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const
Check if SETEND instruction execution in aarch32 should be trapped.
Definition: static_inst.cc:928
gem5::ArmISA::ArmStaticInst::cSwap
static T cSwap(T val, bool big)
Definition: static_inst.hh:350
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:88
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:294
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::ArmISA::ArmStaticInst::undefinedFault64
Fault undefinedFault64(ThreadContext *tc, ExceptionLevel el) const
UNDEFINED behaviour in AArch64.
Definition: static_inst.cc:979
gem5::ArmISA::ArmStaticInst::printMemSymbol
void printMemSymbol(std::ostream &os, const loader::SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) const
Definition: static_inst.cc:480
gem5::ArmISA::ArmStaticInst::shiftReg64
int64_t shiftReg64(uint64_t base, uint64_t shiftAmt, ArmShiftType type, uint8_t width) const
Definition: static_inst.cc:95
gem5::ArmISA::width
Bitfield< 4 > width
Definition: misc_types.hh:72
gem5::ArmISA::rd
Bitfield< 15, 12 > rd
Definition: types.hh:114
gem5::ArmISA::ArmStaticInst::uSaturateOp
static bool uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)
Definition: static_inst.hh:121
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:275
gem5::ArmISA::MachInst
uint32_t MachInst
Definition: types.hh:55
gem5::ArmISA::COND_UC
@ COND_UC
Definition: cc.hh:99
gem5::ArmISA::rm
Bitfield< 3, 0 > rm
Definition: types.hh:118
gem5::ArmISA::ArmStaticInst::checkForWFxTrap64
Fault checkForWFxTrap64(ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const
Check if WFE/WFI instruction execution in aarch64 should be trapped.
Definition: static_inst.cc:870
isa.hh
gem5::ArmISA::nmfi
Bitfield< 27 > nmfi
Definition: misc_types.hh:341
gem5::X86ISA::type
type
Definition: misc.hh:727
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:562
gem5::ArmISA::ArmStaticInst::activateBreakpoint
static void activateBreakpoint(ThreadContext *tc)
Definition: static_inst.hh:230
gem5::ArmISA::ArmStaticInst::isWFxTrapping
bool isWFxTrapping(ThreadContext *tc, ExceptionLevel targetEL, bool isWfe) const
Definition: static_inst.cc:803
gem5::RefCounted::count
int count
Definition: refcnt.hh:67
gem5::ArmISA::ArmStaticInst::advancePC
void advancePC(PCStateBase &pcState) const override
Definition: static_inst.hh:202
gem5::ArmISA::ArmStaticInst::getCurSveVecLen
static unsigned getCurSveVecLen(ThreadContext *tc)
Definition: static_inst.hh:586
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::ArmStaticInst::ArmStaticInst
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Definition: static_inst.hh:154
gem5::ArmISA::ArmStaticInst::intWidth
uint8_t intWidth
Definition: static_inst.hh:69
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constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::ArmStaticInst::setAIWNextPC
static void setAIWNextPC(ExecContext *xc, Addr val)
Definition: static_inst.hh:394
gem5::ArmISA::ArmStaticInst::shift_carry_rs
bool shift_carry_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
Definition: static_inst.cc:260
static_inst.hh
gem5::ArmISA::ArmStaticInst::checkForWFxTrap32
Fault checkForWFxTrap32(ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const
Check if WFE/WFI instruction execution in aarch32 should be trapped.
Definition: static_inst.cc:830
gem5::ArmISA::ArmStaticInst::printVecPredReg
void printVecPredReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:358
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:288
faults.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::ArmStaticInst::checkSveEnabled
Fault checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
Check an SVE access against CPACR_EL1, CPTR_EL2, and CPTR_EL3.
Definition: static_inst.cc:1016
pcstate.hh
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:73
utility.hh
gem5::ArmISA::ArmStaticInst::generalExceptionsToAArch64
bool generalExceptionsToAArch64(ThreadContext *tc, ExceptionLevel pstateEL) const
Return true if exceptions normally routed to EL1 are being handled at an Exception level using AArch6...
Definition: static_inst.cc:1206
full_system.hh
gem5::ArmISA::ArmFault
Definition: faults.hh:64
gem5::ArmISA::ArmStaticInst::buildRetPC
std::unique_ptr< PCStateBase > buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const override
Definition: static_inst.hh:218
gem5::X86ISA::ExtMachInst
Definition: types.hh:212
gem5::ArmISA::ArmStaticInst::extendReg64
int64_t extendReg64(uint64_t base, ArmExtendType type, uint64_t shiftAmt, uint8_t width) const
Definition: static_inst.cc:134
gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDEnabled64
Fault checkFPAdvSIMDEnabled64(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
Check an Advaned SIMD access against CPACR_EL1, CPTR_EL2, and CPTR_EL3.
Definition: static_inst.cc:714
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ExecContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ArmISA::ArmStaticInst::printDataInst
void printDataInst(std::ostream &os, bool withImm) const
gem5::ArmISA::ArmStaticInst::printFloatReg
void printFloatReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:345
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
gem5::ArmISA::ArmStaticInst::shift_rm_imm
int32_t shift_rm_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
Definition: static_inst.cc:60
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:82
gem5::ArmISA::ISA::getSelfDebug
SelfDebug * getSelfDebug() const
Definition: isa.hh:629
exec_context.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::htole
T htole(T value)
Definition: byteswap.hh:172
gem5::X86ISA::E
Bitfield< 31, 0 > E
Definition: int.hh:55
gem5::ArmISA::ArmStaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:626
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::ArmISA::ArmStaticInst::printMiscReg
void printMiscReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:370
gem5::ArmISA::ArmStaticInst::printExtendOperand
void printExtendOperand(bool firstOperand, std::ostream &os, RegIndex rm, ArmExtendType type, int64_t shiftAmt) const
Definition: static_inst.cc:562
gem5::ArmISA::ArmStaticInst::satInt
static bool satInt(int32_t &res, int64_t op, int width)
Definition: static_inst.hh:104
gem5::ArmISA::sd
Bitfield< 4 > sd
Definition: misc_types.hh:827
trace.hh
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::ArmISA::ArmStaticInst::aarch64
bool aarch64
Definition: static_inst.hh:68
self_debug.hh
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:131
gem5::ArmISA::ArmStaticInst::printIntReg
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:299
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:259
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::ArmStaticInst::instSize
ssize_t instSize() const
Returns the byte size of current instruction.
Definition: static_inst.hh:553
gem5::ArmISA::rn
Bitfield< 19, 16 > rn
Definition: types.hh:113
gem5::letobe
T letobe(T value)
Definition: byteswap.hh:166
gem5::X86ISA::op
Bitfield< 4 > op
Definition: types.hh:83
gem5::ArmISA::ArmStaticInst::annotateFault
virtual void annotateFault(ArmFault *fault)
Definition: static_inst.hh:543
thread_context.hh
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:279
gem5::ArmISA::ArmStaticInst::getIntWidth
uint8_t getIntWidth() const
Definition: static_inst.hh:546
gem5::PCStateBase::clone
virtual PCStateBase * clone() const =0
gem5::ArmISA::rs
Bitfield< 9, 8 > rs
Definition: misc_types.hh:377
byteswap.hh
gem5::ArmISA::ArmStaticInst::sveAccessTrap
Fault sveAccessTrap(ExceptionLevel el) const
Trap an access to SVE registers due to access control bits.
Definition: static_inst.cc:999
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:271
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ArmISA::ArmStaticInst::printPFflags
void printPFflags(std::ostream &os, int flag) const
Definition: static_inst.cc:334
gem5::ArmISA::ArmStaticInst::spsrWriteByInstr
static uint32_t spsrWriteByInstr(uint32_t spsr, uint32_t val, uint8_t byteMask, bool affectState)
Definition: static_inst.hh:317
gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64
Fault checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const
Check an Advaned SIMD access against CPTR_EL2 and CPTR_EL3.
Definition: static_inst.cc:675

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