gem5  v21.1.0.2
static_inst.hh
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40 
41 #ifndef __ARCH_ARM_INSTS_STATICINST_HH__
42 #define __ARCH_ARM_INSTS_STATICINST_HH__
43 
44 #include <memory>
45 
46 #include "arch/arm/faults.hh"
47 #include "arch/arm/utility.hh"
48 #include "arch/arm/isa.hh"
49 #include "arch/arm/self_debug.hh"
50 #include "arch/arm/system.hh"
51 #include "base/trace.hh"
52 #include "cpu/exec_context.hh"
53 #include "cpu/static_inst.hh"
54 #include "sim/byteswap.hh"
55 #include "sim/full_system.hh"
56 
57 namespace gem5
58 {
59 
60 namespace ArmISA
61 {
62 
63 class ArmStaticInst : public StaticInst
64 {
65  protected:
66  bool aarch64;
67  uint8_t intWidth;
68 
69  int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
70  uint32_t type, uint32_t cfval) const;
71  int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
72  uint32_t type, uint32_t cfval) const;
73 
74  bool shift_carry_imm(uint32_t base, uint32_t shamt,
75  uint32_t type, uint32_t cfval) const;
76  bool shift_carry_rs(uint32_t base, uint32_t shamt,
77  uint32_t type, uint32_t cfval) const;
78 
79  int64_t shiftReg64(uint64_t base, uint64_t shiftAmt,
80  ArmShiftType type, uint8_t width) const;
81  int64_t extendReg64(uint64_t base, ArmExtendType type,
82  uint64_t shiftAmt, uint8_t width) const;
83 
84  template<int width>
85  static inline bool
86  saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
87  {
88  int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
89  if (bits(midRes, width) != bits(midRes, width - 1)) {
90  if (midRes > 0)
91  res = (1LL << (width - 1)) - 1;
92  else
93  res = -(1LL << (width - 1));
94  return true;
95  } else {
96  res = midRes;
97  return false;
98  }
99  }
100 
101  static inline bool
102  satInt(int32_t &res, int64_t op, int width)
103  {
104  width--;
105  if (op >= (1LL << width)) {
106  res = (1LL << width) - 1;
107  return true;
108  } else if (op < -(1LL << width)) {
109  res = -(1LL << width);
110  return true;
111  } else {
112  res = op;
113  return false;
114  }
115  }
116 
117  template<int width>
118  static inline bool
119  uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)
120  {
121  int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
122  if (midRes >= (1LL << width)) {
123  res = (1LL << width) - 1;
124  return true;
125  } else if (midRes < 0) {
126  res = 0;
127  return true;
128  } else {
129  res = midRes;
130  return false;
131  }
132  }
133 
134  static inline bool
135  uSatInt(int32_t &res, int64_t op, int width)
136  {
137  if (op >= (1LL << width)) {
138  res = (1LL << width) - 1;
139  return true;
140  } else if (op < 0) {
141  res = 0;
142  return true;
143  } else {
144  res = op;
145  return false;
146  }
147  }
148 
150 
151  // Constructor
152  ArmStaticInst(const char *mnem, ExtMachInst _machInst,
153  OpClass __opClass)
154  : StaticInst(mnem, __opClass), machInst(_machInst)
155  {
156  aarch64 = machInst.aarch64;
157  if (bits(machInst, 28, 24) == 0x10)
158  intWidth = 64; // Force 64-bit width for ADR/ADRP
159  else
160  intWidth = (aarch64 && bits(machInst, 31)) ? 64 : 32;
161  }
162 
165  void printIntReg(std::ostream &os, RegIndex reg_idx,
166  uint8_t opWidth = 0) const;
167  void printFloatReg(std::ostream &os, RegIndex reg_idx) const;
168  void printVecReg(std::ostream &os, RegIndex reg_idx,
169  bool isSveVecReg = false) const;
170  void printVecPredReg(std::ostream &os, RegIndex reg_idx) const;
171  void printCCReg(std::ostream &os, RegIndex reg_idx) const;
172  void printMiscReg(std::ostream &os, RegIndex reg_idx) const;
173  void printMnemonic(std::ostream &os,
174  const std::string &suffix = "",
175  bool withPred = true,
176  bool withCond64 = false,
177  ConditionCode cond64 = COND_UC) const;
178  void printTarget(std::ostream &os, Addr target,
179  const loader::SymbolTable *symtab) const;
180  void printCondition(std::ostream &os, unsigned code,
181  bool noImplicit=false) const;
182  void printMemSymbol(std::ostream &os, const loader::SymbolTable *symtab,
183  const std::string &prefix, const Addr addr,
184  const std::string &suffix) const;
185  void printShiftOperand(std::ostream &os, IntRegIndex rm,
186  bool immShift, uint32_t shiftAmt,
187  IntRegIndex rs, ArmShiftType type) const;
188  void printExtendOperand(bool firstOperand, std::ostream &os,
189  IntRegIndex rm, ArmExtendType type,
190  int64_t shiftAmt) const;
191  void printPFflags(std::ostream &os, int flag) const;
192 
193  void printDataInst(std::ostream &os, bool withImm) const;
194  void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
195  IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
196  IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
197  uint64_t imm) const;
198 
199  void
200  advancePC(PCState &pcState) const override
201  {
202  pcState.advance();
203  }
204 
205  uint64_t getEMI() const override { return machInst; }
206 
207  PCState
208  buildRetPC(const PCState &curPC, const PCState &callPC) const override
209  {
210  PCState retPC = callPC;
211  retPC.uEnd();
212  return retPC;
213  }
214 
215  std::string generateDisassembly(
216  Addr pc, const loader::SymbolTable *symtab) const override;
217 
218  static void
220  {
222  sd->activateDebug();
223  }
224 
225  static inline uint32_t
226  cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr,
227  uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)
228  {
229  bool privileged = (cpsr.mode != MODE_USER);
230  bool haveVirt = ArmSystem::haveVirtualization(tc);
231  bool isSecure = ArmISA::isSecure(tc);
232 
233  uint32_t bitMask = 0;
234 
235  if (affectState && byteMask==0xF){
236  activateBreakpoint(tc);
237  }
238  if (bits(byteMask, 3)) {
239  unsigned lowIdx = affectState ? 24 : 27;
240  bitMask = bitMask | mask(31, lowIdx);
241  }
242  if (bits(byteMask, 2)) {
243  bitMask = bitMask | mask(19, 16);
244  }
245  if (bits(byteMask, 1)) {
246  unsigned highIdx = affectState ? 15 : 9;
247  unsigned lowIdx = (privileged && (isSecure || scr.aw || haveVirt))
248  ? 8 : 9;
249  bitMask = bitMask | mask(highIdx, lowIdx);
250  }
251  if (bits(byteMask, 0)) {
252  if (privileged) {
253  bitMask |= 1 << 7;
254  if ( (!nmfi || !((val >> 6) & 0x1)) &&
255  (isSecure || scr.fw || haveVirt) ) {
256  bitMask |= 1 << 6;
257  }
258  // Now check the new mode is allowed
259  OperatingMode newMode = (OperatingMode) (val & mask(5));
260  OperatingMode oldMode = (OperatingMode)(uint32_t)cpsr.mode;
261  if (!badMode(tc, newMode)) {
262  bool validModeChange = true;
263  // Check for attempts to enter modes only permitted in
264  // Secure state from Non-secure state. These are Monitor
265  // mode ('10110'), and FIQ mode ('10001') if the Security
266  // Extensions have reserved it.
267  if (!isSecure && newMode == MODE_MON)
268  validModeChange = false;
269  if (!isSecure && newMode == MODE_FIQ && nsacr.rfr == '1')
270  validModeChange = false;
271  // There is no Hyp mode ('11010') in Secure state, so that
272  // is UNPREDICTABLE
273  if (scr.ns == 0 && newMode == MODE_HYP)
274  validModeChange = false;
275  // Cannot move into Hyp mode directly from a Non-secure
276  // PL1 mode
277  if (!isSecure && oldMode != MODE_HYP && newMode == MODE_HYP)
278  validModeChange = false;
279  // Cannot move out of Hyp mode with this function except
280  // on an exception return
281  if (oldMode == MODE_HYP && newMode != MODE_HYP && !affectState)
282  validModeChange = false;
283  // Must not change to 64 bit when running in 32 bit mode
284  if (!opModeIs64(oldMode) && opModeIs64(newMode))
285  validModeChange = false;
286 
287  // If we passed all of the above then set the bit mask to
288  // copy the mode accross
289  if (validModeChange) {
290  bitMask = bitMask | mask(5);
291  } else {
292  warn_once("Illegal change to CPSR mode attempted\n");
293  }
294  } else {
295  warn_once("Ignoring write of bad mode to CPSR.\n");
296  }
297  }
298  if (affectState)
299  bitMask = bitMask | (1 << 5);
300  }
301 
302  return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
303  }
304 
305  static inline uint32_t
306  spsrWriteByInstr(uint32_t spsr, uint32_t val,
307  uint8_t byteMask, bool affectState)
308  {
309  uint32_t bitMask = 0;
310 
311  if (bits(byteMask, 3))
312  bitMask = bitMask | mask(31, 24);
313  if (bits(byteMask, 2))
314  bitMask = bitMask | mask(19, 16);
315  if (bits(byteMask, 1))
316  bitMask = bitMask | mask(15, 8);
317  if (bits(byteMask, 0))
318  bitMask = bitMask | mask(7, 0);
319 
320  return ((spsr & ~bitMask) | (val & bitMask));
321  }
322 
323  static inline Addr
325  {
326  return xc->pcState().instPC();
327  }
328 
329  static inline void
331  {
332  PCState pc = xc->pcState();
333  pc.instNPC(val);
334  xc->pcState(pc);
335  }
336 
337  template<class T>
338  static inline T
339  cSwap(T val, bool big)
340  {
341  if (big) {
342  return letobe(val);
343  } else {
344  return val;
345  }
346  }
347 
348  template<class T, class E>
349  static inline T
350  cSwap(T val, bool big)
351  {
352  const unsigned count = sizeof(T) / sizeof(E);
353  union
354  {
355  T tVal;
356  E eVals[count];
357  } conv;
358  conv.tVal = htole(val);
359  if (big) {
360  for (unsigned i = 0; i < count; i++) {
361  conv.eVals[i] = letobe(conv.eVals[i]);
362  }
363  } else {
364  for (unsigned i = 0; i < count; i++) {
365  conv.eVals[i] = conv.eVals[i];
366  }
367  }
368  return letoh(conv.tVal);
369  }
370 
371  // Perform an interworking branch.
372  static inline void
374  {
375  PCState pc = xc->pcState();
376  pc.instIWNPC(val);
377  xc->pcState(pc);
378  }
379 
380  // Perform an interworking branch in ARM mode, a regular branch
381  // otherwise.
382  static inline void
384  {
385  PCState pc = xc->pcState();
386  pc.instAIWNPC(val);
387  xc->pcState(pc);
388  }
389 
390  inline Fault
392  {
393  return std::make_shared<UndefinedInstruction>(machInst, false,
394  mnemonic, true);
395  }
396 
397  // Utility function used by checkForWFxTrap32 and checkForWFxTrap64
398  // Returns true if processor has to trap a WFI/WFE instruction.
399  bool isWFxTrapping(ThreadContext *tc,
400  ExceptionLevel targetEL, bool isWfe) const;
401 
408  Fault softwareBreakpoint32(ExecContext *xc, uint16_t imm) const;
409 
420 
421 
428  Fault checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const;
429 
438  CPSR cpsr, CPACR cpacr) const;
439 
447  CPSR cpsr, CPACR cpacr,
448  NSACR nsacr, FPEXC fpexc,
449  bool fpexc_check, bool advsimd) const;
450 
458  ExceptionLevel tgtEl, bool isWfe) const;
459 
467  ExceptionLevel tgtEl, bool isWfe) const;
468 
472  Fault trapWFx(ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) const;
473 
480  Fault checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const;
481 
489 
497 
504 
508  Fault checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const;
509 
517  CPSR getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const;
518 
528  ExceptionLevel pstateEL) const;
529 
530  public:
531  virtual void
533 
534  uint8_t
535  getIntWidth() const
536  {
537  return intWidth;
538  }
539 
541  ssize_t
542  instSize() const
543  {
544  return (!machInst.thumb || machInst.bigThumb) ? 4 : 2;
545  }
546 
553  MachInst
554  encoding() const
555  {
556  return static_cast<MachInst>(machInst & (mask(instSize() * 8)));
557  }
558 
559  size_t
560  asBytes(void *buf, size_t max_size) override
561  {
562  return simpleAsBytes(buf, max_size, machInst);
563  }
564 
565  static unsigned getCurSveVecLenInBits(ThreadContext *tc);
566 
567  static unsigned
569  {
570  return getCurSveVecLenInBits(tc) >> 6;
571  }
572 
573  template<typename T>
574  static unsigned
576  {
577  return getCurSveVecLenInBits(tc) / (8 * sizeof(T));
578  }
579 };
580 
581 } // namespace ArmISA
582 } // namespace gem5
583 
584 #endif //__ARCH_ARM_INSTS_STATICINST_HH__
gem5::ArmISA::ArmStaticInst::printShiftOperand
void printShiftOperand(std::ostream &os, IntRegIndex rm, bool immShift, uint32_t shiftAmt, IntRegIndex rs, ArmShiftType type) const
Definition: static_inst.cc:498
gem5::ArmISA::ArmStaticInst::setNextPC
static void setNextPC(ExecContext *xc, Addr val)
Definition: static_inst.hh:330
gem5::ArmISA::ArmStaticInst::printVecReg
void printVecReg(std::ostream &os, RegIndex reg_idx, bool isSveVecReg=false) const
Definition: static_inst.cc:351
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::ArmISA::ArmStaticInst::advSIMDFPAccessTrap64
Fault advSIMDFPAccessTrap64(ExceptionLevel el) const
Trap an access to Advanced SIMD or FP registers due to access control bits.
Definition: static_inst.cc:655
gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR
CPSR getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const
Get the new PSTATE from a SPSR register in preparation for an exception return.
Definition: static_inst.cc:1148
gem5::ArmISA::ArmStaticInst::uSatInt
static bool uSatInt(int32_t &res, int64_t op, int width)
Definition: static_inst.hh:135
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:282
gem5::ArmISA::SelfDebug
Definition: self_debug.hh:277
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::ArmISA::advsimd
Bitfield< 23, 20 > advsimd
Definition: misc_types.hh:175
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:72
gem5::ArmISA::ArmStaticInst::cSwap
static T cSwap(T val, bool big)
Definition: static_inst.hh:350
gem5::ArmISA::ArmStaticInst::undefinedFault32
Fault undefinedFault32(ThreadContext *tc, ExceptionLevel el) const
UNDEFINED behaviour in AArch32.
Definition: static_inst.cc:960
gem5::ArmISA::ArmStaticInst::setIWNextPC
static void setIWNextPC(ExecContext *xc, Addr val)
Definition: static_inst.hh:373
warn_once
#define warn_once(...)
Definition: logging.hh:249
gem5::ArmISA::ArmStaticInst::shift_carry_imm
bool shift_carry_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
Definition: static_inst.cc:220
gem5::ArmISA::ArmStaticInst::printMnemonic
void printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
Definition: static_inst.cc:377
gem5::ArmISA::ArmStaticInst::getCurSveVecLenInQWords
static unsigned getCurSveVecLenInQWords(ThreadContext *tc)
Definition: static_inst.hh:568
gem5::StaticInst::simpleAsBytes
size_t simpleAsBytes(void *buf, size_t max_size, const T &t)
Definition: static_inst.hh:383
gem5::ArmISA::ArmStaticInst::getEMI
uint64_t getEMI() const override
Definition: static_inst.hh:205
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::ArmStaticInst::buildRetPC
PCState buildRetPC(const PCState &curPC, const PCState &callPC) const override
Definition: static_inst.hh:208
gem5::ArmISA::ArmExtendType
ArmExtendType
Definition: types.hh:215
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::ArmStaticInst::disabledFault
Fault disabledFault() const
Definition: static_inst.hh:391
gem5::ArmISA::ArmStaticInst::getCurSveVecLenInBits
static unsigned getCurSveVecLenInBits(ThreadContext *tc)
Definition: static_inst.cc:1219
gem5::ArmISA::ArmStaticInst::printCCReg
void printCCReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:364
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::ArmISA::badMode
bool badMode(ThreadContext *tc, OperatingMode mode)
badMode is checking if the execution mode provided as an argument is valid and implemented.
Definition: utility.cc:412
system.hh
gem5::ArmISA::ArmStaticInst::encoding
MachInst encoding() const
Returns the real encoding of the instruction: the machInst field is in fact always 64 bit wide and co...
Definition: static_inst.hh:554
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::ArmISA::ArmStaticInst::trapWFx
Fault trapWFx(ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) const
WFE/WFI trapping helper function.
Definition: static_inst.cc:902
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::ArmStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:149
gem5::ArmISA::ArmStaticInst::shift_rm_rs
int32_t shift_rm_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
Definition: static_inst.cc:180
gem5::ArmISA::ArmStaticInst::softwareBreakpoint32
Fault softwareBreakpoint32(ExecContext *xc, uint16_t imm) const
Trigger a Software Breakpoint.
Definition: static_inst.cc:635
gem5::ArmISA::ArmStaticInst::printTarget
void printTarget(std::ostream &os, Addr target, const loader::SymbolTable *symtab) const
Definition: static_inst.cc:398
gem5::ArmISA::ArmStaticInst::saturateOp
static bool saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
Definition: static_inst.hh:86
gem5::letoh
T letoh(T value)
Definition: byteswap.hh:173
gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32
Fault checkAdvSIMDOrFPEnabled32(ThreadContext *tc, CPSR cpsr, CPACR cpacr, NSACR nsacr, FPEXC fpexc, bool fpexc_check, bool advsimd) const
Check if a VFP/SIMD access from aarch32 should be allowed.
Definition: static_inst.cc:726
gem5::ArmISA::ArmStaticInst::cpsrWriteByInstr
static uint32_t cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)
Definition: static_inst.hh:226
gem5::ArmISA::ArmStaticInst::printCondition
void printCondition(std::ostream &os, unsigned code, bool noImplicit=false) const
Definition: static_inst.cc:417
gem5::ArmISA::ArmStaticInst::readPC
static Addr readPC(ExecContext *xc)
Definition: static_inst.hh:324
gem5::ArmISA::ArmStaticInst::printExtendOperand
void printExtendOperand(bool firstOperand, std::ostream &os, IntRegIndex rm, ArmExtendType type, int64_t shiftAmt) const
Definition: static_inst.cc:562
gem5::ArmISA::ArmStaticInst::advancePC
void advancePC(PCState &pcState) const override
Definition: static_inst.hh:200
gem5::ArmISA::ArmStaticInst::asBytes
size_t asBytes(void *buf, size_t max_size) override
Instruction classes can override this function to return a a representation of themselves as a blob o...
Definition: static_inst.hh:560
gem5::ArmISA::ArmStaticInst::checkSETENDEnabled
Fault checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const
Check if SETEND instruction execution in aarch32 should be trapped.
Definition: static_inst.cc:928
gem5::ArmISA::ArmStaticInst::cSwap
static T cSwap(T val, bool big)
Definition: static_inst.hh:339
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:88
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:287
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::ArmStaticInst::undefinedFault64
Fault undefinedFault64(ThreadContext *tc, ExceptionLevel el) const
UNDEFINED behaviour in AArch64.
Definition: static_inst.cc:979
gem5::ArmISA::ArmStaticInst::printMemSymbol
void printMemSymbol(std::ostream &os, const loader::SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) const
Definition: static_inst.cc:480
gem5::ArmISA::ArmStaticInst::shiftReg64
int64_t shiftReg64(uint64_t base, uint64_t shiftAmt, ArmShiftType type, uint8_t width) const
Definition: static_inst.cc:95
gem5::ArmISA::width
Bitfield< 4 > width
Definition: misc_types.hh:71
gem5::ArmISA::rd
Bitfield< 15, 12 > rd
Definition: types.hh:114
gem5::ArmISA::ArmStaticInst::uSaturateOp
static bool uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)
Definition: static_inst.hh:119
gem5::ArmISA::MachInst
uint32_t MachInst
Definition: types.hh:55
gem5::ArmISA::COND_UC
@ COND_UC
Definition: cc.hh:84
gem5::ArmISA::rm
Bitfield< 3, 0 > rm
Definition: types.hh:118
gem5::ArmISA::ArmStaticInst::checkForWFxTrap64
Fault checkForWFxTrap64(ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const
Check if WFE/WFI instruction execution in aarch64 should be trapped.
Definition: static_inst.cc:870
isa.hh
gem5::ArmISA::nmfi
Bitfield< 27 > nmfi
Definition: misc_types.hh:340
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::ExecContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:561
gem5::ArmISA::ArmStaticInst::activateBreakpoint
static void activateBreakpoint(ThreadContext *tc)
Definition: static_inst.hh:219
gem5::ArmISA::ArmStaticInst::isWFxTrapping
bool isWFxTrapping(ThreadContext *tc, ExceptionLevel targetEL, bool isWfe) const
Definition: static_inst.cc:803
gem5::RefCounted::count
int count
Definition: refcnt.hh:67
gem5::ArmISA::ArmStaticInst::getCurSveVecLen
static unsigned getCurSveVecLen(ThreadContext *tc)
Definition: static_inst.hh:575
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::ArmStaticInst::ArmStaticInst
ArmStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:152
gem5::ArmISA::ArmStaticInst::intWidth
uint8_t intWidth
Definition: static_inst.hh:67
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::ArmStaticInst::setAIWNextPC
static void setAIWNextPC(ExecContext *xc, Addr val)
Definition: static_inst.hh:383
gem5::ArmISA::ArmStaticInst::shift_carry_rs
bool shift_carry_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
Definition: static_inst.cc:260
static_inst.hh
gem5::ArmISA::ArmStaticInst::checkForWFxTrap32
Fault checkForWFxTrap32(ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const
Check if WFE/WFI instruction execution in aarch32 should be trapped.
Definition: static_inst.cc:830
gem5::ArmISA::ArmStaticInst::printVecPredReg
void printVecPredReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:358
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:281
faults.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::ArmStaticInst::checkSveEnabled
Fault checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
Check an SVE access against CPACR_EL1, CPTR_EL2, and CPTR_EL3.
Definition: static_inst.cc:1016
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:72
utility.hh
gem5::ArmISA::ArmStaticInst::generalExceptionsToAArch64
bool generalExceptionsToAArch64(ThreadContext *tc, ExceptionLevel pstateEL) const
Return true if exceptions normally routed to EL1 are being handled at an Exception level using AArch6...
Definition: static_inst.cc:1206
full_system.hh
gem5::GenericISA::SimplePCState::advance
void advance()
Definition: types.hh:181
gem5::ArmISA::ArmFault
Definition: faults.hh:64
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::ArmStaticInst::extendReg64
int64_t extendReg64(uint64_t base, ArmExtendType type, uint64_t shiftAmt, uint8_t width) const
Definition: static_inst.cc:134
gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDEnabled64
Fault checkFPAdvSIMDEnabled64(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
Check an Advaned SIMD access against CPACR_EL1, CPTR_EL2, and CPTR_EL3.
Definition: static_inst.cc:714
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::ArmStaticInst::printDataInst
void printDataInst(std::ostream &os, bool withImm) const
gem5::ArmISA::ArmStaticInst::printFloatReg
void printFloatReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:345
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::ArmISA::ArmStaticInst::shift_rm_imm
int32_t shift_rm_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
Definition: static_inst.cc:60
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:67
gem5::ArmISA::ISA::getSelfDebug
SelfDebug * getSelfDebug() const
Definition: isa.hh:524
exec_context.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::htole
T htole(T value)
Definition: byteswap.hh:172
gem5::X86ISA::E
Bitfield< 31, 0 > E
Definition: int.hh:53
gem5::ArmISA::ArmStaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:626
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::ArmISA::ArmStaticInst::printMiscReg
void printMiscReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:370
gem5::ArmISA::ArmStaticInst::satInt
static bool satInt(int32_t &res, int64_t op, int width)
Definition: static_inst.hh:102
gem5::ArmISA::sd
Bitfield< 4 > sd
Definition: misc_types.hh:774
trace.hh
gem5::ArmISA::ArmStaticInst::aarch64
bool aarch64
Definition: static_inst.hh:66
self_debug.hh
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::ArmISA::ArmStaticInst::printIntReg
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:299
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::ArmStaticInst::instSize
ssize_t instSize() const
Returns the byte size of current instruction.
Definition: static_inst.hh:542
gem5::ArmISA::rn
Bitfield< 19, 16 > rn
Definition: types.hh:113
gem5::letobe
T letobe(T value)
Definition: byteswap.hh:166
gem5::X86ISA::op
Bitfield< 4 > op
Definition: types.hh:83
gem5::ArmISA::ArmStaticInst::annotateFault
virtual void annotateFault(ArmFault *fault)
Definition: static_inst.hh:532
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::ArmISA::ArmStaticInst::getIntWidth
uint8_t getIntWidth() const
Definition: static_inst.hh:535
gem5::ArmISA::rs
Bitfield< 9, 8 > rs
Definition: misc_types.hh:376
gem5::ArmSystem::haveVirtualization
bool haveVirtualization() const
Returns true if this system implements the virtualization Extensions.
Definition: system.hh:171
byteswap.hh
gem5::ArmISA::ArmStaticInst::sveAccessTrap
Fault sveAccessTrap(ExceptionLevel el) const
Trap an access to SVE registers due to access control bits.
Definition: static_inst.cc:999
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ArmISA::ArmStaticInst::printPFflags
void printPFflags(std::ostream &os, int flag) const
Definition: static_inst.cc:334
gem5::ArmISA::ArmStaticInst::spsrWriteByInstr
static uint32_t spsrWriteByInstr(uint32_t spsr, uint32_t val, uint8_t byteMask, bool affectState)
Definition: static_inst.hh:306
gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64
Fault checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const
Check an Advaned SIMD access against CPTR_EL2 and CPTR_EL3.
Definition: static_inst.cc:675

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