gem5 v24.0.0.0
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tarmac_tracer.hh
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1/*
2 * Copyright (c) 2017-2018, 2022 Arm Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
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8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
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13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
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23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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36 */
37
43#ifndef __ARCH_ARM_TRACERS_TARMAC_TRACER_HH__
44#define __ARCH_ARM_TRACERS_TARMAC_TRACER_HH__
45
46#include <memory>
47
50#include "params/TarmacTracer.hh"
51#include "sim/insttracer.hh"
52
53namespace gem5
54{
55
56class ThreadContext;
57class OutputStream;
58
59namespace trace {
60
61class TarmacTracer;
62
68{
69 public:
71 ThreadContext* _thread,
72 const StaticInstPtr _staticInst,
73 const PCStateBase &_pc)
74 : tracer(_tracer), thread(_thread), staticInst(_staticInst),
75 pc(_pc.clone())
76 {}
77
78 std::string tarmacCpuName() const;
79
80 public:
84 std::unique_ptr<PCStateBase> pc;
85};
86
94{
95 friend class TarmacTracerRecord;
97
98 public:
99 typedef TarmacTracerParams Params;
100
101 TarmacTracer(const Params &p);
102
110 const StaticInstPtr staticInst, const PCStateBase &pc,
111 const StaticInstPtr macroStaticInst=nullptr) override;
112
113 std::ostream& output();
114
115 protected:
116 typedef std::unique_ptr<Printable> PEntryPtr;
120
122
129
140};
141
142} // namespace trace
143} // namespace gem5
144
145#endif // __ARCH_ARM_TRACERS_TARMAC_TRACER_HH__
ThreadContext is the external interface to all thread state for anything outside of the CPU.
This object type is encapsulating the informations needed by a Tarmac record to generate it's own ent...
const StaticInstPtr staticInst
std::unique_ptr< PCStateBase > pc
std::string tarmacCpuName() const
TarmacContext(const TarmacTracer &_tracer, ThreadContext *_thread, const StaticInstPtr _staticInst, const PCStateBase &_pc)
const TarmacTracer & tracer
TarmacTracer record for ARMv8 CPUs: The record is adding some data to the base TarmacTracer record.
TarmacTracer Record: Record generated by the TarmacTracer for every executed instruction.
std::unique_ptr< TraceRegEntry > RegPtr
std::unique_ptr< TraceMemEntry > MemPtr
std::unique_ptr< TraceInstEntry > InstPtr
Tarmac Tracer: this tracer generates a new Tarmac Record for every instruction being executed in gem5...
TarmacTracerRecord::RegPtr RegPtr
std::vector< InstPtr > instQueue
Collection of heterogeneous printable entries: could be representing either instructions,...
TarmacTracerRecord::MemPtr MemPtr
InstRecord * getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, const PCStateBase &pc, const StaticInstPtr macroStaticInst=nullptr) override
Generates a TarmacTracerRecord, depending on the Tarmac version.
std::vector< RegPtr > regQueue
TarmacTracer(const Params &p)
std::unique_ptr< Printable > PEntryPtr
TarmacTracerRecord::InstPtr InstPtr
std::vector< MemPtr > memQueue
TarmacTracerParams Params
Tick startTick
startTick and endTick allow to trace a specific window of ticks rather than the entire CPU execution.
STL vector class.
Definition stl.hh:37
Bitfield< 4 > pc
Bitfield< 0 > p
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Tick
Tick count type.
Definition types.hh:58

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