gem5 v24.0.0.0
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TarmacTracer record for ARMv8 CPUs: The record is adding some data to the base TarmacTracer record. More...
#include <tarmac_record_v8.hh>
Classes | |
struct | TraceEntryV8 |
General data shared by all v8 entries. More... | |
struct | TraceInstEntryV8 |
Instruction entry for v8 records. More... | |
struct | TraceMemEntryV8 |
Memory Entry for V8. More... | |
struct | TraceRegEntryV8 |
Register entry for v8 records. More... | |
Public Member Functions | |
TarmacTracerRecordV8 (Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, const PCStateBase &_pc, TarmacTracer &_parent, const StaticInstPtr _macroStaticInst=NULL) | |
Public Member Functions inherited from gem5::trace::TarmacTracerRecord | |
TarmacTracerRecord (Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, const PCStateBase &_pc, TarmacTracer &_tracer, const StaticInstPtr _macroStaticInst=NULL) | |
virtual void | dump () override |
Public Member Functions inherited from gem5::trace::TarmacBaseRecord | |
TarmacBaseRecord (Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, const PCStateBase &_pc, const StaticInstPtr _macroStaticInst=nullptr) | |
Public Member Functions inherited from gem5::trace::InstRecord | |
InstRecord (Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, const PCStateBase &_pc, const StaticInstPtr _macroStaticInst=nullptr) | |
virtual | ~InstRecord () |
void | setWhen (Tick new_when) |
void | setMem (Addr a, Addr s, unsigned f) |
template<typename T , size_t N> | |
void | setData (std::array< T, N > d) |
void | setData (uint64_t d) |
void | setData (uint32_t d) |
void | setData (uint16_t d) |
void | setData (uint8_t d) |
void | setData (int64_t d) |
void | setData (int32_t d) |
void | setData (int16_t d) |
void | setData (int8_t d) |
void | setData (double d) |
void | setData (const RegClass ®_class, RegVal val) |
void | setData (const RegClass ®_class, const void *val) |
void | setFetchSeq (InstSeqNum seq) |
void | setCPSeq (InstSeqNum seq) |
void | setPredicate (bool val) |
void | setFaulting (bool val) |
Tick | getWhen () const |
ThreadContext * | getThread () const |
StaticInstPtr | getStaticInst () const |
const PCStateBase & | getPCState () const |
StaticInstPtr | getMacroStaticInst () const |
Addr | getAddr () const |
Addr | getSize () const |
unsigned | getFlags () const |
bool | getMemValid () const |
uint64_t | getIntData () const |
double | getFloatData () const |
int | getDataStatus () const |
InstSeqNum | getFetchSeq () const |
bool | getFetchSeqValid () const |
InstSeqNum | getCpSeq () const |
bool | getCpSeqValid () const |
bool | getFaulting () const |
Protected Member Functions | |
void | addInstEntry (std::vector< InstPtr > &queue, const TarmacContext &ptr) |
Generates an Entry for the executed instruction. | |
void | addMemEntry (std::vector< MemPtr > &queue, const TarmacContext &ptr) |
Generates an Entry for every memory access triggered. | |
void | addRegEntry (std::vector< RegPtr > &queue, const TarmacContext &ptr) |
Generate a Record for every register being written. | |
Protected Member Functions inherited from gem5::trace::TarmacTracerRecord | |
template<typename RegEntry > | |
RegEntry | genRegister (const TarmacContext &tarmCtx, const RegId ®) |
Generate and update a register entry. | |
template<typename RegEntry > | |
void | mergeCCEntry (std::vector< RegPtr > &queue, const TarmacContext &tarmCtx) |
template<typename Queue > | |
void | flushQueues (Queue &queue) |
Flush queues to the trace output. | |
template<typename Queue , typename... Args> | |
void | flushQueues (Queue &queue, Args &... args) |
Additional Inherited Members | |
Public Types inherited from gem5::trace::TarmacTracerRecord | |
using | InstPtr = std::unique_ptr<TraceInstEntry> |
using | MemPtr = std::unique_ptr<TraceMemEntry> |
using | RegPtr = std::unique_ptr<TraceRegEntry> |
Public Types inherited from gem5::trace::TarmacBaseRecord | |
enum | TarmacRecordType { TARMAC_INST , TARMAC_REG , TARMAC_MEM , TARMAC_UNSUPPORTED } |
TARMAC trace record type. More... | |
enum | ISetState { ISET_ARM , ISET_THUMB , ISET_A64 , ISET_UNSUPPORTED } |
ARM instruction set state. More... | |
enum | RegType { REG_R , REG_X , REG_S , REG_D , REG_P , REG_Q , REG_Z , REG_MISC } |
ARM register type. More... | |
Static Public Member Functions inherited from gem5::trace::TarmacBaseRecord | |
static ISetState | pcToISetState (const PCStateBase &pc) |
Returns the Instruction Set State according to the current PCState. | |
Protected Types inherited from gem5::trace::InstRecord | |
enum | DataStatus { DataInvalid = 0 , DataInt8 = 1 , DataInt16 = 2 , DataInt32 = 4 , DataInt64 = 8 , DataDouble = 3 , DataReg = 5 } |
What size of data was written? More... | |
Protected Attributes inherited from gem5::trace::TarmacTracerRecord | |
TarmacTracer & | tracer |
Reference to tracer. | |
Protected Attributes inherited from gem5::trace::InstRecord | |
Tick | when |
ThreadContext * | thread |
StaticInstPtr | staticInst |
std::unique_ptr< PCStateBase > | pc |
StaticInstPtr | macroStaticInst |
Addr | addr = 0 |
The address that was accessed. | |
Addr | size = 0 |
The size of the memory request. | |
unsigned | flags = 0 |
The flags that were assigned to the request. | |
union gem5::trace::InstRecord::Data | data |
InstSeqNum | fetch_seq = 0 |
InstSeqNum | cp_seq = 0 |
enum gem5::trace::InstRecord::DataStatus | dataStatus = DataInvalid |
bool | mem_valid = false |
Are the memory fields in the record valid? | |
bool | fetch_seq_valid = false |
Are the fetch sequence number fields valid? | |
bool | cp_seq_valid = false |
Are the commit sequence number fields valid? | |
bool | predicate = true |
is the predicate for execution this inst true or false (not execed)? | |
bool | faulting = false |
Did the execution of this instruction fault? (requires ExecFaulting to be enabled) | |
TarmacTracer record for ARMv8 CPUs: The record is adding some data to the base TarmacTracer record.
Definition at line 58 of file tarmac_record_v8.hh.
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inline |
Definition at line 142 of file tarmac_record_v8.hh.
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protectedvirtual |
Generates an Entry for the executed instruction.
Reimplemented from gem5::trace::TarmacTracerRecord.
Definition at line 176 of file tarmac_record_v8.cc.
References gem5::trace::InstRecord::predicate.
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protectedvirtual |
Generates an Entry for every memory access triggered.
Reimplemented from gem5::trace::TarmacTracerRecord.
Definition at line 187 of file tarmac_record_v8.cc.
References gem5::trace::InstRecord::getAddr(), gem5::trace::InstRecord::getIntData(), gem5::trace::InstRecord::getMemValid(), and gem5::trace::InstRecord::getSize().
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protectedvirtual |
Generate a Record for every register being written.
Reimplemented from gem5::trace::TarmacTracerRecord.
Definition at line 203 of file tarmac_record_v8.cc.
References gem5::StaticInst::destRegIdx(), gem5::trace::TarmacTracerRecord::genRegister(), gem5::trace::TarmacTracerRecord::mergeCCEntry(), gem5::StaticInst::numDestRegs(), gem5::X86ISA::reg, and gem5::trace::InstRecord::staticInst.