gem5 v24.0.0.0
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tarmac_tracer.cc
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1/*
2 * Copyright (c) 2017-2018, 2022 Arm Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include "tarmac_tracer.hh"
39
40#include <string>
41
42#include "arch/arm/system.hh"
43#include "base/output.hh"
44#include "cpu/base.hh"
45
46#include "enums/TarmacDump.hh"
47
48namespace gem5
49{
50
51namespace trace {
52
53std::string
55{
56 auto id = thread->getCpuPtr()->cpuId();
57 return "cpu" + std::to_string(id);
58}
59
60namespace {
61
63tarmacDump(const TarmacTracerParams &p)
64{
65 switch (p.outfile) {
66 case TarmacDump::stdoutput:
67 return simout.findOrCreate("stdout");
68 case TarmacDump::stderror:
69 return simout.findOrCreate("stderr");
70 case TarmacDump::file:
71 return simout.findOrCreate(p.name);
72 default:
73 panic("Invalid option\n");
74 }
75}
76
77}
78
80 : InstTracer(p),
81 outstream(tarmacDump(p)),
82 startTick(p.start_tick),
83 endTick(p.end_tick)
84{
85 // Wrong parameter setting: The trace end happens before the
86 // trace start.
88 "Tarmac start point: %lu is bigger than "
89 "Tarmac end point: %lu\n", startTick, endTick);
90
91 // By default cpu tracers in gem5 are not tracing faults
92 // (exceptions).
93 // This is not in compliance with the Tarmac specification:
94 // instructions like SVC, SMC, HVC have to be traced.
95 // Tarmac Tracer is then automatically enabling this behaviour.
96 setDebugFlag("ExecFaulting");
97}
98
101 const StaticInstPtr staticInst,
102 const PCStateBase &pc,
103 const StaticInstPtr macroStaticInst)
104{
105 // Check if we need to start tracing since we have passed the
106 // tick start point.
107 if (when < startTick || when > endTick)
108 return nullptr;
109
110 if (ArmSystem::highestELIs64(tc)) {
111 // TarmacTracerV8
112 return new TarmacTracerRecordV8(when, tc, staticInst, pc, *this,
113 macroStaticInst);
114 } else {
115 // TarmacTracer
116 return new TarmacTracerRecord(when, tc, staticInst, pc, *this,
117 macroStaticInst);
118 }
119}
120
121std::ostream&
123{
124 return *(outstream->stream());
125}
126
127} // namespace trace
128} // namespace gem5
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition system.hh:187
int cpuId() const
Reads this CPU's ID.
Definition base.hh:187
OutputStream * findOrCreate(const std::string &name, bool binary=false)
Definition output.cc:262
std::ostream * stream() const
Get the output underlying output stream.
Definition output.hh:62
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual BaseCPU * getCpuPtr()=0
std::string tarmacCpuName() const
InstRecord * getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, const PCStateBase &pc, const StaticInstPtr macroStaticInst=nullptr) override
Generates a TarmacTracerRecord, depending on the Tarmac version.
TarmacTracer(const Params &p)
friend class TarmacTracerRecordV8
TarmacTracerParams Params
Tick startTick
startTick and endTick allow to trace a specific window of ticks rather than the entire CPU execution.
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition logging.hh:214
Bitfield< 4 > pc
Bitfield< 0 > p
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
void setDebugFlag(const char *string)
Definition debug.cc:193
OutputDirectory simout
Definition output.cc:62
uint64_t Tick
Tick count type.
Definition types.hh:58

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