gem5  v21.1.0.2
tarmac_record_v8.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2017-2019 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
43 #ifndef __ARCH_ARM_TRACERS_TARMAC_RECORD_V8_HH__
44 #define __ARCH_ARM_TRACERS_TARMAC_RECORD_V8_HH__
45 
46 #include "tarmac_record.hh"
47 
48 namespace gem5
49 {
50 
51 namespace Trace {
52 
59 {
60  public:
61 
65  struct TraceEntryV8
66  {
67  public:
68  TraceEntryV8(std::string _cpuName)
69  : cpuName(_cpuName)
70  {}
71 
72  protected:
73  std::string cpuName;
74  };
75 
80  {
81  public:
82  TraceInstEntryV8(const TarmacContext& tarmCtx, bool predicate);
83 
84  virtual void print(std::ostream& outs,
85  int verbosity = 0,
86  const std::string &prefix = "") const override;
87 
88  protected:
90  bool paddrValid;
91  };
92 
97  {
98  public:
99  TraceRegEntryV8(const TarmacContext& tarmCtx, const RegId& reg);
100 
101  virtual void print(std::ostream& outs,
102  int verbosity = 0,
103  const std::string &prefix = "") const override;
104 
105  protected:
106  void updateInt(const TarmacContext& tarmCtx,
107  RegIndex regRelIdx) override;
108 
109  void updateMisc(const TarmacContext& tarmCtx,
110  RegIndex regRelIdx) override;
111 
112  void updateVec(const TarmacContext& tarmCtx,
113  RegIndex regRelIdx) override;
114 
115  void updatePred(const TarmacContext& tarmCtx,
116  RegIndex regRelIdx) override;
117 
125  std::string formatReg() const;
126 
128  uint16_t regWidth;
129  };
130 
135  {
136  public:
137  TraceMemEntryV8(const TarmacContext& tarmCtx,
138  uint8_t _size, Addr _addr, uint64_t _data);
139 
140  virtual void print(std::ostream& outs,
141  int verbosity = 0,
142  const std::string &prefix = "") const override;
143 
144  protected:
146  };
147 
148  public:
150  const StaticInstPtr _staticInst, ArmISA::PCState _pc,
151  TarmacTracer& _parent,
152  const StaticInstPtr _macroStaticInst = NULL)
153  : TarmacTracerRecord(_when, _thread, _staticInst, _pc,
154  _parent, _macroStaticInst)
155  {}
156 
157  protected:
159  void addInstEntry(std::vector<InstPtr>& queue, const TarmacContext& ptr);
160 
162  void addMemEntry(std::vector<MemPtr>& queue, const TarmacContext& ptr);
163 
165  void addRegEntry(std::vector<RegPtr>& queue, const TarmacContext& ptr);
166 };
167 
168 } // namespace Trace
169 } // namespace gem5
170 
171 #endif // __ARCH_ARM_TRACERS_TARMAC_RECORD_V8_HH__
gem5::Trace::TarmacTracerRecordV8::TraceInstEntryV8::paddrValid
bool paddrValid
Definition: tarmac_record_v8.hh:90
gem5::Trace::TarmacTracerRecordV8::TraceMemEntryV8::print
virtual void print(std::ostream &outs, int verbosity=0, const std::string &prefix="") const override
Definition: tarmac_record_v8.cc:269
gem5::Trace::TarmacContext
This object type is encapsulating the informations needed by a Tarmac record to generate it's own ent...
Definition: tarmac_tracer.hh:62
gem5::Trace::TarmacTracerRecordV8::TraceRegEntryV8::regWidth
uint16_t regWidth
Size in bits of arch register.
Definition: tarmac_record_v8.hh:128
gem5::Trace::TarmacTracerRecordV8::addInstEntry
void addInstEntry(std::vector< InstPtr > &queue, const TarmacContext &ptr)
Generates an Entry for the executed instruction.
Definition: tarmac_record_v8.cc:188
gem5::Trace::TarmacTracerRecordV8::TraceMemEntryV8
Memory Entry for V8.
Definition: tarmac_record_v8.hh:134
gem5::Trace::TarmacTracerRecordV8::TraceRegEntryV8::formatReg
std::string formatReg() const
Returning a string which contains the formatted register value: transformed in hex,...
Definition: tarmac_record_v8.cc:305
std::vector< InstPtr >
gem5::Trace::TarmacTracerRecord::TraceMemEntry
Memory Entry.
Definition: tarmac_record.hh:173
gem5::Trace::TarmacTracer
Tarmac Tracer: this tracer generates a new Tarmac Record for every instruction being executed in gem5...
Definition: tarmac_tracer.hh:85
gem5::Trace::TarmacTracerRecordV8::TraceRegEntryV8::updateMisc
void updateMisc(const TarmacContext &tarmCtx, RegIndex regRelIdx) override
Register update functions.
Definition: tarmac_record_v8.cc:124
gem5::RefCountingPtr< StaticInst >
gem5::Trace::TarmacTracerRecordV8::TraceRegEntryV8::print
virtual void print(std::ostream &outs, int verbosity=0, const std::string &prefix="") const override
Definition: tarmac_record_v8.cc:288
gem5::Trace::TarmacTracerRecordV8::addRegEntry
void addRegEntry(std::vector< RegPtr > &queue, const TarmacContext &ptr)
Generate a Record for every register being written.
Definition: tarmac_record_v8.cc:215
gem5::Trace::TarmacTracerRecordV8::TraceEntryV8::TraceEntryV8
TraceEntryV8(std::string _cpuName)
Definition: tarmac_record_v8.hh:68
gem5::Trace::TarmacTracerRecordV8::TraceEntryV8::cpuName
std::string cpuName
Definition: tarmac_record_v8.hh:73
gem5::Trace::TarmacTracerRecordV8::TraceInstEntryV8::print
virtual void print(std::ostream &outs, int verbosity=0, const std::string &prefix="") const override
Definition: tarmac_record_v8.cc:239
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Trace::TarmacTracerRecord
TarmacTracer Record: Record generated by the TarmacTracer for every executed instruction.
Definition: tarmac_record.hh:94
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Trace::TarmacTracerRecordV8::TraceRegEntryV8::TraceRegEntryV8
TraceRegEntryV8(const TarmacContext &tarmCtx, const RegId &reg)
Definition: tarmac_record_v8.cc:83
gem5::Trace::TarmacTracerRecordV8::TraceRegEntryV8::updatePred
void updatePred(const TarmacContext &tarmCtx, RegIndex regRelIdx) override
Definition: tarmac_record_v8.cc:160
gem5::Trace::TarmacTracerRecordV8::TraceInstEntryV8::TraceInstEntryV8
TraceInstEntryV8(const TarmacContext &tarmCtx, bool predicate)
Definition: tarmac_record_v8.cc:53
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Trace::TarmacTracerRecord::TraceInstEntry
Instruction Entry.
Definition: tarmac_record.hh:98
gem5::Trace::TarmacTracerRecordV8::TraceRegEntryV8::updateVec
void updateVec(const TarmacContext &tarmCtx, RegIndex regRelIdx) override
Definition: tarmac_record_v8.cc:135
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
tarmac_record.hh
gem5::Trace::TarmacTracerRecordV8::TraceMemEntryV8::TraceMemEntryV8
TraceMemEntryV8(const TarmacContext &tarmCtx, uint8_t _size, Addr _addr, uint64_t _data)
Definition: tarmac_record_v8.cc:69
gem5::Trace::InstRecord::predicate
bool predicate
is the predicate for execution this inst true or false (not execed)?
Definition: insttracer.hh:148
gem5::Trace::TarmacTracerRecordV8
TarmacTracer record for ARMv8 CPUs: The record is adding some data to the base TarmacTracer record.
Definition: tarmac_record_v8.hh:58
gem5::Trace::TarmacTracerRecordV8::TraceEntryV8
General data shared by all v8 entries.
Definition: tarmac_record_v8.hh:65
gem5::Trace::TarmacTracerRecordV8::addMemEntry
void addMemEntry(std::vector< MemPtr > &queue, const TarmacContext &ptr)
Generates an Entry for every memory access triggered.
Definition: tarmac_record_v8.cc:199
gem5::Trace::TarmacTracerRecordV8::TraceInstEntryV8::paddr
Addr paddr
Definition: tarmac_record_v8.hh:89
gem5::Trace::TarmacTracerRecord::TraceRegEntry
Register Entry.
Definition: tarmac_record.hh:121
gem5::Trace::TarmacTracerRecordV8::TraceRegEntryV8::updateInt
void updateInt(const TarmacContext &tarmCtx, RegIndex regRelIdx) override
Definition: tarmac_record_v8.cc:93
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::Trace::TarmacTracerRecordV8::TraceMemEntryV8::paddr
Addr paddr
Definition: tarmac_record_v8.hh:145
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Trace::TarmacTracerRecordV8::TarmacTracerRecordV8
TarmacTracerRecordV8(Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, ArmISA::PCState _pc, TarmacTracer &_parent, const StaticInstPtr _macroStaticInst=NULL)
Definition: tarmac_record_v8.hh:149
gem5::Trace::TarmacTracerRecordV8::TraceInstEntryV8
Instruction entry for v8 records.
Definition: tarmac_record_v8.hh:79
gem5::Trace::TarmacTracerRecordV8::TraceRegEntryV8
Register entry for v8 records.
Definition: tarmac_record_v8.hh:96
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88

Generated on Tue Sep 21 2021 12:24:46 for gem5 by doxygen 1.8.17