gem5  v21.1.0.2
tarmac_record.hh
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37 
43 #ifndef __ARCH_ARM_TRACERS_TARMAC_RECORD_HH__
44 #define __ARCH_ARM_TRACERS_TARMAC_RECORD_HH__
45 
46 #include <memory>
47 
48 #include "arch/arm/regs/misc.hh"
50 #include "base/printable.hh"
51 #include "cpu/reg_class.hh"
52 #include "cpu/static_inst.hh"
53 
54 namespace gem5
55 {
56 
57 namespace Trace {
58 
59 class TarmacContext;
60 
61 class TarmacTracer;
62 
71 std::string
73 
81 std::string
83 
95 {
96  public:
99  {
100  TraceInstEntry(const TarmacContext& tarmCtx, bool predicate);
101 
102  virtual void print(std::ostream& outs,
103  int verbosity = 0,
104  const std::string &prefix = "") const override;
105 
106  protected:
108  static uint64_t instCount;
109 
117  uint8_t instSize;
118  };
119 
122  {
123  public:
124  TraceRegEntry(const TarmacContext& tarmCtx, const RegId& reg);
125 
135  void update(const TarmacContext& tarmCtx);
136 
137  virtual void print(std::ostream& outs,
138  int verbosity = 0,
139  const std::string &prefix = "") const override;
140 
141  protected:
143  virtual void
144  updateMisc(const TarmacContext& tarmCtx, RegIndex regRelIdx);
145 
146  virtual void
147  updateCC(const TarmacContext& tarmCtx, RegIndex regRelIdx);
148 
149  virtual void
150  updateFloat(const TarmacContext& tarmCtx, RegIndex regRelIdx);
151 
152  virtual void
153  updateInt(const TarmacContext& tarmCtx, RegIndex regRelIdx);
154 
155  virtual void
156  updateVec(const TarmacContext& tarmCtx, RegIndex regRelIdx) {};
157 
158  virtual void
159  updatePred(const TarmacContext& tarmCtx, RegIndex regRelIdx) {};
160 
161  public:
163  bool regValid;
169  std::string regName;
170  };
171 
174  {
175  public:
176  TraceMemEntry(const TarmacContext& tarmCtx,
177  uint8_t _size, Addr _addr, uint64_t _data);
178 
179  virtual void print(std::ostream& outs,
180  int verbosity = 0,
181  const std::string &prefix = "") const override;
182 
183  protected:
186  };
187 
188  public:
189  TarmacTracerRecord(Tick _when, ThreadContext *_thread,
190  const StaticInstPtr _staticInst, ArmISA::PCState _pc,
191  TarmacTracer& _tracer,
192  const StaticInstPtr _macroStaticInst = NULL);
193 
194  virtual void dump() override;
195 
196  using InstPtr = std::unique_ptr<TraceInstEntry>;
197  using MemPtr = std::unique_ptr<TraceMemEntry>;
198  using RegPtr = std::unique_ptr<TraceRegEntry>;
199 
200  protected:
202  virtual void addInstEntry(std::vector<InstPtr>& queue,
203  const TarmacContext& ptr);
204 
206  virtual void addMemEntry(std::vector<MemPtr>& queue,
207  const TarmacContext& ptr);
208 
210  virtual void addRegEntry(std::vector<RegPtr>& queue,
211  const TarmacContext& ptr);
212 
213  protected:
215  template<typename RegEntry>
216  RegEntry
217  genRegister(const TarmacContext& tarmCtx, const RegId& reg)
218  {
219  RegEntry single_reg(tarmCtx, reg);
220  single_reg.update(tarmCtx);
221 
222  return single_reg;
223  }
224 
225  template<typename RegEntry>
226  void
228  {
229  // Find all CC Entries and move them at the end of the queue
230  auto it = std::remove_if(
231  queue.begin(), queue.end(),
232  [] (RegPtr& reg) ->bool { return (reg->regClass == CCRegClass); }
233  );
234 
235  if (it != queue.end()) {
236  // Remove all CC Entries.
237  queue.erase(it, queue.end());
238 
239  auto is_cpsr = [] (RegPtr& reg) ->bool
240  {
241  return (reg->regClass == MiscRegClass) &&
242  (reg->regRel == ArmISA::MISCREG_CPSR);
243  };
244 
245  // Looking for the presence of a CPSR register entry.
246  auto cpsr_it = std::find_if(
247  queue.begin(), queue.end(), is_cpsr
248  );
249 
250  // If CPSR entry not present, generate one
251  if (cpsr_it == queue.end()) {
253  queue.push_back(
254  std::make_unique<RegEntry>(
255  genRegister<RegEntry>(tarmCtx, reg))
256  );
257  }
258  }
259  }
260 
262  template<typename Queue>
263  void flushQueues(Queue& queue);
264  template<typename Queue, typename... Args>
265  void flushQueues(Queue& queue, Args & ... args);
266 
267  protected:
270 };
271 
272 } // namespace Trace
273 } // namespace gem5
274 
275 #endif // __ARCH_ARM_TRACERS_TARMAC_RECORD_HH__
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::Trace::iSetStateToStr
std::string iSetStateToStr(TarmacBaseRecord::ISetState isetstate)
Returns the string representation of the instruction set being currently run according to the Tarmac ...
Definition: tarmac_record.cc:56
gem5::Trace::TarmacTracerRecord::InstPtr
std::unique_ptr< TraceInstEntry > InstPtr
Definition: tarmac_record.hh:196
gem5::Trace::TarmacContext
This object type is encapsulating the informations needed by a Tarmac record to generate it's own ent...
Definition: tarmac_tracer.hh:62
gem5::Trace::TarmacTracerRecord::TraceRegEntry::regValid
bool regValid
True if register entry is valid.
Definition: tarmac_record.hh:159
gem5::RegClass
RegClass
Enumerate the classes of registers.
Definition: reg_class.hh:55
gem5::Trace::TarmacTracerRecord::mergeCCEntry
void mergeCCEntry(std::vector< RegPtr > &queue, const TarmacContext &tarmCtx)
Definition: tarmac_record.hh:227
gem5::Trace::TarmacTracerRecord::TraceInstEntry::TraceInstEntry
TraceInstEntry(const TarmacContext &tarmCtx, bool predicate)
Definition: tarmac_record.cc:123
gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateCC
virtual void updateCC(const TarmacContext &tarmCtx, RegIndex regRelIdx)
Definition: tarmac_record.cc:227
gem5::Trace::TarmacBaseRecord
Definition: tarmac_base.hh:64
gem5::Trace::TarmacTracerRecord::TraceInstEntry::secureMode
bool secureMode
True if instruction is executed in secure mode.
Definition: tarmac_record.hh:111
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
std::vector< InstPtr >
gem5::Trace::TarmacTracerRecord::TraceRegEntry::regName
std::string regName
Register name to be printed.
Definition: tarmac_record.hh:169
gem5::Trace::TarmacTracerRecord::TraceMemEntry
Memory Entry.
Definition: tarmac_record.hh:173
tarmac_base.hh
gem5::Trace::TarmacTracerRecord::TraceMemEntry::loadAccess
bool loadAccess
True if memory access is a load.
Definition: tarmac_record.hh:185
gem5::Trace::TarmacTracer
Tarmac Tracer: this tracer generates a new Tarmac Record for every instruction being executed in gem5...
Definition: tarmac_tracer.hh:85
gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateMisc
virtual void updateMisc(const TarmacContext &tarmCtx, RegIndex regRelIdx)
Register update functions.
Definition: tarmac_record.cc:200
printable.hh
gem5::RefCountingPtr< StaticInst >
gem5::Printable
Abstract base class for objects which support being printed to a stream for debugging.
Definition: printable.hh:47
gem5::Trace::TarmacTracerRecord::TraceMemEntry::print
virtual void print(std::ostream &outs, int verbosity=0, const std::string &prefix="") const override
Definition: tarmac_record.cc:435
gem5::Trace::TarmacBaseRecord::ISetState
ISetState
ARM instruction set state.
Definition: tarmac_base.hh:77
gem5::Trace::TarmacTracerRecord::tracer
TarmacTracer & tracer
Reference to tracer.
Definition: tarmac_record.hh:269
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Trace::TarmacBaseRecord::InstEntry
TARMAC instruction trace record.
Definition: tarmac_base.hh:84
gem5::Trace::TarmacTracerRecord::TraceRegEntry::TraceRegEntry
TraceRegEntry(const TarmacContext &tarmCtx, const RegId &reg)
Definition: tarmac_record.cc:156
gem5::Trace::TarmacTracerRecord
TarmacTracer Record: Record generated by the TarmacTracer for every executed instruction.
Definition: tarmac_record.hh:94
gem5::Trace::TarmacTracerRecord::dump
virtual void dump() override
Definition: tarmac_record.cc:344
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Trace::TarmacTracerRecord::TraceRegEntry::updatePred
virtual void updatePred(const TarmacContext &tarmCtx, RegIndex regRelIdx)
Definition: tarmac_record.hh:159
gem5::Trace::TarmacTracerRecord::TraceRegEntry::regRel
RegIndex regRel
Register arch number.
Definition: tarmac_record.hh:167
gem5::Trace::TarmacBaseRecord::RegEntry
TARMAC register trace record.
Definition: tarmac_base.hh:101
gem5::Trace::TarmacTracerRecord::addInstEntry
virtual void addInstEntry(std::vector< InstPtr > &queue, const TarmacContext &ptr)
Generates an Entry for the executed instruction.
Definition: tarmac_record.cc:293
gem5::Trace::TarmacTracerRecord::genRegister
RegEntry genRegister(const TarmacContext &tarmCtx, const RegId &reg)
Generate and update a register entry.
Definition: tarmac_record.hh:217
static_inst.hh
gem5::Queue
A high-level queue interface, to be used by both the MSHR queue and the write buffer.
Definition: queue.hh:70
gem5::Trace::TarmacTracerRecord::TraceRegEntry::regClass
RegClass regClass
Register class.
Definition: tarmac_record.hh:165
gem5::Trace::TarmacTracerRecord::addMemEntry
virtual void addMemEntry(std::vector< MemPtr > &queue, const TarmacContext &ptr)
Generates an Entry for every triggered memory access.
Definition: tarmac_record.cc:304
gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateInt
virtual void updateInt(const TarmacContext &tarmCtx, RegIndex regRelIdx)
Definition: tarmac_record.cc:253
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Trace::TarmacTracerRecord::TraceInstEntry
Instruction Entry.
Definition: tarmac_record.hh:98
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::Trace::TarmacTracerRecord::TraceMemEntry::TraceMemEntry
TraceMemEntry(const TarmacContext &tarmCtx, uint8_t _size, Addr _addr, uint64_t _data)
Definition: tarmac_record.cc:148
gem5::Trace::TarmacTracerRecord::addRegEntry
virtual void addRegEntry(std::vector< RegPtr > &queue, const TarmacContext &ptr)
Generate an Entry for every register being written.
Definition: tarmac_record.cc:320
gem5::Trace::InstRecord::predicate
bool predicate
is the predicate for execution this inst true or false (not execed)?
Definition: insttracer.hh:148
gem5::Trace::TarmacTracerRecord::TarmacTracerRecord
TarmacTracerRecord(Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, ArmISA::PCState _pc, TarmacTracer &_tracer, const StaticInstPtr _macroStaticInst=NULL)
Definition: tarmac_record.cc:112
gem5::Trace::TarmacTracerRecord::TraceInstEntry::instCount
static uint64_t instCount
Number of instructions being traced.
Definition: tarmac_record.hh:108
gem5::Trace::TarmacTracerRecord::TraceRegEntry::print
virtual void print(std::ostream &outs, int verbosity=0, const std::string &prefix="") const override
Definition: tarmac_record.cc:452
misc.hh
gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateVec
virtual void updateVec(const TarmacContext &tarmCtx, RegIndex regRelIdx)
Definition: tarmac_record.hh:156
gem5::Trace::TarmacBaseRecord::MemEntry
TARMAC memory access trace record (stores only).
Definition: tarmac_base.hh:121
reg_class.hh
gem5::Trace::TarmacTracerRecord::MemPtr
std::unique_ptr< TraceMemEntry > MemPtr
Definition: tarmac_record.hh:197
gem5::Trace::TarmacTracerRecord::TraceRegEntry
Register Entry.
Definition: tarmac_record.hh:121
gem5::Trace::TarmacTracerRecord::flushQueues
void flushQueues(Queue &queue)
Flush queues to the trace output.
Definition: tarmac_record.cc:392
gem5::Trace::opModeToStr
std::string opModeToStr(OperatingMode opMode)
Returns the string representation of the ARM Operating Mode (CPSR.M[3:0] field) according to the Tarm...
Definition: tarmac_record.cc:71
gem5::Trace::TarmacTracerRecord::RegPtr
std::unique_ptr< TraceRegEntry > RegPtr
Definition: tarmac_record.hh:198
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateFloat
virtual void updateFloat(const TarmacContext &tarmCtx, RegIndex regRelIdx)
Definition: tarmac_record.cc:240
gem5::Trace::TarmacTracerRecord::TraceRegEntry::update
void update(const TarmacContext &tarmCtx)
This updates the register entry using the update table.
Definition: tarmac_record.cc:167
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Trace::TarmacTracerRecord::TraceInstEntry::instSize
uint8_t instSize
Instruction size: 16 for 16-bit Thumb Instruction 32 otherwise (ARM and BigThumb)
Definition: tarmac_record.hh:117
gem5::Trace::TarmacTracerRecord::TraceInstEntry::print
virtual void print(std::ostream &outs, int verbosity=0, const std::string &prefix="") const override
Definition: tarmac_record.cc:412
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88

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