gem5 v24.0.0.0
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tport.cc
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1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
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26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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39 */
40
41#include "mem/tport.hh"
42#include "sim/sim_object.hh"
43
44namespace gem5
45{
46
47SimpleTimingPort::SimpleTimingPort(const std::string& _name,
48 SimObject* _owner) :
49 QueuedResponsePort(_name, queueImpl), queueImpl(*_owner, *this)
50{
51}
52
53void
55{
57 // do an atomic access and throw away the returned latency
58 recvAtomic(pkt);
59 }
60}
61
62bool
64{
65 // the SimpleTimingPort should not be used anywhere where there is
66 // a need to deal with snoop responses and their flow control
67 // requirements
68 if (pkt->cacheResponding())
69 panic("SimpleTimingPort should never see packets with the "
70 "cacheResponding flag set\n");
71
72 bool needsResponse = pkt->needsResponse();
73 Tick latency = recvAtomic(pkt);
74 // turn packet around to go back to requestor if response expected
75 if (needsResponse) {
76 // recvAtomic() should already have turned packet into
77 // atomic response
78 assert(pkt->isResponse());
79 schedTimingResp(pkt, curTick() + latency);
80 } else {
81 // queue the packet for deletion
82 pendingDelete.reset(pkt);
83 }
84
85 return true;
86}
87
88} // namespace gem5
bool trySatisfyFunctional(PacketPtr pkt)
Check the list of buffered packets against the supplied functional request.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
bool isResponse() const
Definition packet.hh:598
bool needsResponse() const
Definition packet.hh:608
bool cacheResponding() const
Definition packet.hh:659
A queued port is a port that has an infinite queue for outgoing packets and thus decouples the module...
Definition qport.hh:62
RespPacketQueue & respQueue
Packet queue used to store outgoing responses.
Definition qport.hh:67
void schedTimingResp(PacketPtr pkt, Tick when)
Schedule the sending of a timing response.
Definition qport.hh:94
Abstract superclass for simulation objects.
SimpleTimingPort(const std::string &name, SimObject *owner)
Create a new SimpleTimingPort that relies on a packet queue to hold responses, and implements recvTim...
Definition tport.cc:47
void recvFunctional(PacketPtr pkt)
Implemented using recvAtomic().
Definition tport.cc:54
std::unique_ptr< Packet > pendingDelete
Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent c...
Definition tport.hh:89
virtual Tick recvAtomic(PacketPtr pkt)=0
Receive an atomic request packet from the peer.
bool recvTimingReq(PacketPtr pkt)
Implemented using recvAtomic().
Definition tport.cc:63
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
Tick curTick()
The universal simulation clock.
Definition cur_tick.hh:46
uint64_t Tick
Tick count type.
Definition types.hh:58
Declaration of SimpleTimingPort.

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